KR100443515B1 - method for manufacturing via hole - Google Patents
method for manufacturing via hole Download PDFInfo
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- KR100443515B1 KR100443515B1 KR10-2001-0084161A KR20010084161A KR100443515B1 KR 100443515 B1 KR100443515 B1 KR 100443515B1 KR 20010084161 A KR20010084161 A KR 20010084161A KR 100443515 B1 KR100443515 B1 KR 100443515B1
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- via hole
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title description 3
- 230000004888 barrier function Effects 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 claims description 12
- 229910002091 carbon monoxide Inorganic materials 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 4
- 230000009977 dual effect Effects 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 23
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010943 off-gassing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 셀프어라인(self aligned) 듀얼 다마신(dual damascene) 공정에서 트렌치 식각 시에 발생되는 비아홀(via hole)의 상단부가 커지는 현상을 방지할 수 있는 비아홀 형성 방법에 관해 개시한다.The present invention discloses a method of forming a via hole capable of preventing a phenomenon in which an upper end portion of a via hole generated during trench etching in a self-aligned dual damascene process increases.
개시된 본 발명의 비아홀 형성 방법은 도전층을 포함한 반도체기판 상에 무기절연막 및 베리어막을 차례로 형성하는 단계와, 베리어막 상에 도전층의 일부를 노출시키는 제 1감광막 패턴을 형성하는 단계와, 제 1감광막 패턴을 마스크로 하고 무기절연막 및 베리어막을 식각하여 비아홀을 형성하는 단계와, 제 1감광막 패턴을 제거하는 단계와, 베리어막 상에 비아홀을 채우는 유기절연막을 형성하는 단계와, 유기절연막 상에 적어도 비아홀과 대응된 부분을 노출시키는 제 2감광막 패턴을 형성하는 단계와, 제 2감광막 패턴을 마스크로 하고 유기절연막을 식각하여 트렌치를 형성하는 단계와, 제 2감광막 패턴을 제거하는 단계를 포함한다.The disclosed via hole forming method of the present invention comprises the steps of sequentially forming an inorganic insulating film and a barrier film on a semiconductor substrate including a conductive layer, forming a first photoresist film pattern exposing a portion of the conductive layer on the barrier film; Forming a via hole by etching the inorganic insulating film and the barrier film using the photosensitive film pattern as a mask, removing the first photosensitive film pattern, forming an organic insulating film filling the via hole on the barrier film, and at least on the organic insulating film. Forming a second photoresist pattern that exposes a portion corresponding to the via hole, forming a trench by etching the organic insulation layer using the second photoresist pattern as a mask, and removing the second photoresist pattern.
Description
본 발명은 반도체장치의 제조 방법에 관한 것으로, 보다 상세하게는 셀프어라인(self aligned) 듀얼 다마신(dual damascene) 공정에서 트렌치 식각 시에 발생되는 비아홀(via hole)의 상단부가 커지는 현상을 방지할 수 있는 비아홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to prevent a phenomenon in which an upper end portion of a via hole generated during trench etching occurs in a self-aligned dual damascene process. It relates to a method for forming via holes.
반도체 제조 공정에 있어서, 소자의 속도를 향상시키기 위해, 즉 캐패시턴스(capacitance)을 감소시키기 위해 금속 배선과 금속 배선을 절연시키는 막으로, 저 유전 상수값을 가진 절연막(Inter Metal Dielectric layer)을 사용하고 있는 추세이다.In the semiconductor manufacturing process, an inter-metal dielectric layer having a low dielectric constant value is used as a film to insulate the metal wiring from the metal wiring in order to improve the speed of the device, that is, reduce the capacitance. There is a trend.
이러한 저유전 상수값을 가진 절연막은 대부분 유기(organic) 계통의 물질이 대부분이나, 상기 유기 물질의 열적 특성 상 아웃게싱(outgassing)의 문제가 있다.The insulating film having such a low dielectric constant value is mostly organic material, but there is a problem of outgassing due to the thermal properties of the organic material.
따라서, 이러한 아웃게싱을 방지하기 위해 주로 저유전 상수값을 가진 절연막 하부에 기생 캐패시턴스 감소 및 상기 절연막과의 접착력을 향상시키기 위한 베리어막을 개재시킨다.Therefore, in order to prevent such outgassing, a barrier film is disposed in the lower part of the insulating film having a low dielectric constant value to reduce parasitic capacitance and improve adhesion to the insulating film.
도 1a 내지 도 1d는 종래 기술에 따른 비아홀 형성 방법을 설명하기 위한 공정단면도이다.1A through 1D are cross-sectional views illustrating a method of forming a via hole according to the related art.
종래 기술에 따른 비아홀 형성 방법은, 도 1a에 도시된 바와 같이, 먼저 반도체기판(100) 상에 금속 배선 형성용 제 1도전막(102), 제 1실리콘 질화막(104), 제 1유기절연막(106) 및 제 2실리콘 질화막(110)을 차례로 형성한다.In the method of forming a via hole according to the related art, as shown in FIG. 1A, first, a first conductive layer 102, a first silicon nitride layer 104, and a first organic insulating layer 104 for forming a metal wiring on a semiconductor substrate 100 are formed. 106 and the second silicon nitride film 110 are formed in this order.
이어서, 상기 제 2실리콘 질화막(110) 상에 제 1도전막(102)과 대응된 일부분을 노출시키는 제 1감광막 패턴(130)을 형성한다.Subsequently, a first photoresist layer pattern 130 exposing a portion corresponding to the first conductive layer 102 is formed on the second silicon nitride layer 110.
그 다음, 도 1b에 도시된 바와 같이, 상기 제 1감광막 패턴을 마스크로 하고 상기 제 2실리콘 질화막을 제거하여 제 1개구부를 형성한다. 이때, 잔류된 제 2실리콘 질화막이 베리어막(111)으로서의 역할을 한다.Next, as shown in FIG. 1B, the first photoresist pattern is used as a mask, and the second silicon nitride layer is removed to form a first opening. At this time, the remaining second silicon nitride film serves as the barrier film 111.
이 후, 제 1감광막 패턴을 제거하고 나서, 도 1c에 도시된 바와 같이, 상기 베리어막(111)을 포함한 제 1유기절연막(106) 상에 제 2유기절연막(116) 및 제 3실리콘 질화막(118)을 차례로 형성한다. 이때, 제 3실리콘 질화막(118) 및 제 1실리콘 질화막(104)는 확산방지막의 역할을 한다.Subsequently, after the first photoresist layer pattern is removed, as shown in FIG. 1C, the second organic insulation layer 116 and the third silicon nitride layer may be formed on the first organic insulation layer 106 including the barrier layer 111. 118) are formed sequentially. At this time, the third silicon nitride film 118 and the first silicon nitride film 104 serve as a diffusion barrier.
이어, 상기 제 3실리콘 질화막(118) 상에 적어도 제 1개구부(112)을 포함한 부분을 노출시키는 제 2감광막 패턴(132)을 형성한다. 이때, 상기 제 1 및 제 2유기절연막(106)(116)로는 유전 상수값이 낮은(유전상수값이 2.5 이하) 유기 물질을 사용한다.Next, a second photoresist layer pattern 132 exposing at least a portion including the first opening 112 is formed on the third silicon nitride layer 118. In this case, an organic material having a low dielectric constant (dielectric constant value of 2.5 or less) is used as the first and second organic insulating films 106 and 116.
그 다음, 도 1d에 도시된 바와 같이, 제 2감광막 패턴을 식각마스크로 하고 제 3실리콘 질화막 및 제 2유기절연막을 제거하여 베리어막(111)을 노출시키는 제 2개구부(120)를 형성함과 동시에 상기 베리어막(111)을 식각마스크로 하고 상기 제 1유기절연막(106) 및 제 1실리콘 질화막을 제거하여 제 1도전막(102)을 노출시키는 비아홀(122)을 형성한다.Next, as illustrated in FIG. 1D, the second photoresist pattern is used as an etch mask, and the third silicon nitride layer and the second organic insulating layer are removed to form the second opening 120 exposing the barrier layer 111. At the same time, the barrier layer 111 is used as an etch mask, and the first organic insulating layer 106 and the first silicon nitride layer are removed to form a via hole 122 exposing the first conductive layer 102.
이 후, 도면에 도시되어 있지는 않지만, 제 2감광막 패턴을 제거하고, 비아홀 및 제 2개구부를 채워 제 1도전막과 연결되는 제 2도전막을 형성한다.Thereafter, although not shown in the drawing, the second photosensitive film pattern is removed, and the second conductive film is formed to be connected to the first conductive film by filling the via hole and the second opening.
도 2는 종래 기술에 따른 문제점을 도시한 공정단면도로, 점선처리된 부분은 이론치의 비아홀을 도시한 것이다.Figure 2 is a process cross-sectional view showing a problem according to the prior art, the dotted line shows the via hole of the theoretical value.
그러나, 종래 기술에서는, 도 2에 도시된 바와 같이, 제 2개구부 및 비아홀형성을 위한 식각 공정 시, 식각선택비 차이에 의해 비아홀 상단부분의 베리어막이 깨져서 제 1유기절연막이 식각되어 비아홀의 크기가 커지는 문제점이 있었다. (A 참조)However, in the prior art, as shown in FIG. 2, in the etching process for forming the second opening and the via hole, the barrier film in the upper portion of the via hole is broken due to the difference in etching selectivity, so that the first organic insulating layer is etched to increase the size of the via hole. There was a growing problem. (See A)
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 셀프어라인 다마신 공정에서, 비아홀 형성을 위한 식각 공정 시, 원하는 크기의 비아홀을 형성할 수 있는 비아홀 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, the object of the present invention is to provide a via hole forming method that can form a via hole of a desired size during the etching process for forming a via hole in a self-aligned damascene process. have.
도 1a 내지 도 1d는 종래 기술에 따른 비아홀 형성 방법을 설명하기 위한 공정단면도.1A to 1D are cross-sectional views illustrating a method of forming a via hole according to the related art.
도 2는 종래 기술에 따른 문제점을 도시한 공정단면도.Figure 2 is a process cross-sectional view showing a problem according to the prior art.
도 3a 내지 도 3d는 본 발명에 따른 비아홀 형성 방법을 설명하기 위한 공정단면도.3A to 3D are cross-sectional views illustrating a method of forming a via hole according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
200. 반도체기판 202. 도전막200. Semiconductor substrate 202. Conductive film
204, 210, 216. 실리콘 질화막 206. 무기절연막204, 210, 216. Silicon nitride film 206. Inorganic insulating film
207. 비아홀 211. 베리어막207. Via Hole 211. Barrier Films
214. 유기절연막 215. 개구부214. Organic insulating film 215. Opening
230, 232. 감광막 패턴230, 232. Photoresist pattern
상기 목적을 달성하기 위한 본 발명의 비아홀 형성 방법은 도전층을 포함한 반도체기판 상에 무기절연막 및 베리어막을 차례로 형성하는 단계와, 베리어막 상에 도전층의 일부를 노출시키는 제 1감광막 패턴을 형성하는 단계와, 제 1감광막 패턴을 마스크로 하고 무기절연막 및 베리어막을 식각하여 비아홀을 형성하는 단계와, 제 1감광막 패턴을 제거하는 단계와, 베리어막 상에 비아홀을 채우는 유기절연막을 형성하는 단계와, 유기절연막 상에 적어도 비아홀과 대응된 부분을 노출시키는 제 2감광막 패턴을 형성하는 단계와, 제 2감광막 패턴을 마스크로 하고 유기절연막을 식각하여 트렌치를 형성하는 단계와, 제 2감광막 패턴을 제거하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, a method of forming a via hole according to the present invention includes sequentially forming an inorganic insulating film and a barrier film on a semiconductor substrate including a conductive layer, and forming a first photosensitive film pattern exposing a portion of the conductive layer on the barrier film. Forming a via hole by etching the inorganic insulating film and the barrier film using the first photosensitive film pattern as a mask, removing the first photosensitive film pattern, and forming an organic insulating film filling the via hole on the barrier film; Forming a second photoresist pattern on the organic insulating layer to expose at least a portion corresponding to the via hole, forming a trench by etching the organic insulation layer using the second photoresist pattern as a mask, and removing the second photoresist pattern Characterized in that it comprises a step.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3e는 본 발명에 따른 비아홀 형성 방법을 설명하기 위한 공정단면도이다.3A to 3E are cross-sectional views illustrating a method of forming a via hole according to the present invention.
본 발명의 비아홀 형성 방법은, 도 3a에 도시된 바와 같이, 먼저, 반도체기판(200) 상에 알루미늄(AL), 텅스텐(W), 구리(Cu) 등의 제 1도전막(202)을 형성한 후, 상기 제 1도전막(202) 상에 제 1실리콘 질화막(204), 무기절연막(206), 제 2실리콘 질화막(210)을 차례로 형성한다. 이때, 상기 제 1실리콘 질화막(204)은 확산방지막으로서의 역할을 한다.In the method of forming a via hole of the present invention, as shown in FIG. 3A, first, a first conductive film 202 of aluminum (AL), tungsten (W), copper (Cu), or the like is formed on a semiconductor substrate 200. Thereafter, a first silicon nitride film 204, an inorganic insulating film 206, and a second silicon nitride film 210 are sequentially formed on the first conductive film 202. In this case, the first silicon nitride film 204 serves as a diffusion barrier.
이어서, 상기 제 2실리콘 질화막(210) 상에 감광막을 도포하고 노광 및 현상하여 상기 제 1도전막과 대응된 일부분을 노출시키는 제 1감광막 패턴(230)을 형성한다.Subsequently, a photoresist layer is coated on the second silicon nitride layer 210, and the photoresist layer is exposed and developed to form a first photoresist layer pattern 230 exposing a portion corresponding to the first conductive layer.
그 다음, 도 3b에 도시된 바와 같이, 상기 제 1감광막 패턴을 마스크로 하고 제 2실리콘 질화막, 무기절연막 및 제 1실리콘 질화막을 식각하여 비아홀(207)을 형성하고 나서, 제 1감광막 패턴을 제거한다. 이때, 상기 잔류된 제 2실리콘 질화막은 베리어막(211)으로서의 역할을 한다. 또한, 상기 무기절연막 식각 공정은 CX 3B, the via photoresist pattern is formed by etching the second silicon nitride film, the inorganic insulating film, and the first silicon nitride film using the first photoresist pattern as a mask, and then remove the first photoresist pattern. do. In this case, the remaining second silicon nitride film serves as the barrier film 211. In addition, the inorganic insulating film etching process is C X
HYFZ(CF4, C2F6, C4F8또는 C5F8중 어느 하나), O2, N2및 H2계통의 식각 가스를 이용하고, 보조가스로 CO, Ar 가스를 사용한다.H Y F Z (any one of CF 4 , C 2 F 6 , C 4 F 8, or C 5 F 8 ), O 2 , N 2 and H 2 system etching gas, CO, Ar gas as an auxiliary gas Use
이어서, 도 3c에 도시된 바와 같이, 베리어막(211)을 포함한 결과물 상에 유기절연막(214) 및 제 3실리콘 질화막(216)을 형성하고 나서, 상기 제 3실리콘 질화막(216) 상에 적어도 비아홀(207)을 포함한 부분을 노출시키는 제 2감광막 패턴(232)을 형성한다. 이때, 상기 제 3실리콘 질화막(216)은 확산방지막으로서의 역할을 한다.Subsequently, as shown in FIG. 3C, the organic insulating film 214 and the third silicon nitride film 216 are formed on the resultant including the barrier film 211, and then at least via holes on the third silicon nitride film 216. A second photosensitive film pattern 232 exposing a portion including 207 is formed. In this case, the third silicon nitride film 216 serves as a diffusion barrier.
그 다음, 도 3d에 도시된 바와 같이, 상기 제 2감광막 패턴을 마스크로 하고 상기 제 3실리콘 질화막 및 유기절연막을 제거하여 개구부(215)를 형성하고 나서, 저유전 상수값을 갖는 유기절연막 전용 식각 장비 내에서 비아홀(207) 내의 유기절연막을 제거하는 작업을 실시한다. 이때, 상기 비아홀(207)내에 잔류된 유기절연막은 하나의 식각장비 내에서 인시튜(in-situ) 제 2감광막 패턴을 제거하면서 함께 제거할 수도 있다.Next, as shown in FIG. 3D, the second photoresist film pattern is used as a mask, and the third silicon nitride film and the organic insulating film are removed to form the openings 215, and then the organic insulating film-only etching having a low dielectric constant value is performed. The operation of removing the organic insulating film in the via hole 207 is performed in the equipment. In this case, the organic insulating layer remaining in the via hole 207 may be removed together while removing the in-situ second photoresist layer pattern in one etching apparatus.
따라서, B처럼 베리어막이 깨졌음에도 불구하고 무기절연막이 거의 손상되지 않아 비아홀의 크기가 켜지지 않았다.Therefore, even though the barrier film was broken like B, the inorganic insulating film was hardly damaged and the size of the via hole was not turned on.
상기 유기절연막 식각 공정은 O2및 N2를 주 식각가스로 이용하고, 보조 가스로 C2H4, Ar 및 SO2가스를 이용한다.In the organic insulating layer etching process, O 2 and N 2 are used as main etching gases, and C 2 H 4 , Ar, and SO 2 gases are used as auxiliary gases.
이 후, 도면에는 도시되어 있지는 않지만, 상기 비아홀 및 개구부를 채워 제 1도전막과 연결되는 제 2도전막을 형성한다.Thereafter, although not shown in the drawing, the via hole and the opening are filled to form a second conductive film connected to the first conductive film.
이상에서와 같이, 본 발명의 방법에서는 베리어막을 이용하여 무기절연막을 식각하여 비아홀을 형성한 후, 유기절연막을 증착 및 식각함으로써, 상기 유기절연막 식각 공정 시, 비아홀 상단부의 베리어막이 깨져도 식각 대상 물질인 유기절연막과 다른 성분의 무기절연막이 드러나게 되므로 비아홀의 크기에는 영향을 미치지 않는다.As described above, in the method of the present invention, an inorganic insulating layer is etched using a barrier film to form a via hole, and then an organic insulating film is deposited and etched, so that the material to be etched even when the barrier film at the top of the via hole is broken during the organic insulating film etching process. Since the organic insulating film and the inorganic insulating film of other components are exposed, the size of the via hole is not affected.
따라서, 본 발명에서는 베리어막의 손상에 관계없이 원하는 크기의 비아홀을형성할 수 있다.Therefore, in the present invention, via holes having a desired size can be formed regardless of damage to the barrier film.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (7)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000010202A1 (en) * | 1998-08-12 | 2000-02-24 | Applied Materials, Inc. | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics |
| JP2000091422A (en) * | 1998-09-16 | 2000-03-31 | Sony Corp | Manufacture of multilayer wiring structure |
| JP2000188330A (en) * | 1998-12-21 | 2000-07-04 | Nec Corp | Formation of dual-damascene wire |
| KR20010005049A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Improved dual damascene process in semiconductor device |
| KR20020008614A (en) * | 2000-07-24 | 2002-01-31 | 황인길 | Method for forming metal line of semiconductor devices utilizing dual damascene process |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000010202A1 (en) * | 1998-08-12 | 2000-02-24 | Applied Materials, Inc. | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics |
| JP2000091422A (en) * | 1998-09-16 | 2000-03-31 | Sony Corp | Manufacture of multilayer wiring structure |
| JP2000188330A (en) * | 1998-12-21 | 2000-07-04 | Nec Corp | Formation of dual-damascene wire |
| KR20010005049A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Improved dual damascene process in semiconductor device |
| KR20020008614A (en) * | 2000-07-24 | 2002-01-31 | 황인길 | Method for forming metal line of semiconductor devices utilizing dual damascene process |
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