KR20020055302A - Method of forming a copper wiring in a semiconductor device - Google Patents
Method of forming a copper wiring in a semiconductor device Download PDFInfo
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- KR20020055302A KR20020055302A KR1020000084726A KR20000084726A KR20020055302A KR 20020055302 A KR20020055302 A KR 20020055302A KR 1020000084726 A KR1020000084726 A KR 1020000084726A KR 20000084726 A KR20000084726 A KR 20000084726A KR 20020055302 A KR20020055302 A KR 20020055302A
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- copper
- barrier metal
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 97
- 239000010949 copper Substances 0.000 title claims abstract description 85
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 229910008482 TiSiN Inorganic materials 0.000 claims abstract description 3
- 230000009977 dual effect Effects 0.000 claims abstract description 3
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims abstract description 3
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 22
- 229910052739 hydrogen Inorganic materials 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 238000005240 physical vapour deposition Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 61
- 230000007547 defect Effects 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 3
- -1 copper metals Chemical class 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 229910004156 TaNx Inorganic materials 0.000 description 15
- 239000007789 gas Substances 0.000 description 11
- 238000000151 deposition Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000011065 in-situ storage Methods 0.000 description 5
- 238000000879 optical micrograph Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 특히, 절연막 패턴 상부에 1차 장벽 금속층(barrier metal)을 증착하고 대기중에 노출시키거나 기체 분위기에서 열처리를 실시한 후 2차 장벽 금속층을 형성함으로써 장벽 특성을 향상시키는 동시에 구리 (111) 방향성(texture)을 발달시켜 구리 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device, and in particular, by depositing a primary barrier metal layer on an insulating film pattern, exposing it to air, or performing heat treatment in a gas atmosphere, thereby forming a secondary barrier metal layer. The present invention relates to a method for forming a copper wiring of a semiconductor device that can improve the barrier properties and at the same time develop copper (111) texture to improve the reliability of the copper wiring.
반도체 소자의 금속 배선 재료로 알루미늄을 사용할 경우 알루미늄은 절연막으로 사용되는 실리콘 산화막(SiO2)으로의 확산이 전혀 일어나지 않기 때문에 측벽에 장벽 금속층이 증착되지 않아도 된다. 그런데, 구리는 알루미늄과는 달리 층간 절연막으로 사용되는 실리콘 산화막으로 확산되며, 층간 절연막을 통해 확산된 구리는 실리콘내에서 깊은 준위(deep level)로 존재하게 된다. 즉, 구리는 실리콘내에서 깊은 준위(deep level) 도펀트로 작용하여 실리콘의 금지대(forbidden band)내에 여러개의 어셉터(acceptor)와 도우너 (donor) 준위를 형성시킨다. 이들 깊은 준위가 생성(generation)-재조합 (recombination)의 소오스(source)로 작용하여 누설 전류(leakage current)를 발생시키고, 이에 의해 소자가 파괴된다. 따라서, 구리를 배선 공정에 도입하려면 이종 금속과 접촉하는 기저부(bottom) 뿐만 아니라측벽(side wall)의 절연 재료에 대한 장벽 금속이 필요하다.When aluminum is used as the metal wiring material of the semiconductor device, aluminum does not have to be deposited on the sidewall because no diffusion into the silicon oxide film (SiO 2 ) used as the insulating film occurs. However, unlike aluminum, copper diffuses into a silicon oxide film used as an interlayer insulating film, and copper diffused through the interlayer insulating film exists at a deep level in silicon. In other words, copper acts as a deep level dopant in silicon to form multiple acceptor and donor levels within the forbidden band of silicon. These deep levels act as a source of generation-recombination, resulting in leakage currents, thereby destroying the device. Thus, the introduction of copper into the wiring process requires a barrier metal not only for the bottom in contact with the dissimilar metal, but also for the insulating material of the side walls.
구리 배선 공정은 IC 회로의 크기가 축소함에 따라 사용이 불가피해지는 공정이므로 깊은 콘택(deep contact) 또는 트렌치 패턴(trench pattern)에 적용된다. 또한, 장벽 금속층 증착 공정의 한계성으로 인하여 스텝 커버리지가 점차 나빠지므로 기저부 또는 측벽에 증착되는 장벽 금속층의 두께는 점점 얇아지게 되고, 구리 배선의 유효 저항을 높이지 않기 위해서라도 장벽 금속층의 두께에는 제한이 따르게 된다. 예를 들어 현재 실용화 단계에 있는 HCM(hollow cathode magnetron) TaNx, IMP(ion metal plasma) TaNx와 같은 개선된 이온화(advanced ionized) PVD 방식으로 증착된 장벽 금속층의 경우 측벽의 스텝 커버리지가 10%를 넘지 않으므로 장벽 금속층의 두께는 30Å을 넘지 않는다. 또한, PVD 방식의 한계점으로 인하여 CVD 방식으로 장벽 금속층을 증착한다 하더라도 ITRS(International Technology Roadmap for Semiconductor)에 따르면 0.07㎛ 이하에서는 장벽 금속층에 허용되는 두께가 최대 30Å정도인 것으로 예상하고 있다. 따라서, 구리에 대한 장벽 금속층의 역할을 수행하려면 장벽 금속층의 내부가 그레인 바운더리(grain boundary)와 같은 결함이 전혀 없는 완벽한 비정질 구조가 되어야 하는데, 이와 같은 막을 제조하는 것은 거의 불가능하다.The copper wiring process is applied to deep contact or trench patterns because it is inevitable to use as the size of the IC circuit is reduced. In addition, due to the limitation of the barrier metal layer deposition process, the step coverage is gradually worsened, so that the thickness of the barrier metal layer deposited on the base or sidewall becomes thinner, and the thickness of the barrier metal layer is limited even in order not to increase the effective resistance of the copper wiring. Will follow. For example, the barrier metal layers deposited by advanced ionized PVD methods, such as hollow cathode magnetron (HCM) TaNx and ion metal plasma (IMP) TaNx, which are currently in practical use, have a step coverage of more than 10%. Therefore, the thickness of the barrier metal layer does not exceed 30 kPa. In addition, due to the limitations of the PVD method, even when the barrier metal layer is deposited by CVD, it is expected that the thickness of the barrier metal layer is allowed to be at most 30 μm at 0.07 μm or less according to the International Technology Roadmap for Semiconductor (ITRS). Thus, to serve as a barrier metal layer for copper, the interior of the barrier metal layer must be a complete amorphous structure, free of defects such as grain boundaries, which is almost impossible to manufacture.
한편, PVD 방식으로 장벽 금속층을 증착할 때 현재 실용화 단계에 있는 HCM TaNx, IMP TaNx 등과 같은 재료들도 완전한 비결정질 구조가 아닌 단결정의 결정질 구조를 가지고 있으므로 막의 두께가 매우 얇을 경우 장벽 특성의 약화가 쉽게 예상된다. 단지 이를 평가하기 위한 방식으로 표준화된 것이 없을 따름이다.On the other hand, when the barrier metal layer is deposited by PVD method, HCM TaNx, IMP TaNx, etc., which are in practical use, also have a single crystalline structure instead of a complete amorphous structure, so that the barrier property is easily weakened when the film thickness is very thin. It is expected. There is nothing standardized just to assess this.
본 발명의 목적은 결함이 존재하지 않는 장벽 금속층을 형성함으로써 구리 배선을 증착하는 동안에 층간 절연막을 통한 구리의 확산을 방지할 수 있는 반도체 소자의 구리 배선 형성 방법을 제공하는데 있다.An object of the present invention is to provide a method for forming a copper wiring of a semiconductor device which can prevent diffusion of copper through an interlayer insulating film during deposition of copper wiring by forming a barrier metal layer free of defects.
본 발명의 다른 목적은 구리 (111) 방향성을 발달시켜 구리 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법을 제공하는데 있다.Another object of the present invention is to provide a copper wiring formation method of a semiconductor device capable of improving the copper wiring reliability by developing copper (111) orientation.
구리에 대한 장벽 금속층의 역할을 수행하려면 장벽 금속층 내부는 그레인 바운더리와 같은 결함이 전혀 없는 완벽한 비정질 구조가 되어야 한다. 그러나 구리 배선 공정에 적용될 장벽 금속층은 대부분 나노결정(nanocrystalline) 구조를 갖게 되는데, 이들의 두께가 수십Å 이하로 매우 얇아질 경우는 미세한 그레인 바운더리가 결함의 역할을 할 수 있기 때문에 구리에 대한 장벽 금속층으로써 적합하지 않게 된다. 따라서, 장벽 금속층을 증착한 후 대기중에 노출시키거나 기체 분위기에서 열처리 공정을 실시하여 결함이 존재하는 부분을 O, C, H 등의 원자들로 채움으로써 장벽 능력을 향상시킨다.To act as a barrier metal layer for copper, the barrier metal layer interior must be a complete amorphous structure free of defects such as grain boundaries. However, most of the barrier metal layers to be applied to the copper wiring process have a nanocrystalline structure, and when the thickness thereof becomes very thin (less than a few tens of micrometers), the fine grain boundary can act as a defect, so the barrier metal layer to copper This makes it unsuitable. Accordingly, the barrier capability is improved by filling the portion in which defects are present with atoms such as O, C, and H by depositing the barrier metal layer and exposing it to the atmosphere or performing a heat treatment process in a gas atmosphere.
기존의 알루미늄 배선 공정에서는 주상정 구조를 갖는 TiN의 표면을 공기중에 노출시켜 표면 및 결정 계면에 Ti-N-O를 형성시킴으로써 장벽으로써의 역할을 향상시키는 것이 알려져 있으며 실용화되어 있다(산소 스터핑(Oxegen Stuffing) 효과). 이와 같은 TiN을 구리 배선 공정에 적용할 경우에는 장벽 금속으로써의 산소 스터핑 효과가 없는 것으로 보고되었다. 그러나, 이는 TiN을 구리와 실리콘의 계면에 수백∼수천Å의 두께로 매우 두껍게 증착시켜 고온(500∼800℃)에서 실리콘과 구리의 반응성 여부를 통해 장벽 금속층을 평가한 것이므로 신뢰성이 없는 결과이다. 실제로 구리 배선 공정의 경우에는 알루미늄 배선 공정과는 달리 고온 공정을 수반하지 않기 때문에(최대 450℃를 넘지 않는다) 공기중에 노출되었을 때 장벽 금속층 표면 또는 결함등에 흡착되어 있거나 결합되어 있는 O, H, C, N 등은 구리 원자 또는 이온의 이동을 막게 된다. 즉, 구리 배선 공정의 가용 온도(450℃ 이하)에서는 원자들의 진동(vibration)이 크지 않기 때문에 알루미늄에서와 같은 산소 스터핑 효과를 적용시킬 수 있게 된다.In the existing aluminum wiring process, it is known and practically used to improve the role as a barrier by exposing the surface of TiN having a columnar structure to air to form Ti-NO at the surface and crystal interface (Oxegen Stuffing). effect). When TiN is applied to a copper wiring process, it is reported that there is no oxygen stuffing effect as a barrier metal. However, this is an unreliable result because TiN was deposited very thickly at the interface between copper and silicon at a thickness of several hundreds to thousands of micrometers, and the barrier metal layer was evaluated by reactivity of silicon and copper at a high temperature (500-800 ° C.). In fact, the copper wiring process does not involve a high temperature process (not exceeding 450 ° C) unlike the aluminum wiring process, so that it is adsorbed or bonded to the barrier metal layer surface or defects when exposed to air. , N and the like prevent the movement of copper atoms or ions. That is, since the vibration of atoms is not large at the available temperature (450 ° C. or lower) of the copper wiring process, the oxygen stuffing effect as in aluminum can be applied.
한편, 장벽 금속층을 증착한 후 인시투로 구리 시드층을 증착하는 경우는 구리 (111) 방향성이 잘 발달하지만, 장벽 금속층을 증착한 후 일단 공기에 노출되거나 또는 그 밖의 방식으로 표면 처리를 하는 경우에는 표면에 산화물과 같은 비정질층이 형성되므로 후속 공정에서 구리 (111) 방향성은 매우 약하게 된다. 구리 (111) 방향성이 좋으면 구리 배선의 EM 특성이 향상되는 것으로 알려져 있다.On the other hand, when the copper seed layer is deposited in-situ after the barrier metal layer is deposited, the copper (111) orientation is well developed, but once the barrier metal layer is deposited, it is exposed to air or subjected to surface treatment in another manner. Since the amorphous layer such as oxide is formed on the surface, the copper (111) directivity becomes very weak in a subsequent process. It is known that EM characteristic of a copper wiring will improve if copper (111) orientation is good.
장벽 금속층을 증착한 후 대기중에 노출시키거나 기체 분위기에서 열처리를 실시하면 장벽 금속층의 매우 미세한 결함들이 O, H, C, N 등의 미세한 원자들로 채워지기 때문에 구리 원자 또는 구리 이온들의 절연막으로의 확산을 막을 수 있게 된다. 그러나, 장벽 금속층의 표면 처리로 인해 표면에 형성된 비정질막은 구리 (111) 방향성의 발달을 저해하므로 EM 특성이 매우 취약하게 된다. 따라서, 표면 처리된 장벽 금속층 위에 다시 장벽 금속층을 증착한 후 인시투로 구리를 증착한다면 구리 (111) 방향성이 발달하게 된다. 특히, 구리 배선의 선폭이 매우 좁은 경우에는 배선 내부의 구리가 랜덤 구조를 갖게 되는데, 이는 후속 열처리 공정을 통하여 해결할 수 있다. 즉, 배선 내부는 구리 랜덤 구조를 갖지만 패턴 이외의 영역은 구리 (111) 방향성을 갖기 때문에 열처리할 경우 배선 내부가 구리 (111) 방향성을 갖도록 재결정된다.When the barrier metal layer is deposited and then exposed to the atmosphere or subjected to heat treatment in a gaseous atmosphere, very fine defects of the barrier metal layer are filled with fine atoms such as O, H, C, N, and the like. This can prevent the spread. However, the amorphous film formed on the surface due to the surface treatment of the barrier metal layer inhibits the development of the copper (111) directionality, which makes the EM characteristic very weak. Therefore, if the barrier metal layer is deposited on the surface-treated barrier metal layer and then copper is deposited in-situ, the copper (111) orientation is developed. In particular, when the line width of the copper wiring is very narrow, the copper inside the wiring has a random structure, which can be solved through a subsequent heat treatment process. That is, since the inside of the wiring has a copper random structure, but the region other than the pattern has the copper (111) orientation, when the heat treatment is performed, the inside of the wiring is recrystallized to have the copper (111) orientation.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of devices sequentially shown in order to explain a method for forming a copper wiring of a semiconductor device according to the present invention.
도 2는 장벽 금속층의 대기중 노출 여부에 따른 구리 (111) 방향성을 나타낸 XRD 피크 프로파일.Figure 2 is an XRD peak profile showing the copper (111) orientation according to whether the barrier metal layer is exposed to the atmosphere.
도 3(a) 및 도 3(b)는 0.5㎛ 폭의 트랜치 선에 TaNx를 증착한 후 구리를 인시투로 증착하고 열처리한 경우의 평면 및 단면 SEM 사진.3 (a) and 3 (b) are planar and cross-sectional SEM photographs when TaNx is deposited on a 0.5 µm wide trench line and copper is deposited in-situ and then heat-treated.
도 4, 도 5 및 도 6은 장벽 금속층을 형성한 후의 대기 노출 여부 및 2차 장벽 금속층 두께에 따른 소자의 특성을 나타낸 광학 현미경 사진.4, 5 and 6 are optical micrographs showing the characteristics of the device according to the atmospheric exposure and the thickness of the secondary barrier metal layer after forming the barrier metal layer.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판12 : 절연막11 semiconductor substrate 12 insulating film
13A : 1차 장벽 금속층13B : 비정질층13A: primary barrier metal layer 13B: amorphous layer
13C : 2차 장벽 금속층14 : 구리 배선13C: secondary barrier metal layer 14: copper wiring
본 발명에 따른 반도체 소자의 구리 배선 형성 방법은 소정의 구조가 형성된 반도체 기판 상부에 절연막을 형성한 후 상기 절연막을 패터닝하여 상기 반도체 기판의 소정 영역을 노출시키는 단계와, 전체 구조 상부에 1차 장벽 금속층을 형성한 후 대기중에 노출시키는 단계와, 전체 구조 상부에 2차 장벽 금속층을 형성한 후 구리층을 형성하는 단계와, 상기 구리층 및 상기 장벽 금속층을 연마하여 구리 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The method for forming a copper wiring of a semiconductor device according to the present invention includes forming an insulating film on a semiconductor substrate having a predetermined structure, patterning the insulating film to expose a predetermined region of the semiconductor substrate, and forming a first barrier on the entire structure. Forming a metal layer and exposing it to the atmosphere; forming a second barrier metal layer over the entire structure, and then forming a copper layer; and polishing the copper layer and the barrier metal layer to form a copper wiring. Characterized in that made.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a method for forming a copper wiring of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 절연막(12)을 형성한다. 싱글 또는 듀얼 다마신(damascene) 공정을 실시하여 절연막(12)을 패터닝한다. 절연막 패턴을 포함한 전체 구조 상부에 1차 장벽금속층(13A)을 형성한다. 이때 사용되는 장벽 금속층은 CVD 또는 PVD 방식으로 증착된 Ta막, TaN막, WN막, TiN막, TiW막, TiSiN막, WBN막 및 WC막중 어느 하나를 20∼500Å의 두께로 형성한다.Referring to FIG. 1A, an insulating film 12 is formed on a semiconductor substrate 11 having a predetermined structure. The insulating film 12 is patterned by performing a single or dual damascene process. The primary barrier metal layer 13A is formed on the entire structure including the insulating film pattern. The barrier metal layer used at this time forms any one of a Ta film, a TaN film, a WN film, a TiN film, a TiW film, a TiSiN film, a WBN film, and a WC film deposited by CVD or PVD in a thickness of 20 to 500 mW.
도 1(b)를 참조하면, 1차 장벽 금속층(13A)을 대기중에 노출시키거나 기체 분위기에서 열처리하여 1차 장벽 금속층(13A) 표면에 비정질층(13B)을 형성한다. 이때, 대기중에 노출시키는 위해서는 0℃∼100℃의 온도와 10∼80%의 습도를 유지하는 대기중에 1초∼10시간동안 노출시킨다. 또한, 열처리는 150℃∼450℃의 온도에서 1분∼10시간동안 반응로 열처리를 실시하거나, 250℃∼500℃의 온도에서 1초∼20분동안 급속 열처리를 실시한다. 이러한 열처리는 N2, Ar 및 H2중 어느 하나의 분위기에서 실시하거나 N2와 H2의 혼합 기체, Ar과 H2의 혼합 기체, Ar과 N2의 혼합 기체중 어느 하나의 혼합 기체 분위기에서 실시한다. 한편, 상기 열처리는 1차 장벽 금속층(13A)을 형성한 후 동일 챔버내에 Ar, O2, N2, NH3중 어느 하나 또는 그들의 혼합 기체를 유입시켜 실시하는데, 이때의 챔버 내부의 압력은 1 mTorr∼10Torr가 되도록 유지한다.Referring to FIG. 1 (b), the amorphous primary layer 13B is formed on the surface of the primary barrier metal layer 13A by exposing the primary barrier metal layer 13A to the air or by heat treatment in a gaseous atmosphere. At this time, in order to expose to air, it exposes for 1 second-10 hours in the atmosphere which keeps the temperature of 0 degreeC-100 degreeC, and 10-80% humidity. In addition, the heat treatment is performed by the reaction furnace heat treatment for 1 minute to 10 hours at a temperature of 150 ℃ to 450 ℃, or rapid heat treatment for 1 second to 20 minutes at a temperature of 250 ℃ to 500 ℃. This heat treatment may be performed in any one of N 2 , Ar, and H 2 , or in a mixed gas atmosphere of any of N 2 and H 2 , a gas of Ar and H 2 , and a gas of Ar and N 2 . Conduct. On the other hand, the heat treatment is performed by introducing any one of Ar, O 2 , N 2 , NH 3 or their mixed gas into the same chamber after forming the primary barrier metal layer 13A, wherein the pressure inside the chamber is 1 Keep to mTorr to 10 Torr.
도 1(c)는 전체 구조 상부에 2차 장벽 금속층(13C)을 20∼500Å의 두께로 형성한 상태의 단면도이다.FIG. 1C is a cross-sectional view of the secondary barrier metal layer 13C having a thickness of 20 to 500 kPa on the entire structure.
도 1(d)를 참조하면, 진공 파괴 없이 PVD 방식 또는 CVD 방식으로 50∼1500Å 두께의 구리 시드층(도시안됨)을 증착한다. 무전해 도금 방식, 전해 도금 방식, PVD 또는 CVD 방식으로 다마신 패턴이 매립되도록 구리층을 형성한다. 구리층을 형성한 후 N2, Ar, H2중 어느 하나의 분위기 또는 N2와 H2의 혼합 기체, Ar과 H2의 혼합 기체, Ar과 N2의 혼합 기체중 어느 하나의 혼합 기체 분위기에서 24시간 이내의 열처리를 수행하는데, 바람직하게는 200∼500℃의 온도에서 10초∼30분동안 실시한다. 그리고, 연마 공정을 실시하여 구리 배선(14)을 형성한다.Referring to FIG. 1 (d), a copper seed layer (not shown) having a thickness of 50 to 1500 mW is deposited by PVD or CVD without vacuum breakage. The copper layer is formed to embed the damascene pattern by electroless plating, electrolytic plating, PVD, or CVD. After forming the copper layer, N 2, Ar, H 2 of any one of the atmospheric or N 2 and the mixture gas of H 2, Ar and H 2 mixed gas, Ar and N 2 any one of the mixed gas atmosphere of the mixed gas of the The heat treatment is performed within 24 hours at, preferably 10 seconds to 30 minutes at a temperature of 200 ~ 500 ℃. Then, the polishing step is performed to form the copper wiring 14.
도 2는 장벽 금속층의 대기중 노출 여부에 따른 구리 (111) 방향성을 나타낸 XRD 피크 프로파일이다. 여기서, A는 TaNx를 300Å의 두께로 증착한 후 구리를 1500Å의 두께로 증착한 경우이 방향성을 나타내고, B는 TaNx를 100Å의 두께로 증착하고 대기중에 노출시킨 후 다시 TaNx를 150Å의 두께로 증착하고 구리를 1500Å의 두께로 증착한 경우의 방향성을 나타낸다. 한편, C는 TaNx를 300Å의 두께로 증착하고 대기중에 노출시킨 후 구리를 1500Å의 두께로 증착한 경우의 방향성을 나타낸다. A, B 및 C를 비교하면 알 수 있듯이 구리를 증착하기 전에 공기에 노출시킨 경우는 구리 (111) 피크의 세기가 매우 약하다. 그러나 장벽 특성을 향상시키기 위해 TaNx을 증착한 후 대기중에 노출시키고 다시 TaNx를 증착한 후 인시투로 구리를 증착한 경우는 매우 강한 구리 (111) 방향성을 갖는다.FIG. 2 is an XRD peak profile showing copper (111) orientation according to whether the barrier metal layer is exposed to the atmosphere. Here, A represents the directionality when TaNx is deposited to a thickness of 300Å and copper is deposited to a thickness of 1500Å, B shows TaNx to a thickness of 100Å, exposed to the air, and then TaNx is deposited to a thickness of 150Å The orientation when copper is deposited at a thickness of 1500 kPa is shown. On the other hand, C represents the directionality in the case of depositing TaNx at a thickness of 300 kPa and exposing it to air and then depositing copper at a thickness of 1500 kPa. As can be seen from the comparison of A, B and C, the strength of the copper (111) peak is very weak when exposed to air prior to copper deposition. However, in order to improve the barrier properties, when TaNx is deposited and then exposed to the atmosphere, and TaNx is deposited and copper is deposited in-situ, it has a very strong copper (111) orientation.
도 3(a) 및 도 3(b)는 0.5㎛ 폭의 트랜치 선에 TaNx를 300Å의 두께로 증착한 후 구리를 인시투로 증착하고 400℃의 온도로 열처리한 경우의 평면 및 단면 SEM 사진이다. 이때, 기저부의 실리콘과 구리가 반응하여 Cu3Si가 형성되어 부피 팽창으로 막이 들뜨는 현상이 발생된다.3 (a) and 3 (b) are planar and cross-sectional SEM photographs when TaNx is deposited to a thickness of 300 kPa on a 0.5 µm wide trench line, and then copper is deposited in-situ and heat-treated at a temperature of 400 ° C. . At this time, silicon and copper at the base react to form Cu 3 Si, which causes the film to be lifted due to volume expansion.
도 4(a) 및 도 4(b)는 0.7㎛ 및 0.8㎛의 선폭에서 TaNx를 300Å의 두께로 증착한 후 구리를 증착한 경우의 광학 현미경 사진이다. 또한, 도 5(a) 및 도 5(b)는 0.25㎛ 및 0.3㎛의 선폭에서 TaNx를 100Å의 두께로 증착한 후 대기중에 노출시키고, 다시 TaNx를 100Å의 두께로 증착한 후 구리를 증착한 경우의 광학 현미경 사진이다. 한편, 도 5(a) 및 도 5(b)는 0.25㎛ 및 0.3㎛의 선폭에서 TaNx를 100Å의 두께로 증착한 후 대기중에 노출시키고, 다시 TaNx를 150Å의 두께로 증착한 후 구리를 증착한 경우의 광학 현미경 사진이다. 상기 도 4, 도 5 및 도 6 각각의 경우는 450℃의 온도로 30분간 열처리를 했을 때를 나타낸다. 이들을 비교하면, 장벽 금속층을 형성한 후 대기중에 노출시키지 않고 구리를 증착할 경우 장벽 파괴 현상을 보여 하부의 실리콘과의 반응에 의해 Cu3Si가 형성된다. 그러나, 장벽 금속층을 1차로 증착한 후 대기중에 노출시키고 장벽 금속층을 2차로 증착한 후 구리를 증착할 경우 2차 장벽 금속층의 두께에 따라 안정한 장벽 특성을 나타낸다.4 (a) and 4 (b) are optical micrographs when copper was deposited after TaNx was deposited to a thickness of 300 GPa at line widths of 0.7 μm and 0.8 μm. 5 (a) and 5 (b) show that TaNx is deposited to a thickness of 100 GPa at a line width of 0.25 μm and 0.3 μm, and then exposed to the atmosphere. Optical micrograph of the case. Meanwhile, FIGS. 5 (a) and 5 (b) show that TaNx is deposited to a thickness of 100 GPa at a line width of 0.25 μm and 0.3 μm, and then exposed to the atmosphere. Optical micrograph of the case. 4, 5 and 6 show the case where the heat treatment is performed for 30 minutes at the temperature of 450 ° C. In comparison, when the copper is deposited without forming the barrier metal layer and exposed to the air, a barrier fracture phenomenon is observed, and Cu 3 Si is formed by the reaction with the underlying silicon. However, when the barrier metal layer is first deposited and then exposed to the atmosphere, and the barrier metal layer is secondly deposited and copper is deposited, the barrier metal layer exhibits stable barrier properties depending on the thickness of the secondary barrier metal layer.
상술한 바와 같이 본 발명에 의하면 1차 장벽 금속층을 증착한 후 대기중에 노출시키거나 기체 분위기에서 열처리를 실시하여 장벽 특성을 향상시키고, 2차 장벽 금속층을 증착한 후 구리를 증착하여 구리 (111) 방향성을 발달시킴으로써 소자의 신뢰성을 향상시킬 수 있다.As described above, according to the present invention, after depositing the primary barrier metal layer, the barrier property is exposed to air or heat-treated in a gas atmosphere to improve barrier properties, and after depositing the secondary barrier metal layer, copper is deposited to deposit copper (111). By developing the orientation, the reliability of the device can be improved.
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| KR100919378B1 (en) * | 2002-10-28 | 2009-09-25 | 매그나칩 반도체 유한회사 | Metal wiring in a semiconductor device and method of forming the same |
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| US6015749A (en) * | 1998-05-04 | 2000-01-18 | Taiwan Semiconductor Manufacturing Company | Method to improve adhesion between copper and titanium nitride, for copper interconnect structures, via the use of an ion implantation procedure |
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| KR100807066B1 (en) * | 2006-08-31 | 2008-02-25 | 동부일렉트로닉스 주식회사 | Apparatus for manufacturing a semiconductor device and method of manufactruing a semiconductor device using the apparatus |
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