KR20020043780A - Leakage current suppression circuit of DRAM cell - Google Patents

Leakage current suppression circuit of DRAM cell Download PDF

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Publication number
KR20020043780A
KR20020043780A KR1020000072898A KR20000072898A KR20020043780A KR 20020043780 A KR20020043780 A KR 20020043780A KR 1020000072898 A KR1020000072898 A KR 1020000072898A KR 20000072898 A KR20000072898 A KR 20000072898A KR 20020043780 A KR20020043780 A KR 20020043780A
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South Korea
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memory cell
cell array
block
selection signal
block selection
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KR1020000072898A
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Korean (ko)
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김상철
최강식
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000072898A priority Critical patent/KR20020043780A/en
Publication of KR20020043780A publication Critical patent/KR20020043780A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

PURPOSE: A leakage current restraint circuit is provided to improve a cell refresh property by preventing a leakage current. CONSTITUTION: A leakage current restraint circuit comprises a plurality of memory cell array blocks(10,20,30) respectively having a cell transistor and a cell capacitor, a VBB generator(40) receiving a Vcc voltage and outputting a VBB, that is, a back bias voltage, a block selection signal generator(50) supplying one signal out of block selection signals(BS1,BS2,BS3) to the selected memory cell array block out of the memory cell array blocks(10,20,30), and a plurality of VBB transforming part(11,21,31) switching by the block selection signals(BS1,BS2,BS3) and selectively supplying the VBB voltage to the memory cell array block(10,20,30). At this circuit, when the memory cell array block(10) is selected, the other blocks(20,30) are grounded, thereby restraining a leakage current from the standby memory cell array blocks(20,30).

Description

디램 셀의 누설전류 억제 회로{Leakage current suppression circuit of DRAM cell}Leakage current suppression circuit of DRAM cell

본 발명은 디램 셀의 누설전류 억제 회로에 관한 것으로서, 특히, 리드/라이트 동작이 일어나는 셀 블럭에만 백바이어스 전압(Back-Bias voltage, 이하, 'VBB'라 함)을 인가시키고 대기하는 셀 블럭은 간단한 회로를 이용하여 VBB대신 그라운드 처리하여 셀 리프레시 특성을 개선하도록 하는 디램 셀의 누설전류 억제 회로에 관한 것이다.The present invention relates to a leakage current suppression circuit of a DRAM cell. In particular, a cell block applying a back-bias voltage (hereinafter referred to as 'VBB') only to a cell block in which a read / write operation occurs is The present invention relates to a leakage current suppression circuit of a DRAM cell that uses a simple circuit to improve the cell refresh characteristics by grounding instead of VBB.

디램 장치의 집적도가 증가함에 따라 캐패시터의 형성시 셀 캐패시터와 엑티브 영역 사이의 접촉 면적이 감소하는데, 이에 따른 접촉저항 감소를 위하여 접촉부위의 웰 불순물의 농도를 증가시켜야 한다.As the integration degree of the DRAM device increases, the contact area between the cell capacitor and the active region decreases when the capacitor is formed. Accordingly, the concentration of well impurities at the contact portion must be increased to reduce the contact resistance.

또한, 메모리 셀의 워드라인 길이의 감소에 따라 셀 트랜지스터의 채널 누설전류를 억제하기 위해 웰의 불순물 농도를 증가시키고 있다.In addition, as the word line length of the memory cell decreases, the impurity concentration of the well is increased to suppress the channel leakage current of the cell transistor.

그런데, 종래의 디램 메모리 셀은 이러한 캐패시터와 엑티브 영역과의 접촉부위의 농도 증가에 따라 pn접합의 폭 감소에 따른 전기장이 증가하기 때문에 셀 캐패시터의 누설전류가 증가하여 셀의 리프레시 특성을 열화시키게 되는 문제점이 있다.However, in the conventional DRAM memory cell, the electric field increases as the width of the pn junction decreases as the concentration of the contact portion between the capacitor and the active region increases, so that the leakage current of the cell capacitor increases to deteriorate the refresh characteristics of the cell. There is a problem.

또한, 셀 트랜지스터의 경우 트랜지스터 특성확보를 위해 백-바이어스 전압, 즉, VBB를 인가하게 되는데 이러한 VBB의 인가는 셀 캐패시터의 누설전류를 더욱 증가시키는 원인이 된다.In addition, in the case of a cell transistor, a back-bias voltage, that is, VBB, is applied to secure transistor characteristics. The application of VBB causes an increase in leakage current of the cell capacitor.

따라서, 종래의 디램 메모리 셀은 선택적으로 리드/라이트 동작이 일어나는 셀 블럭 뿐만 아니라 대기중인 셀 블럭에도 VBB를 인가하고 있기 때문에, VBB에 의해 셀 캐패시터의 pn 접합의 누설전류가 증가되어 대기중인 셀 리프레시 특성을 감소시키게 되는 문제점이 있다.Therefore, since the conventional DRAM memory cell applies VBB not only to the cell block in which the read / write operation occurs but also to the cell block in standby, the leakage current of the pn junction of the cell capacitor is increased by VBB, thereby refreshing the cell waiting. There is a problem that the characteristics are reduced.

본 발명은 상기와 같은 문제점을 해결하기 위하여 창출된 것으로, 리드/라이트 동작이 일어나는 셀 블럭에만 VBB를 인가시키고 대기하는 셀 블럭은 VBB를 인가하는 대신 그라운드 처리하여 대기중의 누설전류를 억제시킴으로써 셀 리프레시 특성을 개선하도록 하는 디램 셀의 누설전류 억제 회로를 제공함에 그 목적이 있다.The present invention has been made to solve the above problems, the cell block that applies the VBB only to the cell block in which the read / write operation occurs and the cell block by grounding instead of applying the VBB to suppress the leakage current in the cell It is an object of the present invention to provide a leakage current suppression circuit of a DRAM cell to improve refresh characteristics.

도 1은 본 발명에 따른 디램 셀의 누설전류 억제 회로에 관한 회로도.1 is a circuit diagram of a leakage current suppression circuit of a DRAM cell according to the present invention.

〈 도면의 주요 부분에 대한 부호의 설명 〉<Description of the code | symbol about the principal part of drawing>

10 : 메모리 셀 어레이 블럭 11 : 제 1 VBB전환부10: memory cell array block 11: first VBB switching unit

20 : 메모리 셀 어레이 블럭 21 : 제 2 VBB전환부20: memory cell array block 21: second VBB switching unit

30 : 메모리 셀 어레이 블럭 31 : 제 3 VBB전환부30: memory cell array block 31: third VBB switching unit

40 : VBB발생기 50 : 블럭선택신호 발생기40: VBB generator 50: Block selection signal generator

60 : 딜레이 체인부60: delay chain portion

상기 목적을 달성하기 위한 본 발명의 디램 셀의 누설전류 억제 회로는, 셀 캐패시터 및 셀 트랜지스터를 구비한 복수개의 메모리 셀 어레이 블럭과, 복수개의 메모리 셀 어레이 블럭 중 리드 또는 라이트 동작이 이루어지는 메모리 셀 어레이 블럭을 선택하여 블럭선택 신호를 출력하는 블럭 선택신호 발생기와, 복수개의 메모리 셀 어레이 블럭마다 각각 구비되고, 블럭 선택 신호 발생기로부터 인가되는 블럭선택 신호에 따라 선택된 셀 어레이 블럭에만 백바이어스 전압을 인가시키는 복수개의 백바이어스 전압 전환수단 및 블럭 선택신호 발생기로부터 출력된 블럭선택 신호를 일정 시간 딜레이 시켜 선택된 메모리 셀 어레이 블럭에 인가하는 딜레이 체인부를 구비함을 특징으로 한다.A leakage current suppression circuit of a DRAM cell of the present invention for achieving the above object includes a memory cell array block including a cell capacitor and a cell transistor, and a memory cell array in which a read or write operation is performed among the plurality of memory cell array blocks. A block selection signal generator for selecting a block and outputting a block selection signal, and each of the plurality of memory cell array blocks, and applying a back bias voltage to only the selected cell array block according to the block selection signal applied from the block selection signal generator. And a delay chain part for delaying a block selection signal output from the plurality of back bias voltage switching means and the block selection signal generator to a selected memory cell array block for a predetermined time.

이하, 첨부한 도면을 참조하여 본 발명의 실시예에 대해 상세히 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 1은 본 발명에 따른 디램 셀의 누설전류 억제 회로의 회로도이다.1 is a circuit diagram of a leakage current suppression circuit of a DRAM cell according to the present invention.

도 1을 보면, 본 발명의 실시예는 셀 트랜지스터 및 셀 캐패시터를 각각 구비한 복수개의 메모리 셀 어레이 블럭(10,20,30) 및 Vcc전압을 인가받아 백바이어스 전압, VBB를 출력하는 VBB발생기(40)를 구비한다. 그리고, 실시예는 리드/라이트 동작 입력 신호에 따라 메모리 셀 어레이 블럭(10,20,30) 중 어느 하나의 블럭을 선택하는 블럭선택 신호(BS1,BS2,BS3)를 발생하는 블럭선택 신호 발생기(50)를 구비한다. 이 블럭 선택 신호 발생기(50)와 메모리 셀 어레이 블럭(10,20,30) 사이에는 블럭선택 신호 발생기(50)로부터 인가되는 블럭선택 신호에 의해 스위칭 동작하여 백바이어스 전압 VBB를 메모리 셀 어레이 블럭(10,20,30)에 선택적으로 인가하는 제 1 내지 제 3 VBB전환부(11,21,31)를 구비하고 있다.Referring to FIG. 1, an embodiment of the present invention provides a plurality of memory cell array blocks 10, 20, and 30 each having a cell transistor and a cell capacitor, and a VBB generator configured to output a back bias voltage and VBB by receiving Vcc voltage. 40). In addition, the embodiment provides a block selection signal generator for generating block selection signals BS1, BS2, and BS3 for selecting any one of the memory cell array blocks 10, 20, and 30 according to a read / write operation input signal. 50). Between the block select signal generator 50 and the memory cell array blocks 10, 20, and 30, a switching operation is performed by a block select signal applied from the block select signal generator 50 to convert the back bias voltage VBB into a memory cell array block. First to third VBB switching units 11, 21 and 31 are selectively provided to 10, 20 and 30.

여기서, 제 1 내지 제 3 VBB전환부(11,21,31)는 VBB발생기(40)의 출력단과 Vss전압단 사이에 직렬 연결되어, 그 공통 게이트 단자를 통하여 블럭 선택 신호 발생기(50)로부터 인가되는 블럭 선택 신호를 인가받고, 그 공통 드레인 단자는 메모리 셀 어레이 블럭(10,20,30)과 각각 연결된 PMOS트랜지스터(12,22,32) 및 NMOS트랜지스터(13,23,33)로 이루어진다.Here, the first to third VBB switching units 11, 21, and 31 are connected in series between the output terminal of the VBB generator 40 and the Vss voltage terminal, and are applied from the block select signal generator 50 through the common gate terminal thereof. The common drain terminal is composed of PMOS transistors 12, 22, 32 and NMOS transistors 13, 23, 33 connected to the memory cell array blocks 10, 20, and 30, respectively.

또한, 블럭선택 신호 발생기(50)로부터 출력된 블럭 선택 신호는 N개의 인버터 딜레이 체인으로 구성된 딜레이 체인부(60)를 통하여 일정 시간 지연된 후 블럭 선택신호(BS1_D, BS2_D, BS3_D)를 선택된 메모리 셀 어레이 블럭(10~30)에 인가시킨다. 이러한 딜레이 체인부(60)는 선택된 메모리 셀 어레이 블럭(10~30)이 인에이블 되기 전에 메모리 셀 어레이 블럭을 미리 VBB레벨로 만들어 놓기 위하여 사용된다.In addition, the block selection signal output from the block selection signal generator 50 is delayed for a predetermined time through the delay chain unit 60 composed of N inverter delay chains, and then the block selection signals BS1_D, BS2_D, and BS3_D are selected. To the blocks 10-30. The delay chain unit 60 is used to make the memory cell array block to the VBB level before the selected memory cell array blocks 10 to 30 are enabled.

이러한 구성을 갖는 본 발명의 디램 셀의 누설전류 억제 회로의 동작 과정을 살펴보면 다음과 같다.Looking at the operation of the leakage current suppression circuit of the DRAM cell of the present invention having such a configuration as follows.

먼저, 메모리 셀 어레이 블럭(10)에 리드 또는 라이트 동작 입력신호가 입력된다고 가정하면, 블럭 선택 신호 발생기(50)는 메모리 셀 어레이 블럭(10) 동작 신호를 입력받아 메모리 셀 어레이 블럭(10)을 선택하는 블럭선택신호(BS1)만 로우가 되도록 하고 나머지 블럭선택신호(BS2, BS3)는 모두 하이가 되도록 한다.First, assuming that a read or write operation input signal is input to the memory cell array block 10, the block select signal generator 50 receives the operation signal of the memory cell array block 10 to receive the memory cell array block 10. Only the selected block select signal BS1 is made low and the remaining block select signals BS2, BS3 are all made high.

블럭 선택 신호 발생기(50)로부터 출력된 블럭선택신호(BS1)는 제 1 VBB전환부(11)로 입력되어 PMOS트랜지스터(12)를 턴온시키게 된다. 이때, VBB발생기(40)로부터 인가되는 백바이어스 전압 VBB가 메모리 셀 어레이 블럭(10)에 인가되어 메모리 셀의 웰을 VBB레벨로 변환시키게 된다.The block select signal BS1 output from the block select signal generator 50 is input to the first VBB switching unit 11 to turn on the PMOS transistor 12. At this time, the back bias voltage VBB applied from the VBB generator 40 is applied to the memory cell array block 10 to convert the well of the memory cell to the VBB level.

이때, 제 2 VBB변환부(21) 및 제 3 VBB변환부(31)는 블럭선택신호 발생기(50)로부터 인가되는 "하이" 로직신호에 의해 NMOS트랜지스터(23,33)가 각각 턴온되어 Vss전압과 연결된다. 따라서, 선택되지 않고 대기중인 메모리 셀 어레이 블럭(20)및 메모리 셀 어레이 블럭(30)은 그라운드(Vss) 전압과 연결된다.At this time, the second VBB converter 21 and the third VBB converter 31 are turned on by the NMOS transistors 23 and 33 by the "high" logic signal applied from the block select signal generator 50 so that the Vss voltage is turned on. Connected with Accordingly, the unselected and waiting memory cell array block 20 and the memory cell array block 30 are connected to the ground (Vss) voltage.

다음에, 블럭선택 신호 발생기(50)로부터 출력된 블럭 선택신호(BS1)는 딜레이 체인부(60)의 N개의 인버터 딜레이 체인을 거쳐 일정시간 지연된 블럭 선택 신호(BS1_D)를 만들어 내고, 이 지연된 블럭선택신호(BS1_D)에 의해 메모리 셀 어레이 블럭(10)이 최종적으로 인에이블 된다.Next, the block selection signal BS1 output from the block selection signal generator 50 generates a block selection signal BS1_D delayed for a predetermined time through the N inverter delay chains of the delay chain unit 60, and the delayed block. The memory cell array block 10 is finally enabled by the selection signal BS1_D.

즉, 메모리 셀 어레이 블럭(10)은 딜레이 체인부(60)를 거쳐 발생한 지연된 블럭선택신호(BS1_D)에 의해 메모리 셀 어레이 블럭(10)이 엑티브 되기 전에 블럭 선택신호 BS1에 의해 미리 백바이어스 전압 VBB가 인가된 상태이다.That is, the memory cell array block 10 is previously back-biased by the block selection signal BS1 before the memory cell array block 10 is activated by the delayed block selection signal BS1_D generated through the delay chain unit 60. Is applied.

따라서, 라이트/리드 동작이 일어나는 메모리 셀 어레이 블럭(10)의 웰은 백바이어스 전압 VBB레벨이 되고, 라이트/리드 동작이 일어나지 않는 메모리 셀 어레이 블럭(20) 및 메모리 셀 어레이 블럭(30)의 웰은 그라운드가 된다. 결국, 대기중인 메모리 셀 어레이 블럭에서 전류가 누설되는 것이 방지된다.Therefore, the wells of the memory cell array block 10 in which the write / read operation occurs become the back bias voltage VBB level, and the wells of the memory cell array block 20 and the memory cell array block 30 in which the write / read operation does not occur. Becomes ground. As a result, leakage of current in the waiting memory cell array block is prevented.

이상에서 설명한 바와 같이, 본 발명의 디램 셀의 누설전류 억제 회로는, 캐패시터의 저장노드와 웰에 형성되는 pn접합의 전기장을 감소시켜 캐패시터의 대기중의 누설전류를 억제시킴으로써 디램 셀의 리프레시 특성을 개선시키도록 하는 효과를 제공한다.As described above, the leakage current suppression circuit of the DRAM cell of the present invention reduces the electric field of the pn junction formed in the storage node of the capacitor and the well to suppress the leakage current in the atmosphere of the capacitor, thereby improving the refresh characteristics of the DRAM cell. It provides an effect to improve.

Claims (2)

셀 캐패시터 및 셀 트랜지스터를 구비한 복수개의 메모리 셀 어레이 블럭;A plurality of memory cell array blocks having cell capacitors and cell transistors; 상기 복수개의 메모리 셀 어레이 블럭 중 리드 또는 라이트 동작이 이루어지는 메모리 셀 어레이 블럭을 선택하여 블럭선택 신호를 출력하는 블럭 선택신호 발생기;A block selection signal generator for selecting a memory cell array block to which a read or write operation is performed among the plurality of memory cell array blocks and outputting a block selection signal; 상기 복수개의 메모리 셀 어레이 블럭마다 각각 구비되고, 상기 블럭 선택 신호 발생기로부터 인가되는 블럭선택 신호에 따라 선택된 셀 어레이 블럭에만 백바이어스 전압을 인가시키는 복수개의 백바이어스 전압 전환수단; 및A plurality of back bias voltage switching means which are provided for each of the plurality of memory cell array blocks and apply a back bias voltage only to a selected cell array block according to a block selection signal applied from the block selection signal generator; And 상기 블럭 선택신호 발생기로부터 출력된 블럭선택 신호를 일정 시간 딜레이 시켜 상기 선택된 메모리 셀 어레이 블럭에 인가하는 딜레이 체인부를 구비함을 특징으로 하는 디램 셀의 누설전류 억제 회로.And a delay chain part configured to delay a block selection signal output from the block selection signal generator for a predetermined time and apply the delayed block selection signal to the selected memory cell array block. 제 1 항에 있어서,The method of claim 1, 상기 백바이어스 전압 전환수단은 공통 게이트 단자를 통하여 상기 블럭 선택 신호 발생기로부터 인가되는 블럭 선택 신호를 인가받고, 그 공통 드레인 단자는 각각의 메모리 셀 어레이 블럭과 연결되며, VBB전압단과 접지단 사이에 직렬 연결된 PMOS트랜지스터 및 NMOS트랜지스터로 구성됨을 특징으로 하는 디램 셀의 누설전류 억제 회로.The back bias voltage switching means receives a block selection signal applied from the block selection signal generator through a common gate terminal, and the common drain terminal is connected to each memory cell array block, and is connected in series between a VBB voltage terminal and a ground terminal. A leakage current suppression circuit of a DRAM cell, comprising: a connected PMOS transistor and an NMOS transistor.
KR1020000072898A 2000-12-04 2000-12-04 Leakage current suppression circuit of DRAM cell KR20020043780A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100612944B1 (en) * 2005-04-29 2006-08-14 주식회사 하이닉스반도체 Semiconductor device
KR100649973B1 (en) * 2005-09-14 2006-11-27 주식회사 하이닉스반도체 Device for generating internal voltage
KR100833587B1 (en) * 2001-12-22 2008-05-30 주식회사 하이닉스반도체 Semiconductor memory device for improving refresh characteristics

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100833587B1 (en) * 2001-12-22 2008-05-30 주식회사 하이닉스반도체 Semiconductor memory device for improving refresh characteristics
KR100612944B1 (en) * 2005-04-29 2006-08-14 주식회사 하이닉스반도체 Semiconductor device
KR100649973B1 (en) * 2005-09-14 2006-11-27 주식회사 하이닉스반도체 Device for generating internal voltage
US7292483B2 (en) 2005-09-14 2007-11-06 Hynix Semiconductor Inc. Back-bias voltage generator for decreasing a current consumption of a self-refresh operation

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