KR20020032696A - Method of manufacturing a capacitor in a semiconductor device - Google Patents
Method of manufacturing a capacitor in a semiconductor device Download PDFInfo
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- KR20020032696A KR20020032696A KR1020000063144A KR20000063144A KR20020032696A KR 20020032696 A KR20020032696 A KR 20020032696A KR 1020000063144 A KR1020000063144 A KR 1020000063144A KR 20000063144 A KR20000063144 A KR 20000063144A KR 20020032696 A KR20020032696 A KR 20020032696A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
Description
본 발명은 반도체 소자의 커패시터 제조 방법에 관한 것으로, 특히 하부 전극의 표면이 거칠어지는 것을 방지함으로써 계면 특성을 향상시켜 전기적 특성이 우수한 커패시터를 제조할 수 있는 반도체 소자의 커패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device capable of producing a capacitor having excellent electrical characteristics by improving an interfacial property by preventing the surface of the lower electrode from being rough.
반도체 소자의 고집적화에 따라서 1G DRAM 이상의 초고집적 소자에서는 기존의 나이트라이드/산화막(Nitride/Oxide) 구조로 충분한 축전 용량을 확보하기 어렵게 되었다. 이를 대체한 유전체로서 고유전율을 갖는 탄탈리움 산화막(Ta2O5)에 관하여 많이 연구되고 있으나, Ta2O5막은 상부 전극인 폴리실리콘과 후속 고온 열공정시 계면에서 실리콘 산화막을 생성시키는 등 열 안정성이 매우 나빠 소자의 특성을 저하시키는 원인이 되고 있다. 현재 상태에서는, 이러한 문제점을 해결하기 위한 방법으로 현재 CVD-TiN 이나 WNx 등을 Ta2O5와 폴리실리콘 사이에 형성시켜 상부 전극 겸 확산 방지막으로 많이 사용하거나 다른 재료의 개발이 시도되고 있다. 그러나, 후속 열공정에서의 상분리 문제, Ta2O5등의 고유전체막에서 분리되어 나온 산소가 산화물을 형성하여 유효 산화막 두께(Tox)가 증가하는 문제, 스텝 커버리지 문제, 누설 전류 특성 저하 등의 커패시터 특성이 저하될 있는 문제들을 획기적으로 개선하기 위한 연구가 지속적으로 전개되고 있다.Due to the high integration of semiconductor devices, it is difficult to secure sufficient storage capacity with an existing nitride / oxide structure in ultra-high density devices of 1G DRAM or more. Although many studies have been conducted on tantalum oxide films (Ta 2 O 5 ) having high dielectric constant as substitute dielectrics, Ta 2 O 5 films have thermal stability such as polysilicon as the upper electrode and silicon oxide film at the interface during the subsequent high temperature thermal process. This is very bad and causes the deterioration of the characteristics of the device. In the current state, as a method for solving such problems, CVD-TiN or WNx is currently formed between Ta 2 O 5 and polysilicon to be used as an upper electrode and a diffusion barrier, or development of other materials has been attempted. However, the problem of phase separation in the subsequent thermal process, the problem that the oxygen separated from the high-k dielectric film such as Ta 2 O 5 forms an oxide, which increases the effective oxide film thickness (Tox), the step coverage problem, the leakage current characteristics, etc. Research is continuously being conducted to drastically improve problems in which capacitor characteristics may be degraded.
반도체 소자의 축전기에 Ta2O5이외에 BST, PZT, Y1(SBT) 등의 높은 유전 상수를 갖는 재료를 사용하는 연구가 병행되고 있으나, 특히 이들 물질에 대해서도상하부 전극의 형성 조건은 매우 중요하며, 전극 재료와 유전층과의 계면 반응을 최대한 억제하여야 하고, 우수한 스텝 커버리지가 요구된다. 현재, 연구되고 있는 Pt, RuO2는 화학적 안정성이 매우 뛰어나기 때문에 유전층과의 계면특성이 우수한 반면, 전극 형성을 위한 식각이 매우 어려우며 스텝 커버리지가 우수한 CVD법으로 제조하는데 또한 어려움이 있다.In addition to Ta 2 O 5 in the capacitor of the semiconductor device, studies using a material having a high dielectric constant, such as BST, PZT, Y1 (SBT), but the formation of the upper and lower electrodes is very important, especially for these materials, The interfacial reaction between the electrode material and the dielectric layer should be suppressed as much as possible and excellent step coverage is required. Currently, Pt and RuO 2 being studied are excellent in chemical stability and have excellent interfacial properties with dielectric layers, but are difficult to etch for forming electrodes and have difficulty in manufacturing by CVD with excellent step coverage.
현재, MOCVD 방법을 이용하여 Ru을 증착하는데 있어서 계면 활성제(Surfactant)나 촉매 작용(Catalysis)을 도입한 화학적 처리(Chemical treatment) 등의 전처리를 가해주지 않는 MOCVD Ru막을 증착하고 있으나, 이러한 경우 기판에 상관없이 증착된 Ru의 표면이 매우 거칠어(Rough) 후속 공정에 큰 문제점이 야기 되고 있다. 이와 같이, 전극(Electrode)의 표면에 거친 상태에서 유전체막(Dielectric)을 증착하게 되면 Ru의 형태(Morphology)에 따라 전기장(Electric field)이 커패시터 내에서 다르게 생성되며, 특히 Ru 전극의 단면(Facet)이 형성된 곳에서 전기장이 집중되어 낮은 전압에서 커패시터의 불량이 발생하게 된다.Currently, in the deposition of Ru using MOCVD method, MOCVD Ru film which does not apply pretreatment such as chemical treatment with surfactant or catalysis is deposited. Regardless, the surface of the deposited Ru is very rough, which poses a big problem for subsequent processes. As such, when the dielectric film is deposited on the surface of the electrode, the electric field is generated differently in the capacitor according to the shape of Ru, in particular, the cross section of the Ru electrode. Where the field is concentrated, resulting in capacitor failure at low voltages.
또한, MOCVD로 증착한 Ru의 경우 불순물(Impurity) 제거를 통한 저항 감소와 물리적 공격(Attack)에 대한 저항성을 키우기 위하여 후속 열처리를 하여 주는데, 열처리를 하게 되면 그레인(Grain) 성장에 의해 형태가 더욱 나쁘게 된다. 그리고, 고집적화 되어 가는 소자에서 요구되는 커패시턴스(Capacitance)를 만족시키기 위하여 오목한(Concave) 콘택 안에 Ru을 증착하여 커패시터를 3차원(3D)으로 형성하는 경우 그레인이 매우 크게 성장하여 평판에 비해 형태가 더욱 열악해 진다.In addition, in the case of Ru deposited by MOCVD, subsequent heat treatment is performed in order to reduce resistance through impurity removal and to increase resistance to physical attack. When heat treatment is performed, the shape is further increased by grain growth. Becomes bad. In addition, when Ru is deposited in a concave contact to form a capacitor in three dimensions (3D) in order to satisfy the capacitance required by the highly integrated device, the grain grows very large and the shape becomes more than the flat plate. Worse
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 하부 전극을 Ru로 형성하되, 계면 활성제를 이용하여 하부 전극이 형성될 영역의 표면을 전처리하여 줌으로 증착된 Ru의 표면이 거칠어지는 것을 방지하여 커패시터 내부의 전기장을 균일하게 분포시킴으로써 불량을 방지하고 전기적 특성을 향상시킬 수 있는 반도체 소자의 커패시터 제조 방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention forms a lower electrode as Ru, but pretreat the surface of the region where the lower electrode is to be formed by using a surfactant to prevent the surface of the deposited Ru from being roughened by a capacitor. It is an object of the present invention to provide a method of manufacturing a capacitor of a semiconductor device capable of preventing defects and improving electrical characteristics by uniformly distributing an internal electric field.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 커패시터 제조 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도.1A to 1D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1 : 반도체 기판2 : 층간 절연막1 semiconductor substrate 2 interlayer insulating film
3a : 콘택 플러그용 폴리실리콘층3b : 오믹 콘택층3a: polysilicon layer for contact plug 3b: ohmic contact layer
3c : 확산 방지막3 : 콘택 플러그3c: diffusion barrier 3: contact plug
4 : 캡 절연막5 : Ru 하부 전극4 cap insulating film 5 Ru lower electrode
6 : 고유전체막7 : 상부 전극6: high dielectric film 7: upper electrode
본 발명에 따른 반도체 소자의 커패시터 제조 방법은 층간 절연막에 콘택홀이 형성되고, 콘택홀 내부에 확산 방지막을 포함한 콘택 플러그가 형성된 반도체 기판이 제공되는 단계, 전체 상에 캡 절연막을 형성한 후 하부 전극 마스크를 이용한 식각 공정으로 캡 절연막의 소정 영역을 식각하여 콘택 플러그가 노출되도록 홀을 형성하는 단계, 계면 활성제 또는 촉매를 이용하여 홀을 포함한 캡 절연막의 표면을 전처리하는 단계, 홀의 측벽 및 저면에 하부 전극을 형성하는 단계 및 전체 상에 유전체막 및 상부 전극을 형성하는 단계를 포함하여 이루어진다.In the method of manufacturing a capacitor of a semiconductor device according to the present invention, a contact hole is formed in an interlayer insulating film, and a semiconductor substrate is formed in which a contact plug including a diffusion barrier is formed inside the contact hole. Forming a hole to expose the contact plug by etching a predetermined region of the cap insulating film by an etching process using a mask; pretreating the surface of the cap insulating film including the hole by using a surfactant or a catalyst; Forming an electrode and forming a dielectric film and an upper electrode on the whole.
확산 방지막은 CVD법 또는 PVD법으로 형성한 TiN, TiAlN, TiSiN, TaN 또는 WNx막을 이용한다.As the diffusion barrier film, a TiN, TiAlN, TiSiN, TaN or WNx film formed by the CVD method or the PVD method is used.
계면 활성제 또는 촉매로는 순수 요오드 가스, 요오드 함유 가스, 요오드 함유 액체 화합물, BTA 또는 티오 요소 등을 이용하하며, 원소 주기율표 상의 7족 원소들인 F, Cl, Br, I 또는 At를 액체 상태 또는 가스 상태로 이용하거나, 이들의 화합물을 이용할 수도 있다. 전처리는 -20 내지 300℃의 온도 범위에서 1초 내지 10분 동안 실시한다.As the surfactant or catalyst, pure iodine gas, iodine-containing gas, iodine-containing liquid compound, BTA or thiourea, etc. are used, and Group 7, elements F, Cl, Br, I or At on the periodic table of the element are in liquid or gaseous state. It is also possible to use these compounds or these compounds. Pretreatment is carried out for 1 second to 10 minutes in the temperature range of -20 to 300 ℃.
하부 전극은 MOCVD법, CVD법 또는 PVD법으로 Ru막 또는 RuO2막을 증착하여 형성하되, 소오스로 Ru(Cp)2, Ru(EtCp)2, Ru(MeCp)2, Ru(tmhd)3, Ru(mhd)3, Ru(Od)3, RuCl3, Ru3(CO)12, Ru-acetylacetonate(Ru-AA), RuO3또는 RuO4을 이용하며, Ir막 또는 IrO2막을 증착하여 형성할 수도 있다.The lower electrode is formed by depositing a Ru film or a RuO 2 film by MOCVD, CVD, or PVD, but using a source of Ru (Cp) 2 , Ru (EtCp) 2 , Ru (MeCp) 2 , Ru (tmhd) 3 , Ru (mhd) 3 , Ru (Od) 3 , RuCl 3 , Ru 3 (CO) 12 , Ru-acetylacetonate (Ru-AA), RuO 3 or RuO 4 , and may be formed by depositing an Ir film or an IrO 2 film. have.
유전체막은 고유전율 값을 가지는 Ta2O5, PbTiO3, PbZr1-XTiXO3, PbLa1-XZrXTiO3, SrBi2Ta2O9, Bi4Ti3O12, BaTiO3, Ba1-XSrXTiO3또는 SrTiO3등을 이용하여 형성한다.The dielectric film has Ta 2 O 5 , PbTiO 3 , PbZr1-XTiXO 3 , PbLa1-XZrXTiO 3 , SrBi 2 Ta 2 O 9 , Bi 4 Ti 3 O 12 , BaTiO 3 , Ba1-XSrXTiO 3 , SrTiO 3, etc. To form.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 커패시터 제조 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 1a를 참조하면, 반도체 기판(1) 상에 층간 절연막(2)을 형성한 후 층간 절연막의 소정 영역을 식각하여 수직 배선을 위한 콘택홀을 형성해 접합부를 노출시킨다. 콘택홀 내부에는 수직 배선으로 콘택 플러그(3)를 형성한다. 이후 전체 상에 캡 절연막(4)을 형성한 후 하부 전극 마스크를 이용한 식각 공정으로 캡 절연막(4)의 소정 영역을 식각하여 홀을 형성해 콘택 플러그(3)가 노출되도록 한다.Referring to FIG. 1A, after forming the interlayer insulating film 2 on the semiconductor substrate 1, a predetermined region of the interlayer insulating film is etched to form a contact hole for vertical wiring to expose the junction. The contact plug 3 is formed in the contact hole by vertical wiring. Thereafter, the cap insulating film 4 is formed on the entire surface, and a predetermined area of the cap insulating film 4 is etched by an etching process using a lower electrode mask to form a hole so that the contact plug 3 is exposed.
일반적으로 콘택 플러그(3)는 콘택 플러그용 폴리실리콘층(3a), 오믹 콘택층(3b) 및 확산 방지막(3c)이 순차적으로 적층된 구조로 형성된다. 오믹 콘택층(3b)은 확산 방지막(3c)과의 오믹 콘택을 이루기 위하여 형성되며, 일반적으로 전체 상에 Ti을 증착한 후 열처리를 통해 형성된 TiSi2막을 이용하여 형성한다. 확산 방지막(3c)은 후속 공정에서 형성될 하부 전극이 열공정에 의해 콘택 플러그(3)로 확산되는 것을 방지하가 위하여 CVD법 또는 PVD법으로 형성하며, 질소(N)를 함유한 TiN, TiAlN, TiSiN, TaN 또는 WNx막 등이 사용된다.In general, the contact plug 3 has a structure in which a polysilicon layer 3a for contact plugs, an ohmic contact layer 3b, and a diffusion barrier 3c are sequentially stacked. The ohmic contact layer 3b is formed to form an ohmic contact with the diffusion barrier 3c. In general, the ohmic contact layer 3b is formed by using a TiSi 2 film formed by depositing Ti on the whole and then performing heat treatment. The diffusion barrier 3c is formed by a CVD method or a PVD method in order to prevent the lower electrode to be formed in the subsequent process from being diffused into the contact plug 3 by the thermal process, and includes TiN and TiAlN containing nitrogen (N). , TiSiN, TaN, or WNx film is used.
캡 절연막(4)은 커패시터의 하부 전극을 형성하기 위한 틀로 사용되며, 식각되는 형태에 따라서 하부 전극의 형태가 결정된다. 본 발명에서의 캡 절연막(4)은 오목한 구조(Concave)의 하부 전극을 형성하기 위한 식각 공정이 이루어진 상태이다. 캡 절연막(4)을 식각하는 과정에서, 하부에 형성되어 있는 층간 절연막(2)이 식각되지 않도록 식각 차단막(도시되지 않음)을 형성하며, 일반적으로 질화막을 이용한다.The cap insulating film 4 is used as a frame for forming the lower electrode of the capacitor, and the shape of the lower electrode is determined according to the form of etching. In the present invention, the cap insulating film 4 is in a state where an etching process for forming a lower electrode of a concave structure is performed. In the process of etching the cap insulating film 4, an etch blocking film (not shown) is formed so that the interlayer insulating film 2 formed below is not etched, and a nitride film is generally used.
도 1b를 참조하면, 하부 전극이 형성될 캡 절연막(4)의 측벽을 포함한 전체 표면을 계면 활성제 또는 촉매를 이용하여 전처리를 실시해 계면 활성제를 흡착시킨다.Referring to FIG. 1B, the entire surface including the sidewall of the cap insulating film 4 on which the lower electrode is to be formed is pretreated using a surfactant or a catalyst to adsorb the surfactant.
이때, 전처리는 순수 요오드(pure I2) 가스, 요오드(I) 함유 가스, 요오드(I) 함유 액체 화합물, BTA(Benzotriazole) 또는 티오 요소(Thiourea) 등을 화학 작용제(Chemical)로 사용하며, -20 내지 300℃의 온도 범위에서 1초 내지 10분 동안 실시한다. 또한, 화학 작용제로는 원소 주기율표 상의 7족 원소들인 F, Cl, Br, I 또는 At를 액체 상태 또는 가스 상태로 이용할 수 있으며, 이들의 화합물을 이용할 수도 있다. 상기의 공정으로 하부 전극이 형성될 영역에는 계면 활성제가 분포하게 된다.At this time, the pretreatment uses pure iodine (pure I 2 ) gas, iodine (I) containing gas, iodine (I) containing liquid compound, BTA (Benzotriazole) or thiourea (Thiourea) as a chemical agent,- It is carried out for 1 second to 10 minutes in the temperature range of 20 to 300 ℃. As the chemical agent, F, Cl, Br, I or At, which are Group 7 elements on the Periodic Table of the Elements, may be used in a liquid state or a gas state, and compounds thereof may be used. In the above process, the surfactant is distributed in the region where the lower electrode is to be formed.
도 1c를 참조하면, 전체 상에 MOCVD Ru막을 증착한 후 화학적 기계적 연마를 실시하여 캡 절연막(4) 상의 Ru막을 제거하여 Ru 하부 전극(5)을 형성한다.Referring to FIG. 1C, after depositing the MOCVD Ru film on the whole, chemical mechanical polishing is performed to remove the Ru film on the cap insulating film 4, thereby forming the Ru lower electrode 5.
하부 전극을 형성하기 위한 Ru막은 PVD(Physical vapor deposition)법이나 CVD(Chemical vapor deposition)법으로 형성할 수도 있다. 이때, CVD법으로 Ru막을 형성할 경우에는 Ru막의 소오스로 Ru(Cp)2, Ru(EtCp)2, Ru(MeCp)2, Ru(tmhd)3, Ru(mhd)3, Ru(Od)3, RuCl3, Ru3(CO)12, Ru-acetylacetonate(Ru-AA), RuO3또는 RuO4을 이용한다.The Ru film for forming the lower electrode may be formed by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition). In this case, when the Ru film is formed by CVD, Ru (Cp) 2 , Ru (EtCp) 2 , Ru (MeCp) 2 , Ru (tmhd) 3 , Ru (mhd) 3 , Ru (Od) 3 , RuCl 3 , Ru 3 (CO) 12 , Ru-acetylacetonate (Ru-AA), RuO 3 or RuO 4 is used.
하부 전극은 Ru막 대신에 RuO2막, Ir막 또는 IrO2막을 이용하여 형성할 수도 있으며, CVD법 또는 PVD법으로 형성한다. 이때, RuO2막을 이용하여 하부 전극을 형성할 경우에는 소오스로 Ru(Cp)2, Ru(EtCp)2, Ru(MeCp)2, Ru(tmhd)3, Ru(mhd)3, Ru(Od)3, RuCl3, Ru3(CO)12, Ru-acetylacetonate(Ru-AA), RuO3또는 RuO4을 이용한다.The lower electrode may be formed using a RuO 2 film, an Ir film, or an IrO 2 film instead of the Ru film, and may be formed by CVD or PVD. In this case, when the lower electrode is formed using a RuO 2 film, Ru (Cp) 2 , Ru (EtCp) 2 , Ru (MeCp) 2 , Ru (tmhd) 3 , Ru (mhd) 3 , and Ru (Od) 3 , RuCl 3 , Ru 3 (CO) 12 , Ru-acetylacetonate (Ru-AA), RuO 3 or RuO 4 are used.
도 1d를 참조하면, 전체 상에 고유전체막(6) 및 상부 전극(7)을 순차적으로 형성하여 커패시터를 제조한다.Referring to FIG. 1D, a capacitor is manufactured by sequentially forming the high dielectric film 6 and the upper electrode 7 over the whole.
고유전체막(6)은 Ta2O5, PbTiO3, PbZr1-XTiXO3, PbLa1-XZrXTiO3, SrBi2Ta2O9, Bi4Ti3O12, BaTiO3, Ba1-XSrXTiO3또는 SrTiO3등을 이용하여 형성하며, 상부 전극(7)으로는 Ru막을 이용하여 형성한다. 상부 전극(7)은 Ru막 뿐만 아니라, Pt 등과 같은 노블 메탈(Noble metal)을 이용하여 형성할 수도 있다. 고유전체막(6)을 형성한 후에는 고유전체막(6)을 막질을 향상시키기 위한 열처리를 실시하며, 커패시터가 제조된 후에도 커패시터의 전기적 특성을 향상시키기 위한 열처리를 실시할 수도 있다.The high-k dielectric film 6 includes Ta 2 O 5 , PbTiO 3 , PbZr1-XTiXO 3 , PbLa1-XZrXTiO 3 , SrBi 2 Ta 2 O 9 , Bi 4 Ti 3 O 12 , BaTiO 3 , Ba1-XSrXTiO 3, or SrTiO 3, etc. It is formed using the, and the upper electrode 7 is formed using a Ru film. The upper electrode 7 may be formed using a noble metal such as Pt as well as a Ru film. After the high dielectric film 6 is formed, the high dielectric film 6 is heat treated to improve the film quality, and even after the capacitor is manufactured, heat treatment may be performed to improve the electrical characteristics of the capacitor.
상기의 공정과 같이, Ru 하부 전극(5)을 증착하기 전에 Ru 하부 전극이 형성될 캡 절연막(4)의 측벽을 포함한 전체 표면에 계면 활성제로 전처리 하여 흡착시킨 후 MOCVD Ru을 증착하게 되면, 표면에 형성되어 있던 계면 활성제는 Ru막의 3차원 성장(3-D growth)을 억제하고 2차원 성장(2-D growth)을 촉진시키면서 Ru막의 표면으로 떠올라 표면의 거칠기 정도를 향상시키게 된다.As in the above process, before depositing the Ru lower electrode 5, the MOCVD Ru is deposited by pretreatment with a surfactant on the entire surface including the sidewall of the cap insulating film 4 on which the Ru lower electrode 5 is to be formed, and then adsorbed. The surfactant formed on the surface of the Ru film is suppressed to 3-D growth and promotes 2-D growth, thereby rising to the surface of the Ru film to improve the roughness of the surface.
상술한 바와 같이, 본 발명은 하부 전극을 형성하기 전에 하부 전극이 형성될 영역에 계면 활성제를 이용하여 전처리를 실시하여 줌으로써 하부 전극 형성 시 표면이 거칠어지는 것을 방지하여 커패시터의 전기적 특성을 향상시키는 효과가 있다.As described above, according to the present invention, before the lower electrode is formed, the surface of the lower electrode is formed by performing a pretreatment using a surfactant in the region where the lower electrode is to be formed. There is.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100493707B1 (en) * | 2002-02-28 | 2005-06-03 | 재단법인서울대학교산학협력재단 | Ruthenium Thin Film Formation Method |
| KR100693787B1 (en) * | 2005-06-09 | 2007-03-12 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor in semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100493707B1 (en) * | 2002-02-28 | 2005-06-03 | 재단법인서울대학교산학협력재단 | Ruthenium Thin Film Formation Method |
| KR100693787B1 (en) * | 2005-06-09 | 2007-03-12 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor in semiconductor device |
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