KR20020013195A - Method for forming gate pattern of semiconductor device - Google Patents
Method for forming gate pattern of semiconductor device Download PDFInfo
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- KR20020013195A KR20020013195A KR1020000046677A KR20000046677A KR20020013195A KR 20020013195 A KR20020013195 A KR 20020013195A KR 1020000046677 A KR1020000046677 A KR 1020000046677A KR 20000046677 A KR20000046677 A KR 20000046677A KR 20020013195 A KR20020013195 A KR 20020013195A
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- layer
- gate
- gate pattern
- film
- polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229920005591 polysilicon Polymers 0.000 claims abstract description 40
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 8
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000011800 void material Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 좀더 구체적으로 반도체 장치의 게이트 패턴 형성 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate pattern of a semiconductor device.
반도체 소자가 고집적화되면서 게이트 패턴의 폭도 감소하고 있다. 이는 게이트 전극의 저항을 증가시켜 트랜지스터의 동작 속도를 저하시키는 원인이 된다. 따라서, 저항이 낮은 도전 물질을 사용하여 게이트 전극을 형성함으로써, 트랜지스터의 동작 속도를 증가시키려는 시도들이 진행되고 있다.As semiconductor devices are highly integrated, the width of gate patterns is also decreasing. This causes the resistance of the gate electrode to increase, thereby lowering the operating speed of the transistor. Thus, attempts have been made to increase the operating speed of transistors by forming gate electrodes using conductive materials with low resistance.
최근에는 게이트 전극의 저항을 감소시키기 위한 저저항 물질로 금속과 실리콘의 화합물인 실리사이드(silicide)를 사용하는 추세이다. 실리사이드는 예를 들어, 텅스텐(W), 티타늄(Ti) 및 탄탈륨(Ta) 등으로 형성할 수 있으며, 특히 게이트 전극용으로는 텅스텐 실리사이드(WSix)가 주로 사용된다. 실리사이드는 종래의 도핑된 폴리실리콘에 비해 비저항이 낮고, 고온에서 안정한 물질이다. 그러나, 실리사이드막은 실리콘 산화막과의 접착 특성이 나쁘기 때문에, 폴리실리콘막과 실리사이드막을 적층시킨 폴리사이드(polycide) 구조로 게이트 전극을 형성한다.Recently, silicides, which are compounds of metals and silicon, have been used as low-resistance materials for reducing the resistance of gate electrodes. The silicide may be formed of, for example, tungsten (W), titanium (Ti), tantalum (Ta), or the like, and tungsten silicide (WSi x ) is mainly used for the gate electrode. Silicide is a low resistivity and stable material at high temperatures compared to conventional doped polysilicon. However, since the silicide film has poor adhesion characteristics with the silicon oxide film, the gate electrode is formed with a polycide structure in which a polysilicon film and a silicide film are laminated.
이하, 도 1 을 참조하여 종래 기술의 문제점을 설명한다.Hereinafter, the problems of the prior art will be described with reference to FIG. 1.
도 1a 및 도 1d는 종래 기술에 의한 게이트 형성 방법을 나타내는 단면도들이다.1A and 1D are cross-sectional views illustrating a gate forming method according to the prior art.
도 1a를 참조하면, 반도체 기판(10) 상에 게이트 산화막(12), 도핑된 폴리실리콘막(13), 텅스텐 실리사이드막(14) 및 캡핑절연막(15)을 차례로 형성한다.Referring to FIG. 1A, a gate oxide layer 12, a doped polysilicon layer 13, a tungsten silicide layer 14, and a capping insulating layer 15 are sequentially formed on the semiconductor substrate 10.
도 1b 및 도 1c를 참조하면, 캡핑절연막(15), 텅스텐 실리사이드막(14), 폴리실리콘막(13) 및 게이트 산화막(12)을 패터닝하여 게이트 패턴(17)을 형성한다. 따라서, 게이트 패턴(17)은 게이트 산화막 패턴(12a), 폴리실리콘막 패턴(13a), 실리사이드막 패턴(14a) 및 캡핑절연막 패턴(15a)이 차례로 적층된 구조를 갖는다.1B and 1C, the capping insulating layer 15, the tungsten silicide layer 14, the polysilicon layer 13, and the gate oxide layer 12 are patterned to form a gate pattern 17. Accordingly, the gate pattern 17 has a structure in which the gate oxide film pattern 12a, the polysilicon film pattern 13a, the silicide film pattern 14a, and the capping insulating film pattern 15a are sequentially stacked.
패터닝 공정 후에도 게이트 패턴(17) 양옆의 활성 영역 상에 남아있는 게이트 산화막(12b)을 습식 세정 공정으로 제거한다.After the patterning process, the gate oxide film 12b remaining on the active regions on both sides of the gate pattern 17 is removed by a wet cleaning process.
도 1d를 참조하면, 게이트 패턴(17)을 포함하는 반도체 기판(10) 전면을 열산화시켜 게이트 패턴(17) 및 반도체 기판(10)을 덮는 열산화막(19)을 형성한다. 이러한 산화 공정의 목적은 다음과 같다. 첫째, 활성 영역의 표면에 존재하는 이온 주입 공정에 의한 손상을 치유하고, 새로운 산화막을 형성하여 기판 표면의 누설 전류를 감소시키기 위한 것이다. 둘째, 게이트 전극의 하단 모서리에 버즈 빅(bird's beak)이 형성되도록 하여, 게이트 전극의 모서리에 전계(electric field)가 집중되어 발생하는 캐리어(carrier)들의 열화를 감소시켜 트랜지스터의 특성을 안정화시키기 위한 것이다. 세째, 실리사이드 표면에 양질의 절연막을 형성함으로써 게이트 전극의 절연 특성을 강화시키기 위한 것이다.Referring to FIG. 1D, the entire surface of the semiconductor substrate 10 including the gate pattern 17 is thermally oxidized to form a thermal oxide film 19 covering the gate pattern 17 and the semiconductor substrate 10. The purpose of this oxidation process is as follows. First, it is to heal the damage caused by the ion implantation process present on the surface of the active region, and to form a new oxide film to reduce the leakage current on the surface of the substrate. Second, a bird's beak is formed at the bottom edge of the gate electrode to reduce deterioration of carriers caused by the concentration of an electric field at the edge of the gate electrode to stabilize the characteristics of the transistor. will be. Third, it is to enhance the insulating characteristics of the gate electrode by forming a high quality insulating film on the silicide surface.
그러나, 이와 같은 종래 기술에 의하면, 열산화 공정에 의해 게이트 패턴(17)을 덮는 열산화막(19)을 형성할 때, 폴리실리콘막(13)의 내부에 보이드가 생성되는 문제가 발생한다. 이는 텅스텐 실리사이드막(14)이 산화되면서 실리사이드막(14) 내부의 실리콘 원자들이 소모된 후 하부 폴리실리콘막(13)의 실리콘 원자들이 실리사이드막(14)으로 확산하기 때문이다.However, according to this conventional technique, when the thermal oxide film 19 covering the gate pattern 17 is formed by the thermal oxidation process, a problem occurs in that voids are generated inside the polysilicon film 13. This is because the silicon atoms of the lower polysilicon film 13 diffuse into the silicide film 14 after the tungsten silicide film 14 is oxidized and the silicon atoms inside the silicide film 14 are consumed.
이를 해결하기 위해, 최근에는 실리사이드막 내에 실리콘 원자의 함유량을 증가시킨 실리콘 리치 실리사이드막(silicon rich silicide)을 형성하는 방법이 제안되었다. 그러나, 실리콘 리치 실리사이드막은 종래의 실리사이드막에 비해 저항이 크다는 문제가 있다.In order to solve this problem, recently, a method of forming a silicon rich silicide in which the content of silicon atoms is increased in the silicide film has been proposed. However, a silicon rich silicide film has a problem that resistance is large compared with the conventional silicide film.
본 발명은 상술한 제반 문제를 해결하기 위해 제안된 것으로, 폴리사이드 구조의 게이트 전극을 형성할 때 폴리실리콘막 내부에 보이드가 생성되는 것을 방지할 수 있는 게이트 패턴의 형성 방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problems, and an object thereof is to provide a method of forming a gate pattern capable of preventing voids from being generated inside a polysilicon layer when forming a gate electrode having a polyside structure. There is this.
도 1a 내지 도 1d는 종래 기술에 의한 게이트 패턴 형성 방법을 나타내는 단면도들이다.1A to 1D are cross-sectional views illustrating a gate pattern forming method according to the prior art.
도 2a 내지 도 2f는 본 발명의 실시예에 의한 게이트 패턴 형성 방법을 나타내는 단면도들이다.2A to 2F are cross-sectional views illustrating a gate pattern forming method according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10, 100 : 반도체 기판 12, 102 : 게이트 산화막10, 100: semiconductor substrate 12, 102: gate oxide film
13, 103 : 폴리실리콘막 14, 104 : 실리사이드막13, 103 polysilicon film 14, 104 silicide film
15, 105 : 캡핑절연막 17, 107 : 게이트 패턴15, 105: capping insulating film 17, 107: gate pattern
109 : 산화용 폴리실리콘막109: polysilicon film for oxidation
109a : 스페이서 19, 110 : 열산화막109a: spacer 19, 110: thermal oxide film
(구성)(Configuration)
상술한 목적을 달성하기 위하여 본 발명에 따른 게이트 패턴 형성 방법은, 반도체 기판 상에 게이트 산화막, 도핑된 폴리실리콘막 및 텅스텐 실리사이드막을 차례로 형성한 후 패터닝하여 게이트 패턴을 형성한다. 게이트 패턴의 양측벽에 폴리실리콘 스페이서를 형성한다. 스페이서가 형성된 게이트 패턴을 포함하는 반도체 기판 전면을 열산화시켜 게이트 패턴 및 반도체 기판을 덮는 열산화막을 형성한다.In order to achieve the above object, in the gate pattern forming method according to the present invention, a gate oxide film, a doped polysilicon film, and a tungsten silicide film are sequentially formed on a semiconductor substrate and then patterned to form a gate pattern. Polysilicon spacers are formed on both sidewalls of the gate pattern. A thermal oxide film covering the gate pattern and the semiconductor substrate is formed by thermally oxidizing the entire surface of the semiconductor substrate including the gate pattern having the spacer formed thereon.
상기 게이트 패턴을 형성한 후 게이트 산화막의 일부분을 추가로 습식 식각하여 상기 게이트 패턴의 하단 양측에 언더컷을 형성하는 것이 바람직하다.After forming the gate pattern, a portion of the gate oxide layer may be further wet-etched to form undercuts on both sides of the lower end of the gate pattern.
(실시예)(Example)
이하, 도 2를 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.
도 2a 내지 도 2f는 본 발명의 실시예에 의한 반도체 장치의 게이트 패턴 형성 방법을 설명하기 위한 단면도들이다.2A to 2F are cross-sectional views illustrating a gate pattern forming method of a semiconductor device in accordance with an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(100) 전면에 게이트 산화막(102)을 형성한다. 게이트 산화막(102) 상에 폴리실리콘막을 형성한 후 도전형의 불순물 이온, 예를 들어 인(P) 이온을 주입하여 도핑된 폴리실리콘막(103)을 형성한다. 도핑된 폴리실리콘막(103) 상에 실리사이드막(104), 예를 들어 텅스텐 실리사이드막을 형성한다. 텅스텐 실리사이드막은 실리콘 소오스 기체인 SiH4와 텅스텐 소오스 기체인 WF6을 400 내지 500 ℃ 온도에서 반응시켜 형성한다. 실리사이드막(104) 상에 캡핑절연막(105)을 형성한다. 캡핑절연막(105)은 예를 들어, CVD 공정에 의한 실리콘 산화막 또는 실리콘 질화막으로 형성한다. 캡핑절연막(105)은 게이트 패턴을 절연시키는 역할을 할 뿐만 아니라 후속 패터닝 공정에서 게이트 패턴을 형성하기 위한 식각 마스크로 사용된다.Referring to FIG. 2A, a gate oxide layer 102 is formed over the semiconductor substrate 100. After the polysilicon layer is formed on the gate oxide layer 102, a doped polysilicon layer 103 is formed by implanting conductive type impurity ions such as phosphorus (P) ions. A silicide film 104, for example, a tungsten silicide film, is formed on the doped polysilicon film 103. The tungsten silicide film is formed by reacting SiH 4 , a silicon source gas, and WF 6 , a tungsten source gas, at a temperature of 400 to 500 ° C. The capping insulating layer 105 is formed on the silicide layer 104. The capping insulating film 105 is formed of, for example, a silicon oxide film or a silicon nitride film by a CVD process. The capping insulating layer 105 not only insulates the gate pattern but also serves as an etch mask for forming the gate pattern in a subsequent patterning process.
도 2b를 참조하면, 캡핑절연막(105) 상에 포토레지스트막(도면에 미도시)을 형성한다. 포토레지트스막을 패터닝하여 게이트 패턴을 정의하는 포토레지스트 패턴을 형성한다. 포토레지스트 패턴을 식각마스크로 사용하여 캡핑절연막(105)을 건식 식각하여 캡핑절연막 패턴(105a)을 형성한다. 캡핑절연막 패턴(105a)을 식각마스크로 사용하여 실리사이드막(104), 폴리실리콘막(103) 및 게이트 산화막(102)을 차례로 건식 식각한다. 그러면, 게이트 산화막 패턴(102a), 폴리실리콘막 패턴(103a), 실리사이드막 패턴(104a) 및 캡핑절연막 패턴(105a)이 차례로 적층된 게이트 패턴(107)이 형성된다.Referring to FIG. 2B, a photoresist film (not shown) is formed on the capping insulating film 105. The photoresist film is patterned to form a photoresist pattern defining a gate pattern. The capping insulating layer 105 is dry-etched using the photoresist pattern as an etching mask to form the capping insulating layer pattern 105a. The silicide layer 104, the polysilicon layer 103, and the gate oxide layer 102 are sequentially dry-etched using the capping insulating layer pattern 105a as an etching mask. As a result, a gate pattern 107 in which the gate oxide layer pattern 102a, the polysilicon layer pattern 103a, the silicide layer pattern 104a, and the capping insulation layer pattern 105a are sequentially stacked is formed.
경우에 따라서는, 포토레지스트 패턴을 식각마스크로 사용하여 캡핑절연막(105), 실리사이드막(104), 폴리실리콘막(103) 및 게이트 산화막(102)을 차례로 식각하여 게이트 패턴(107)을 형성할 수도 있다.In some cases, the gate pattern 107 may be formed by sequentially etching the capping insulating layer 105, the silicide layer 104, the polysilicon layer 103, and the gate oxide layer 102 using the photoresist pattern as an etching mask. It may be.
이때, 게이트 산화막(102)을 제거하면서 반도체 기판(100)의 표면에 손상이 가해지는 것을 방지하기 위하여 게이트 산화막(102)은 일부부만 식각한다. 따라서, 게이트 패턴(107) 양옆의 활성 영역 상에는 게이트 산화막의 일부(102b)가 남아있게 된다.At this time, in order to prevent damage to the surface of the semiconductor substrate 100 while removing the gate oxide layer 102, only a portion of the gate oxide layer 102 is etched. Accordingly, a part of the gate oxide film 102b remains on the active regions on both sides of the gate pattern 107.
도 2c를 참조하면, 게이트 패턴(107) 양옆의 활성 영역 상에 잔류하는 게이트 산화막(102b)을 습식 식각으로 제거한다. 습식 식각은 예를 들어, 완충 산화막 식각용액(burffered oxide etchant; BOE)을 사용한다.Referring to FIG. 2C, the gate oxide layer 102b remaining on the active regions on both sides of the gate pattern 107 is removed by wet etching. Wet etching uses, for example, a buffered oxide etchant (BOE).
여기서, 게이트 패턴(107)의 하부를 구성하는 게이트 산화막 패턴(102a)의 일부분을 추가로 습식 식각하여, 게이트 패턴(107)의 하단 양측에 언더컷(108)을 형성하는 것이 바람직하다. 그러면, 산화막을 형성하는 후속 공정에서 게이트 산화막(102a)과 폴리실리콘막(103a)의 경계 부위에 버즈 빅 현상이 발생하므로, 폴리실리콘막(103a)의 하단 모서리에 전계가 집중되는 것을 감소시킬 수 있다.Here, it is preferable to further wet-etch a part of the gate oxide layer pattern 102a constituting the lower portion of the gate pattern 107 to form the undercuts 108 on both sides of the lower end of the gate pattern 107. Then, a buzz big phenomenon occurs at the boundary between the gate oxide film 102a and the polysilicon film 103a in a subsequent step of forming the oxide film, thereby reducing concentration of an electric field on the bottom edge of the polysilicon film 103a. have.
도 2d 및 도 2e를 참조하면, 언더컷(108)이 형성된 결과물 전면에 스페이서를 형성하기 위한 산화용 폴리실리콘막(109)을 형성한다. 산화용 폴리실리콘막(109)을 이방성 식각하여 게이트 패턴(107)의 양측벽에 폴리실리콘 스페이서(109a)를 형성한다.2D and 2E, the polysilicon film 109 for forming an oxide is formed on the entire surface of the resultant undercut 108. The polysilicon layer 109 for oxidation is anisotropically etched to form polysilicon spacers 109a on both sidewalls of the gate pattern 107.
도 2f를 참조하면, 스페이서(109a)가 형성된 게이트 패턴(107)을 포함하는 반도체 기판(100) 전면을 열처리하여 게이트 패턴(107) 및 반도체 기판(100)을 덮는 열산화막(110)을 형성한다. 열산화막(110)은 예를 들어, 산소 기체 분위기 하에서 800 내지 1000 ℃ 의 온도로 열처리하여 형성한다.Referring to FIG. 2F, the entire surface of the semiconductor substrate 100 including the gate pattern 107 having the spacer 109a is heat-treated to form a thermal oxide film 110 covering the gate pattern 107 and the semiconductor substrate 100. . The thermal oxide film 110 is formed by, for example, heat treatment at a temperature of 800 to 1000 ° C. in an oxygen gas atmosphere.
이와 같은 방법에 의하면, 게이트 패턴(107)의 양측벽에 형성된 폴리실리콘 스페이서(109a)가 산화되어 열산화막(110)이 형성되므로, 실리사이드막(104) 내부의 실리콘 원자는 소모되지 않는다. 따라서, 폴리실리콘막(103) 내부의 실리콘 원자들이 실리사이드막(104)으로 확산하는 것을 방지할 수 있게 된다.According to this method, since the polysilicon spacers 109a formed on both sidewalls of the gate pattern 107 are oxidized to form the thermal oxide film 110, silicon atoms inside the silicide film 104 are not consumed. Therefore, it is possible to prevent the silicon atoms inside the polysilicon film 103 from diffusing into the silicide film 104.
본 발명은 폴리사이드로 형성된 게이트 패턴의 측벽에 폴리실리콘막 스페이서를 형성한 후 열산화시킴으로써, 폴리실리콘막의 실리콘 원자가 실리사이드막으로 확산하는 것을 방지할 수 있다. 따라서, 폴리실리콘막 내부에 보이드가 생성되는 것을 방지할 수 있고, 우수한 프로파일을 갖는 게이트 패턴을 형성할 수 있다.According to the present invention, a polysilicon film spacer is formed on sidewalls of a gate pattern formed of polyside and thermally oxidized to prevent diffusion of silicon atoms of the polysilicon film into the silicide film. Therefore, voids can be prevented from being generated inside the polysilicon film, and a gate pattern having an excellent profile can be formed.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100495662B1 (en) * | 2002-11-11 | 2005-06-16 | 삼성전자주식회사 | Method for fabricating a semiconductor device |
KR100580050B1 (en) * | 2004-12-29 | 2006-05-12 | 동부일렉트로닉스 주식회사 | Method for fabricating the poly silicon gate of semiconductor device |
KR20070003021A (en) * | 2005-06-30 | 2007-01-05 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
KR100780651B1 (en) * | 2006-06-30 | 2007-11-29 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
KR100929631B1 (en) * | 2007-02-15 | 2009-12-03 | 주식회사 하이닉스반도체 | Manufacturing method of MOSFET device |
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2000
- 2000-08-11 KR KR1020000046677A patent/KR20020013195A/en not_active Application Discontinuation
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100495662B1 (en) * | 2002-11-11 | 2005-06-16 | 삼성전자주식회사 | Method for fabricating a semiconductor device |
US7001817B2 (en) | 2002-11-11 | 2006-02-21 | Samsung Electronics Co., Ltd. | Method for fabricating a semiconductor device |
KR100580050B1 (en) * | 2004-12-29 | 2006-05-12 | 동부일렉트로닉스 주식회사 | Method for fabricating the poly silicon gate of semiconductor device |
KR20070003021A (en) * | 2005-06-30 | 2007-01-05 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
KR100780651B1 (en) * | 2006-06-30 | 2007-11-29 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
KR100929631B1 (en) * | 2007-02-15 | 2009-12-03 | 주식회사 하이닉스반도체 | Manufacturing method of MOSFET device |
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