KR20010063771A - A method for forming a field oxide of a semiconductor device - Google Patents
A method for forming a field oxide of a semiconductor device Download PDFInfo
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- KR20010063771A KR20010063771A KR1019990061859A KR19990061859A KR20010063771A KR 20010063771 A KR20010063771 A KR 20010063771A KR 1019990061859 A KR1019990061859 A KR 1019990061859A KR 19990061859 A KR19990061859 A KR 19990061859A KR 20010063771 A KR20010063771 A KR 20010063771A
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- forming
- trench
- polysilicon
- tungsten silicide
- stacked structure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000002955 isolation Methods 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000007517 polishing process Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000009271 trench method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 특히 반도체소자의 고집적화에 적용하기 위하여 소자분리막의 크기가 비교적 큰 주변회로부의 트렌치형 소자분리막 내부에 폴리실리콘으로 형성하고 후속공정으로 이에 콘택되는금속배선을 형성할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation film of a semiconductor device. In particular, the present invention relates to a method of forming a device isolation film of a semiconductor device. The present invention relates to a technology for forming a metal wiring.
고집적화라는 관점에서 소자의집적도를 높이기 위하여 각각 소자의 디맨젼 ( dimension ) 을 축소하는 것과 소자간에 존재하는 분리영역 ( isolation region ) 의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 크기를 결정하는 기술이라고 할 수 있다.In order to increase the density of devices from the viewpoint of high integration, it is necessary to reduce the dimension of each device and to reduce the width and area of the isolation region existing between the devices. In this regard, device isolation technology is a technology for determining the size of a memory cell.
소자분리막을 제조하는 종래의 기술로는 절연물 분리방식의 로코스 ( LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함 ) 방법, 반도체기판 상부에 산화막, 다결정실리콘층 및 질화막 순으로 적층한 구조의 피.비.엘. ( poly buffered LOCOS, 이하에서 PBL 이라 함 ) 방법 및 반도체기판을 식각하여 홈을 형성하고 이를 매립하는 트렌치 방법 등이 있으나, 반도체소자의 단차 특성을 향상시킬 수 있는 트렌치 방법을 주로 사용하고 있다.Conventional techniques for manufacturing device isolation films include LOCal Oxidation of Silicon (LOCOS) method of insulation isolation method, P. structure of stacked structure of oxide film, polysilicon layer and nitride film on top of semiconductor substrate. .L. (Poly buffered LOCOS, hereinafter referred to as PBL) method and a trench method for etching a semiconductor substrate to form a groove and filling it, but a trench method for improving the step characteristic of a semiconductor device is mainly used.
도 1 은 종래기술에 따른 트렌치형 소자분리막 형성방법을 도시한 단면도이다.1 is a cross-sectional view illustrating a method of forming a trench type isolation layer according to the prior art.
먼저, 반도체기판(11) 상부에 패드절연막(도시안됨)을 형성하고 이를 소자분리마스크(도시안됨)를 이용한 사진식각공정으로 패터닝한다.First, a pad insulating layer (not shown) is formed on the semiconductor substrate 11 and patterned by a photolithography process using a device isolation mask (not shown).
그리고, 상기 패터닝된 패드절연막을 마스크로하여 상기 반도체기판(11)을 식각하여 트렌치를 형성하고 이를 매립하는 산화막을 전체표면상부에 형성한다.The semiconductor substrate 11 is etched using the patterned pad insulating layer as a mask to form a trench, and an oxide film filling the trench is formed on the entire surface.
그 다음, 상기 산화막을 평탄화식각하여 상기 트렌치를 매립하는 산화막으로 소자분리막(13)을 형성한다. (도 1)Next, the device isolation layer 13 is formed of an oxide layer filling the trench by planar etching of the oxide layer. (Figure 1)
상기한 바와같이 종래기술에 따른 반도체소자의 소자분리막 형성방법은, 소자분리영역에 구비되는 소자분리막은 활성영역을 전기적으로 분리시켜 역할만을 하여 소자의 회로동작을 구현하는 주변회로부의 고집적화를 어렵게 하는 문제점이 있다.As described above, the method of forming a device isolation film of a semiconductor device according to the prior art makes it difficult to achieve high integration of a peripheral circuit part implementing a circuit operation of a device by only separating the active area electrically from the device isolation layer provided in the device isolation area. There is a problem.
본 발명은, 셀부에 비하여 비교적 큰 영역에 형성되는 주변회로부의 소자분리막 내부에 폴리실리콘을 형성하고, 회로를 구현하기 위한 후속 금속배선 콘택공정시 폴리실리콘과 콘택시켜 Vcc 나 Vss 로 사용할 수 있도록 함으로써 반도체소자의 고집적화를 가능하게 하는 반도체소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.According to the present invention, polysilicon is formed inside a device isolation film of a peripheral circuit portion formed in a relatively large area compared to a cell portion, and the polysilicon can be used as Vcc or Vss by contacting polysilicon in a subsequent metallization contact process for implementing a circuit. It is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device that enables high integration of the semiconductor device.
도 1 은 종래기술에 따른 반도체소자의 소자분리막 형성방법을 나타낸 단면도.1 is a cross-sectional view showing a device isolation film forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 나타낸 단면도.2A to 2F are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
〈도면의 주요주분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11,21 : 반도체기판 13,41 : 소자분리막11,21: semiconductor substrate 13,41: device isolation film
23 : 감광막패턴 25 : 트렌치23 photoresist pattern 25 trench
27 : 제1산화막 29 : 폴리실리콘27: first oxide film 29: polysilicon
31 : 텅스텐 실리사이드 33 : 제2산화막31: tungsten silicide 33: second oxide film
상기 목적 달성을 위해 본 발명에 따른 반도체소자의 소자분리막 형성방법은,In order to achieve the above object, a device isolation film forming method of a semiconductor device according to the present invention is
반도체기판의 소자분리영역에 트렌치를 형성하는 공정과,Forming a trench in the isolation region of the semiconductor substrate;
상기 트렌치를 포함한 전체표면상부에 제1산화막을 일정두께 형성하는 공정과,Forming a first oxide film at a predetermined thickness on the entire surface including the trench;
상기 제1산화막 상부에 폴리실리콘과 텅스텐 실리사이드를 일정두께 형성하는 공정과,Forming a predetermined thickness of polysilicon and tungsten silicide on the first oxide film;
상기 텅스텐 실리사이드의 활성영역 부분을 에치백하여 소자분리영역인 트렌치 내부에만 폴리실리콘과 텅스텐 실리사이드의 적층구조를 형성하는 공정과,Etching back the active region of the tungsten silicide to form a stacked structure of polysilicon and tungsten silicide only in the trench as an isolation region;
전체표면상부에 제2산화막을 형성하여 평탄화시키는 공정과,Forming and planarizing a second oxide film on the entire surface;
상기 반도체기판을 노출시킬때까지 상기 제1,2산화막을 평탄화식각하여 상기 트렌치를 매립하며 내부에 폴리실리콘과 텅스텐 실리사이드의 적층구조가 구비되는 소자분리막을 형성하는 공정을 포함하는 것을 특징으로한다.And forming a device isolation film having a stacked structure of polysilicon and tungsten silicide and filling the trench by planarizing etching the first and second oxide films until the semiconductor substrate is exposed.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도로서, 반도체소자의 주변회로부를 도시한다.2A to 2F are cross-sectional views illustrating a method of forming an isolation layer of a semiconductor device in accordance with an embodiment of the present invention, and illustrate a peripheral circuit portion of the semiconductor device.
먼저, 반도체기판(21) 상부에 감광막패턴(23)을 형성한다. 이때, 상기 감광막패턴(23)은 소자분리마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다.First, the photosensitive film pattern 23 is formed on the semiconductor substrate 21. In this case, the photoresist pattern 23 is formed by an exposure and development process using an element isolation mask (not shown).
그리고, 상기 감광막패턴(23)을 마스크로하여 상기 반도체기판(21)을 식각하여 트렌치(25)를 형성한다.The semiconductor substrate 21 is etched using the photoresist pattern 23 as a mask to form the trench 25.
이때, 상기 트렌치(25)은 소자분리막을 형성하기 위한 일반적인 깊이보다 깊게 형성한다. (도 2a)In this case, the trench 25 is formed deeper than the general depth for forming the device isolation layer. (FIG. 2A)
그 다음, 상기 트렌치(25)를 포함한 전체표면상부에 제1산화막(27)을 일정두께 형성한다.Next, a first oxide film 27 is formed on the entire surface including the trench 25 by a predetermined thickness.
그리고, 상기 제1산화막(27) 상부에 폴리실리콘(29)과 텅스텐 실리사이드(31)를 각각 일정두께 형성한다. (도 2b, 도 2c)In addition, polysilicon 29 and tungsten silicide 31 are formed on the first oxide layer 27 at a predetermined thickness. (FIG. 2B, FIG. 2C)
그 다음, 상기 텅스텐 실리사이드(31)와 상기 폴리실리콘(29)을 에치백하여 활성영역 상부의 상기 텅스텐 실리사이드(31)와 상기 폴리실리콘(29)을 제거함으로써 상기 소자분리막이 형성될 영역의 트렌치(25) 상에만 상기 텅스텐 실리사이드(31)와 상기 폴리실리콘(29) 적층구조를 남긴다.Then, the tungsten silicide 31 and the polysilicon 29 are etched back to remove the tungsten silicide 31 and the polysilicon 29 over the active region, thereby forming a trench in the region where the device isolation layer is to be formed. Only the tungsten silicide 31 and the polysilicon 29 stacked structure are left on the layer 25).
이때, 상기 텅스텐 실리사이드(31)와 상기 폴리실리콘(29)의 식각공정은 에치백 ( etch back ) 공정이나 화학기계연마 ( chemical mechanical polishing ) 방법으로 하부층인 상기 폴리실리콘(29)이 완전히 제거될때까지 실시한다. (도 2d)In this case, the etching process of the tungsten silicide 31 and the polysilicon 29 is performed until the polysilicon 29 as the lower layer is completely removed by an etch back process or chemical mechanical polishing. Conduct. (FIG. 2D)
전체표면상부에 제2산화막(33)을 충분히 두껍게 형성하여 평탄화시킴으로써 상기 산화막(33,27)을 식각하여 상기 트렌치(25)를 매립하는 소자분리막(41)을 형성하되, 상기 소자분리막(41) 내부에 폴리실리콘(29)과 텅스텐 실리사이드(31)의 적층구조가 구비된 소자분리막을 형성한다.The second oxide film 33 is sufficiently thickened and planarized on the entire surface to form the device isolation film 41 which etches the oxide films 33 and 27 and fills the trench 25, wherein the device isolation film 41 is formed. A device isolation film having a stacked structure of polysilicon 29 and tungsten silicide 31 is formed therein.
후속공정으로 금속배선 콘택공정시 콘택시켜 Vcc, Vss 등과 같은 일반적인 전력선으로 사용할 수 있도록 한다. (도 2e, 도 2f)As a follow-up process, contact is made during the metal wiring contact process so that it can be used as a general power line such as Vcc and Vss. (FIG. 2E, FIG. 2F)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 주변회로부의 소자분리막 내부에 폴리실리콘과 텅스텐 실리사이드의 적층구조를 형성하여 후속공정에서 전력배선으로 사용할 수 있도록 함으로써 주변회로부의 고집적화를 가능하게 하는 효과를 제공한다.As described above, in the method of forming a device isolation film of a semiconductor device according to the present invention, a multilayer structure of polysilicon and tungsten silicide is formed inside the device isolation film of the peripheral circuit portion so as to be used as power wiring in a subsequent process, thereby increasing integration of the peripheral circuit portion. It provides the effect of enabling.
Claims (2)
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| KR1019990061859A KR20010063771A (en) | 1999-12-24 | 1999-12-24 | A method for forming a field oxide of a semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101009091B1 (en) * | 2002-12-27 | 2011-01-18 | 크로스텍 캐피탈, 엘엘씨 | CMOS image sensor with reduced crosstalk and method for fabricating thereof |
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1999
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101009091B1 (en) * | 2002-12-27 | 2011-01-18 | 크로스텍 캐피탈, 엘엘씨 | CMOS image sensor with reduced crosstalk and method for fabricating thereof |
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