KR20010063763A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20010063763A KR20010063763A KR1019990061850A KR19990061850A KR20010063763A KR 20010063763 A KR20010063763 A KR 20010063763A KR 1019990061850 A KR1019990061850 A KR 1019990061850A KR 19990061850 A KR19990061850 A KR 19990061850A KR 20010063763 A KR20010063763 A KR 20010063763A
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- insulating film
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- hard mask
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 금속배선 형성공정에서 무기 저유전물질을 층간절연막으로 사용하는 경우 산화막계열의 층간절연막을 증착 및 전면식각하는 공정을 추가로 실시하여 기존의 습식 케미칼(wet chemical)을 사용한 세정공정을 실시할 수 있는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and in particular, when an inorganic low dielectric material is used as an interlayer insulating film in a metal wiring forming process, a process of depositing and etching the interlayer insulating film of an oxide layer by additionally performing conventional wet chemical A method for manufacturing a semiconductor device capable of carrying out a cleaning step using wet chemical.
최근의 반도체장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체장치의 제조공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture : NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.
[ R = k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수 ][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365nm인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet ; DUV), 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광장치를 이용하거나, 공정상의 방법으로는 노광마스크(photo mask)를 위상 반전 마스크(phase shift mask)를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer, 이하 CEL이라 함)방법이나 두 층의 감광막 사이에 SOG 등의 중간층을 개재시킨 삼층레지스트(tri layer resist, TLR) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure using a light source of deep ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or ArF laser having a wavelength of 193 nm, to form a fine pattern of 0.5 µm or less. As an apparatus or a process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. It has been developed, such as silico-migration method for implanting lowering the resolution limit.
또한 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings has a high integration of the device, and the size of the contact holes decreases, and the distance between the peripheral wirings is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이러한 콘택홀은 간격유지를 위하여 마스크 정렬시 오배열의 여유(misalignment tolerance), 노광공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration) 등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes have misalignment tolerance when aligning the mask, lens distortion during the exposure process, critical dimension variation during the mask fabrication and photolithography process, and between masks to maintain the spacing. The mask is formed by considering factors such as registration.
그리고, 콘택홀 형성시 리소그래피(lithography)공정의 한계를 극복하기 위하여 자기 정렬 방법으로 콘택홀을 형성하는 자기정렬콘택(self aligned contact, 이하 SAC 라 함)기술이 개발되었다.In order to overcome the limitations of the lithography process in forming the contact holes, a self aligned contact (SAC) technology for forming contact holes by a self alignment method has been developed.
상기 SAC 방법은 식각장벽층으로 사용하는 물질에 따라 다결정실리콘층이나 질화막 또는 산화질화막 등을 사용하는 것으로 나눌 수 있으며, 가장 유망한 것으로 질화막을 식각방어막으로 사용하는 방법이 있다.The SAC method may be divided into a polysilicon layer, a nitride film, or an oxynitride film according to the material used as the etch barrier layer, and the most promising method is to use a nitride film as an etch barrier.
도시되어 있지는 않으나, 종래 반도체소자의 SAC 제조방법에 관하여 살펴보면 다음과 같다.Although not shown, the SAC manufacturing method of the conventional semiconductor device will be described as follows.
먼저, 반도체기판 상에 소정의 하부구조물, 예를 들어 소자분리 절연막과 게이트 절연막, 마스크 산화막 패턴과 중첩되어 있는 게이트 전극 및 소오스/드레인영역 등의 모스 전계효과 트랜지스터(MOS field effect transistor : 이하 MOS FET 라 함) 등을 형성한 후, 상기 구조의 전표면에 식각방지막과 산화막 재질의 층간절연막을 순차적으로 형성한다.First, a MOS field effect transistor (MOS FET) such as a gate electrode and a source / drain region overlapping a predetermined substructure, for example, a device isolation insulating film, a gate insulating film, and a mask oxide film pattern on a semiconductor substrate. And the like, and then sequentially form an etch stop film and an interlayer insulating film made of an oxide film on the entire surface of the structure.
그 다음, 상기 반도체기판에서 저장전극이나 비트라인 등의 콘택으로 예정되어 있는 부분 상의 층간절연막을 노출시키는 감광막 패턴을 형성한 후, 상기 감광막 패턴에 의해 노출되어 있는 층간절연막을 건식식각하여 식각방지막을 노출시키고, 다시 식각방지막을 식각하여 콘택홀을 형성한다.Next, a photoresist pattern is formed on the semiconductor substrate to expose an interlayer insulating film on a portion of the semiconductor substrate, which is intended to be a contact such as a storage electrode or a bit line. Then, the interlayer insulating film exposed by the photosensitive film pattern is dry-etched to form an etching prevention film. It exposes and etches an etch stop layer again, and forms a contact hole.
상기에서 식각방지막을 다결정실리콘으로 사용하는 경우, 이는 다시 식각방지막을 전면에 형성하는 방법과 콘택홀이 형성될 지역에만 다결정실리콘층 패드를 형성하는 방법으로 나누어지는데, 이러한 다결정실리콘 SAC 방법은 산화막과는 다른 식각기구를 가지는 다결정실리콘을 식각방지막으로 사용하므로 산화막과는 높은 식각선택비차를 얻을 수 있으나, 전면 증착 방법은 콘택홀간의 절연 신뢰성이 떨어지고, 패드를 형성하는 방법은 콘택 패드와 실리콘기판간의 오정렬 발생시 기판에 손상이 발생되는데, 이를 방지하기 위하여 스페이서 또는 폴리머를 사용하여 콘택 패드를 확장시키는 방법이 제시되고 있으나, 이 역시 0.18㎛ 이하의 디자인룰을 실현할 수 없는 문제점이 있다.When the etch barrier is used as polysilicon, it is divided into a method of forming an etch barrier on the front surface and a method of forming a polysilicon layer pad only in a region where a contact hole is to be formed. Such a polysilicon SAC method is characterized in that Since polycrystalline silicon having different etching mechanisms is used as an etch stopper, it is possible to obtain a high etching selectivity difference from an oxide film. However, in the case of the front deposition method, the insulation reliability between contact holes is inferior, and the pad forming method is used between the contact pad and the silicon substrate. When misalignment occurs, damage occurs to the substrate. In order to prevent this, a method of expanding a contact pad using a spacer or a polymer has been proposed, but this also has a problem in that a design rule of 0.18 μm or less can not be realized.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 다마신공정을 사용하여 콘택홀을 형성할 때 층간절연막으로 무기 저유전물질을 사용하는 경우에 트렌치식각, 비아콘택 식각 및 듀얼 다마신식각공정을 진행할 때 금속배선 상부의 하드마스크 및 캐핑절연막을 식각하는 과정에서 사이드월에 금속성 폴리머가 발생하게 된다. 상기 폴리머는 기존의 층간절연막으로 산화막 계열의 유전체를 사용하는 경우와는 다르다. 즉, 무기 저유전물질이 카본(carbon), 수소(hydrogen) 등의 무기성분으로 되어 있어서, 무기성분이 비아콘택 식각공정에서 발생하는 폴리머의 성분에 포함되어 기존의 층간절연막으로 산화막계열의 유전체를 사용하는 경우 사용하던 ACT935, EKC 830 등의 습식 케미칼(wet chemical)을 사용하면 상기 폴리머가 잘 제거되지 않기 때문에 새로운 습식 케미칼을 사용해야 하는 문제점이 있다.As described above, the method of manufacturing a semiconductor device according to the related art uses a trench etching, a via contact etching, and a dual damascene etching process when an inorganic low dielectric material is used as an interlayer insulating layer when forming a contact hole using a damascene process. As it proceeds, a metal polymer is generated in the sidewall during the etching of the hard mask and the capping insulating layer over the metal wiring. The polymer is different from the case of using an oxide-based dielectric as an existing interlayer insulating film. That is, since the inorganic low dielectric material is an inorganic component such as carbon and hydrogen, the inorganic component is included in the polymer component generated in the via contact etching process, and the dielectric of the oxide series is used as an existing interlayer insulating film. In case of using wet chemicals such as ACT935, EKC 830, etc., the new polymer is not easily removed.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 하부의 금속배선이 노출되기 전에 무기 저유전물질을 산화막계열의 유전체로 캐핑시켜 금속배선이 노출되는 과정에서 발생하는 폴리머의 성분이 기존의 층간절연막으로 산화막계열의 유전체를 사용하는 경우와 유사하게 하여 기존의 습식 케미칼을 사용한 세정공정을 가능하게 하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, a polymer component generated in a process of exposing an inorganic low dielectric material to an oxide-based dielectric before the metal wiring is exposed is exposed to a metal wiring. It is an object of the present invention to provide a method of manufacturing a semiconductor device that enables a cleaning process using a conventional wet chemical, similarly to the case of using an oxide-based dielectric as an insulating film.
도 1a 내지 도 1d 는 본 발명의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 2a 내지 도 2d 는 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
도 3a 내지 도 3f 는 본 발명의 제3실시예에 따른 반도체소자의 제조방법을 도시한 단면도.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.
< 도면의 주요부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>
11, 21, 31 : 반도체기판 12, 33 : 제1층간절연막11, 21, 31: semiconductor substrate 12, 33: first interlayer insulating film
13, 22, 32 : 확산방지막 14, 23 : 금속배선13, 22, 32: diffusion barrier 14, 23: metal wiring
15, 24, 34 : 캐핑절연막 16, 25, 35 : 제2층간절연막15, 24, 34: capping insulating film 16, 25, 35: second interlayer insulating film
17, 26 : 하드마스크용 절연막 18, 27 : 감광막패턴17, 26: insulating film for hard mask 18, 27: photoresist pattern
19a, 28a : 산화막 19b, 28b : 산화막 스페이서19a, 28a: oxide film 19b, 28b: oxide film spacer
36 : 제1하드마스크용 절연막 37 : 제1감광막 패턴36: insulating film for first hard mask 37: first photosensitive film pattern
38 : 제3층간절연막 39 : 제2하드마스크용 절연막38: third interlayer insulating film 39: second hard mask insulating film
40 : 제2감광막 패턴40: second photosensitive film pattern
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
캐핑절연막, 무기저유전물질으로 형성된 층간절연막 및 하드마스크용 절연막의 적층구조를 식각하는 공정을 포함하는 반도체소자의 제조방법에 있어서,A method of manufacturing a semiconductor device comprising etching a stacked structure of a capping insulating film, an interlayer insulating film formed of an inorganic low dielectric material, and an insulating film for a hard mask.
절연기판 상부에 확산방지막과 하부금속배선을 형성하는 공정과,Forming a diffusion barrier and a lower metal wiring on the insulating substrate;
전체표면 상부에 캐핑절연막, 무기저유전물질으로 형성된 층간절연막 및 하드마스크용 절연막을 형성하는 공정과,Forming a capping insulating film, an interlayer insulating film formed of an inorganic low dielectric material, and an insulating film for a hard mask on the entire surface thereof;
상기 하드마스크용 절연막 상부에 패턴으로 예정되는 부분을 노출시키는 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern on the hard mask insulating layer to expose a predetermined portion as a pattern;
상기 감광막 패턴을 식각마스크로 사용한 식각공정으로 하드마스크용 절연막과 층간절연막을 식각하여 하드마스크용 절연막 패턴과 층간절연막 패턴을 형성하는 공정과,Etching the hard mask insulating film and the interlayer insulating film by an etching process using the photoresist pattern as an etching mask to form a hard mask insulating film pattern and an interlayer insulating film pattern;
상기 감광막 패턴을 제거하고, 1차세정공정을 실시하는 공정과,Removing the photoresist pattern and performing a primary cleaning step;
전체표면 상부에 산화막을 형성하고 전면식각공정을 실시하여 상기 하드마스크용 절연막 패턴과 층간절연막 패턴의 식각면에 산화막 스페이서를 형성하는 동시에 상기 캐핑절연막을 식각하여 상기 하부금속배선을 노출시키는 공정과,Forming an oxide film on the entire surface and performing an entire surface etching process to form an oxide spacer on the etching surface of the hard mask insulating film pattern and the interlayer insulating film pattern, and etching the capping insulating film to expose the lower metal wiring;
2차세정공정을 실시하는 공정을 포함하는 것을 특징으로 한다.It is characterized by including a step of performing a secondary cleaning process.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d 는 본 발명의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도로서, 금속배선으로 예정되는 부분을 노출시키는 트렌치식각공정을 진행하는 과정을 도시한다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, and illustrate a process of performing a trench etching process for exposing a portion of a semiconductor wiring.
먼저, 반도체기판 (11) 상부에 금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택홀(도시안됨)이 구비된 제1층간절연막(12)을 형성한다.First, a first interlayer insulating film 12 having a metal wiring contact hole (not shown) for exposing a portion intended as a metal wiring contact is formed on the semiconductor substrate 11.
다음, 전체표면 상부에 소정 두께의 확산방지막(13)을 형성하고, 상기 확산방지막(13) 상부에 금속층을 형성한 후 상기 금속층과 확산방지막(13)을 식각하여상기 금속배선 콘택홀을 매립하는 금속배선 콘택플러그(14)를 형성한다.Next, a diffusion barrier 13 having a predetermined thickness is formed on the entire surface, a metal layer is formed on the diffusion barrier 13, and the metal layer and the diffusion barrier 13 are etched to bury the metal wiring contact hole. A metal wiring contact plug 14 is formed.
그 다음, 전체표면 상부에 캐핑절연막(15), 제2층간절연막(16) 및 하드마스크용 절연막(17)을 순차적으로 적층하고, 상기 하드마스크용 절연막(17) 상부에 금속배선으로 예정되는 부분을 노출시키는 감광막 패턴(18)을 형성한다. 이때, 상기 제2층간절연막(16)은 FLARE2.0, SILK 등의 무기 저유전물질을 사용하여 형성하고, 상기 하드마스크용 절연막(17)은 SiO2막또는 SiN막 또는 SiON막 등으로 형성한다. (도 1a 참조)Next, the capping insulating film 15, the second interlayer insulating film 16, and the hard mask insulating film 17 are sequentially stacked on the entire surface, and a portion of the hard mask insulating film 17 that is supposed to be formed of metal wirings. The photosensitive film pattern 18 which exposes this is formed. In this case, the second interlayer insulating film 16 is formed using inorganic low dielectric materials such as FLARE2.0 and SILK, and the hard mask insulating film 17 is formed of SiO 2 film, SiN film, or SiON film. . (See Figure 1A)
다음, 상기 감광막 패턴(18)을 식각마스크로 상기 하드마스크용 절연막(17)과 제2층간절연막(16)을 식각한 후, 상기 감광막 패턴(18)을 제거한다. 이때, 상기 하드마스크용 절연막(17)은 CF계열의 식각가스를 이용하여 제거하고, 무기 저유전물질인 제2층간절연막(16)은 O2/Ar/N2혼합가스를 이용하여 제거한다. 상기 식각공정시 폴리머의 발생을 억제하기 위하여 바이어스 파워(bias power)는 10 ∼ 300W로 인가하거나 소오스파워(source power)에 대비하여 1 ∼ 20% 로 인가하여 스퍼터링효과를 최소화시킨다.Next, the hard mask insulating layer 17 and the second interlayer insulating layer 16 are etched using the photoresist pattern 18 as an etch mask, and then the photoresist pattern 18 is removed. In this case, the hard mask insulating layer 17 is removed using an etching gas of CF series, and the second interlayer insulating layer 16, which is an inorganic low dielectric material, is removed using an O 2 / Ar / N 2 mixed gas. In order to suppress the generation of the polymer during the etching process, a bias power is applied at 10 to 300 W or 1 to 20% compared to source power to minimize the sputtering effect.
그 다음, ACT935, EKC 830등의 습식 케미칼으로 1차 세정공정을 실시하여 상기 제2층간절연막(16)의 식각공정에서 발생한 폴리머를 제거한다. 이때, 상기 1차 세정공정은 탈이온수(deionized water)만을 사용하여 실시할 수 있다. 또한, 상기 제2층간절연막(16)을 O2/N2혼합가스를 사용하여 식각하는 경우 인시튜(in-situ)로 CF4/Ar/O2혼합가스를 사용하여 폴리머를 제거하여 1차 세정공정을 대신할 수 있다.(도 1b 참조)Subsequently, a first cleaning process is performed using wet chemicals such as ACT935 and EKC 830 to remove the polymer generated in the etching process of the second interlayer insulating film 16. In this case, the primary washing process may be performed using only deionized water. In addition, when the second interlayer dielectric layer 16 is etched using the O 2 / N 2 mixed gas, the polymer may be removed in-situ using a CF 4 / Ar / O 2 mixed gas to remove the polymer. It can replace the cleaning process (see Fig. 1b).
다음, 전체표면 상부에 산화막(19a)을 소정 두께 형성하고, 전면식각공정을 실시하여 상기 하드마스크용 절연막(17) 및 제2층간절연막(16)의 식각면에 산화막 스페이서(19b)를 형성하는 동시에 상기 캐핑절연막(15)을 식각하여 상기 비아콘택(14)을 노출시킨다. 여기서, 상기 산화막은 SiO2, SiON 및 SiO2계열의 유기 저유전물질(inorganic low-k dielectric material)로 이루어지는 군에서 임의로 선택된 하나를 사용하여 형성할 수 있고, 상기 제2층간절연막(16)이 노출되지 않게 한다. 상기 SiO2계열의 유기 저유전물질은 SiOC, SiOF, 실록산 SOG, 실리케이트 SOG, HSQ, MSQ, HOSP, LOSP 및 FSG 로 구성된다. (도 1c, 도 1d 참조)Next, an oxide film 19a is formed on the entire surface, and an entire surface etching process is performed to form an oxide spacer 19b on an etching surface of the hard mask insulating film 17 and the second interlayer insulating film 16. At the same time, the capping insulating layer 15 is etched to expose the via contact 14. The oxide film may be formed using one selected from the group consisting of SiO 2 , SiON, and SiO 2 series organic low-k dielectric materials, and the second interlayer insulating film 16 may be formed. Do not expose. The SiO 2 series organic low dielectric material is composed of SiOC, SiOF, siloxane SOG, silicate SOG, HSQ, MSQ, HOSP, LOSP and FSG. (See FIG. 1C, FIG. 1D)
그 다음, 금속층을 형성한 후 CMP공정으로 제거하여 상기 금속배선 콘택플러그(14)와 접속되는 금속배선(도시안됨)을 형성한다.Next, the metal layer is formed and then removed by a CMP process to form a metal wire (not shown) connected to the metal wire contact plug 14.
도 2a 내지 도 2d 는 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도로서, 제1실시예와 같은 방법으로 비아콘택을 형성하는 공정을 도시한다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, and show a process of forming a via contact in the same manner as in the first embodiment.
도 3a 내지 도 3f 는 본 발명의 제3실시예에 따른 반도체소자의 제조방법을 도시한 단면도로서, 제1실시예와 같은 방법으로 듀얼 다마신공정을 사용하여 금속배선을 형성하는 공정을 도시한다.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention, which illustrates a process of forming metal wirings using a dual damascene process in the same manner as in the first embodiment.
상기 듀얼 다마신공정을 사용하는 경우 도 3f 의 ⓐ부분과 같이 제1하드마스크용 절연막(36)의 두께가 얇아질 위험이 있다.In the case of using the dual damascene process, there is a risk that the thickness of the first hard mask insulating layer 36 becomes thin, as shown in ⓐ in FIG. 3F.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 트렌치식각 또는 비아콘택식각 또는 듀얼다마신공정을 이용하여 금속배선을 형성할 때 캐핑절연막/무기저유전물질(organic low-k dielectric material)/하드마스크용 절연막을 피식각층으로 사용하는 경우 감광막 패턴을 식각마스크로 상기 하드마스크용 절연막과 무기저유전체물질을 식각한 후, 상기 감광막 패턴을 제거하고 세정공정을 실시한 다음, 전체표면 상부에 산화막 또는 SiO2계열의 유기저유전물질(inorganic low-k dielectric material)을 전면에 형성한 후 전면식각하여 스페이서를 형성하는 동시에 상기 캐핑절연막을 식각함으로써 상기 무기저유전물질의 식각면이 노출되어 기존에 사용되던 습식 케미칼(wet chemical)으로 제거하기 어려운 폴리머가 발생되는 것을 방지하여 별도의 세정용액을 필요로 하지 않는 이점이 있다.As described above, the method of manufacturing a semiconductor device according to the present invention includes a capping insulating layer / organic low-k dielectric material when forming a metal wiring by using trench etching, via contact etching, or dual damascene process. In the case of using a hard mask insulating film as an etched layer, the hard mask insulating film and the inorganic low dielectric material are etched using the photoresist pattern as an etch mask, and then the photoresist pattern is removed and a cleaning process is performed. Alternatively, an SiO 2 series organic low-k dielectric material may be formed on the entire surface, and then the surface may be etched to form a spacer, and the capping insulating layer may be etched to expose the etching surface of the inorganic low dielectric material. Separate cleaning by preventing the formation of polymers that are difficult to remove by wet chemicals There is an advantage that does not require liquid.
Claims (9)
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100447325B1 (en) * | 2002-12-13 | 2004-09-07 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
| KR100456829B1 (en) * | 2002-06-17 | 2004-11-10 | 삼성전자주식회사 | MIM capacitor compatible to dual damascene and method for fabricating the same |
| KR100751698B1 (en) * | 2006-07-12 | 2007-08-23 | 동부일렉트로닉스 주식회사 | Metal line structure in semiconductor device and method of manufactruing the same |
| KR100906306B1 (en) * | 2002-06-25 | 2009-07-07 | 매그나칩 반도체 유한회사 | Method of forming a copper wiring in a semiconductor device |
| KR100937331B1 (en) * | 2002-06-25 | 2010-01-18 | 매그나칩 반도체 유한회사 | An interlayer insulating film in a semiconductor device |
-
1999
- 1999-12-24 KR KR1019990061850A patent/KR20010063763A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100456829B1 (en) * | 2002-06-17 | 2004-11-10 | 삼성전자주식회사 | MIM capacitor compatible to dual damascene and method for fabricating the same |
| KR100906306B1 (en) * | 2002-06-25 | 2009-07-07 | 매그나칩 반도체 유한회사 | Method of forming a copper wiring in a semiconductor device |
| KR100937331B1 (en) * | 2002-06-25 | 2010-01-18 | 매그나칩 반도체 유한회사 | An interlayer insulating film in a semiconductor device |
| KR100447325B1 (en) * | 2002-12-13 | 2004-09-07 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
| KR100751698B1 (en) * | 2006-07-12 | 2007-08-23 | 동부일렉트로닉스 주식회사 | Metal line structure in semiconductor device and method of manufactruing the same |
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