KR20010061016A - Fabricating method for storage node of semiconductor device - Google Patents

Fabricating method for storage node of semiconductor device Download PDF

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KR20010061016A
KR20010061016A KR1019990063491A KR19990063491A KR20010061016A KR 20010061016 A KR20010061016 A KR 20010061016A KR 1019990063491 A KR1019990063491 A KR 1019990063491A KR 19990063491 A KR19990063491 A KR 19990063491A KR 20010061016 A KR20010061016 A KR 20010061016A
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amorphous silicon
silicon layer
storage electrode
sacrificial insulating
forming
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KR1019990063491A
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Korean (ko)
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KR100346453B1 (en
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김동환
채수진
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for manufacturing a storage electrode of a semiconductor device is provided to maximize the increase of the surface area of the storage electrode, by uniformly forming a meta-stable polysilicon(MPS) layer inside and outside a cylindrical storage electrode. CONSTITUTION: An interlayer dielectric(13) having a storage electrode contact plug(15) is formed on a semiconductor substrate(11) having a predetermined lower structure. After the first sacrificial insulating layer pattern and an etch blocking layer pattern which have a trench exposing a portion of a storage electrode, are formed on the entire surface, a cleaning process is performed. The first amorphous silicon layer of high density is formed on the entire surface. The second amorphous silicon layer of low density is formed on the first amorphous silicon layer. The second sacrificial insulating layer is formed and planarized on the entire surface. The second sacrificial insulating layer, the second amorphous silicon layer, the first amorphous silicon layer and the etch blocking layer pattern are etched separate the upper portion of the second amorphous silicon layer and the first amorphous silicon layer by a chemical mechanical polishing(CMP) process. The second sacrificial insulating layer and the first sacrificial insulating layer pattern are eliminated to form a cylindrical storage electrode(25) composed of the second amorphous silicon layer and the first amorphous silicon layer. A meta-stable polysilicon(MPS) layer of uniform density is formed inside and outside the cylindrical storage electrode.

Description

반도체소자의 저장전극 형성방법{Fabricating method for storage node of semiconductor device}Fabrication method for storage node of semiconductor device

본 발명은 반도체소자의 저장전극 형성방법에 관한 것으로서, 특히 실린더형 저장전극의 내부 및 외부에 준안정다결정실리콘(meta-stable polysilicon, 이하 MPS라 함)막을 균일하게 형성함으로써 저장전극의 표면적을 증가시켜 캐패시터의 정전용량을 증가시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a storage electrode of a semiconductor device. In particular, the surface area of the storage electrode is increased by uniformly forming a meta-stable polysilicon (MPS) film inside and outside the cylindrical storage electrode. To increase the capacitance of a capacitor.

일반적으로, 반도체소자의 고집적화가 1G DRAM급 이상으로 증가됨에 따라 캐패시터의 고정전용량이 요구되고 있다. 이를 해결하기 위해 캐패시터의 유전상수가 높은 물질을 사용하거나 유전체막의 두께를 얇게 하거나 저장전극의 표면적을 증대시키는 방법 등이 대두되고 있다.In general, as the high integration of semiconductor devices is increased to 1G DRAM or more, a fixed capacitance of a capacitor is required. In order to solve this problem, a method of using a material having a high dielectric constant of a capacitor, reducing the thickness of a dielectric film, or increasing the surface area of a storage electrode has emerged.

그러나, 반도체소자가 고집적화되어 갈수록 메모리 단위 소자인 각 셀(cell)에 할당된 면적은 한정이 되어 있기 때문에 저장전극의 표면적을 증가시키기 위하여 일반적으로 실린더형의 저장전극이 사용되고 있다.However, as semiconductor devices become more integrated, an area allocated to each cell, which is a memory unit device, is limited, so that a cylindrical storage electrode is generally used to increase the surface area of the storage electrode.

또한, 저장전극의 표면적을 더욱 증가시키기 위하여 실린더형 저장전극을 형성하고 그 표면에 MPS막을 형성하기도 한다.Further, in order to further increase the surface area of the storage electrode, a cylindrical storage electrode may be formed and an MPS film may be formed on the surface thereof.

상기 MPS막은 비정실리콘에 결정질이 작은 시드(seed)를 형성하고 열처리공정을 통하여 시드를 중심으로 비정실상의 결정질로 변화시켜 가는 공정으로, 저장전극의 증착조건과 밀접한 관계가 있다.The MPS film is a process of forming a seed having a small crystalline in amorphous silicon and changing the amorphous crystalline around the seed through a heat treatment process, and is closely related to the deposition conditions of the storage electrode.

즉, 저장전극을 비정질실리콘층으로 증착되도록 500 ∼ 550℃ 의 온도에서 형성하여야 하며, 인(phosphorus)원자는 입자의 이동을 방해하고 결정질화를 가속화시키므로 인농도를 최대한 낮게 하여야 한다.That is, the storage electrode should be formed at a temperature of 500 ~ 550 ℃ to be deposited as an amorphous silicon layer, and phosphorus (phosphorus) atoms should be as low as possible because phosphorus atoms interfere with the movement of particles and accelerate the crystallization.

그러나, 통상의 다결정실리콘층의 증착방법으로 증착하는 경우에는 실리콘 내의 인 농도를 SIMS(secondary ion mass spectroscopy)를 이용하여 측정하면 도 1 의 그래프와 같이 실리콘이 증착되기 시작하는 부분과 증착이 끝나는 부분의 농도가 서로 다른 것을 알 수 있다. 이것은 인원자가 실리콘 내부에 용해될 때 막 내에 스트레스가 증가하여 스트레스를 감소시키는 방향으로 이동하여 실리콘 표면으로 축적되어 나타나는 현상이다.However, in the case of depositing by the conventional method of depositing a polysilicon layer, when the phosphorus concentration in the silicon is measured by using secondary ion mass spectroscopy (SIMS), as shown in the graph of FIG. It can be seen that the concentrations of are different. This is a phenomenon in which when a person dissolves inside the silicon, the stress increases in the film and moves in the direction of decreasing the stress, which accumulates on the silicon surface.

따라서, 통상의 방법으로 다결정실리콘층을 증착하고 MPS막의 증착공정을 진행할 경우에 있어서도 도 2a 및 도 2b 와 같이 실린더의 내벽과 외벽에 MPS막의 성장정도가 다르기 때문에 MPS 그레인(grain)의 밀도 차이가 나고, 결국 캐패시터의 캐패시턴스 저하를 일으키는 문제점이 있다.Therefore, even when the polysilicon layer is deposited by the conventional method and the deposition process of the MPS film is performed, the density difference of the MPS grain is different because the degree of growth of the MPS film is different on the inner and outer walls of the cylinder as shown in FIGS. 2A and 2B. In other words, there is a problem in that the capacitance of the capacitor is reduced.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 저장전극으로 예정되는 부분을 노출시키는 트렌치가 구비된 희생절연막패턴을 형성하고, 2단계에 거쳐 비정질실리콘층을 형성하되, PH3가스의 양을 서로 다르게 사용하여 형성된 비정질실리콘층을 사용하여 실린더형 저장전극을 형성함으로써 상기 실린더형 저장전극의 내부 및 외부에 균일한 밀도로 MPS막을 증착시켜 캐패시터의 캐패시턴스를 증가시키는 반도체소자의 저장전극 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, a sacrificial insulating film pattern having a trench for exposing a predetermined portion of the storage electrode is formed, and an amorphous silicon layer is formed in two steps, but the amount of PH 3 gas is increased. To form a cylindrical storage electrode using an amorphous silicon layer formed by using differently, depositing an MPS film at a uniform density inside and outside the cylindrical storage electrode to increase the capacitance of the capacitor. The purpose is to provide.

도 1 은 다결정실리콘내의 인(phosphorus)농도를 SIMS(secondary ion mass spectroscopy)으로 측정하여 도시한 그래프도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a graph illustrating the measurement of phosphorus concentration in polycrystalline silicon by secondary ion mass spectroscopy (SIMS).

도 2a 내지 도 2c 는 종래기술에 따른 반도체소자의 저장전극 형성방법에 의해 형성된 실린더형 저장전극의 내부 및 외부를 나타내는 사진.Figure 2a to 2c is a photograph showing the inside and outside of the cylindrical storage electrode formed by a storage electrode forming method of a semiconductor device according to the prior art.

도 3a 내지 도 3c 는 본 발명에 따른 반도체소자의 저장전극 형성방법을 도시한 단면도.3A to 3C are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the present invention.

도 4a 및 도 4b 는 본 발명에 따른 반도체소자의 저장전극 형성방법에 의해 형성된 실린더형 저장전극의 내부 및 외부를 나타내는 사진.4a and 4b are photographs showing the inside and outside of the cylindrical storage electrode formed by the storage electrode forming method of the semiconductor device according to the present invention.

<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>

11 : 반도체기판 13 : 층간절연막11 semiconductor substrate 13 interlayer insulating film

15 : 저장전극 콘택플러그 17 : 희생절연막패턴15: storage electrode contact plug 17: sacrificial insulating film pattern

19 : 식각방지막 21 : 제1비정질실리콘층19: etching prevention film 21: first amorphous silicon layer

23 : 제2비정질실리콘층 25 : 저장전극23: second amorphous silicon layer 25: the storage electrode

이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 저장전극 형성방법은,In order to achieve the above object, the storage electrode forming method of the semiconductor device according to the present invention,

소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택플러그가 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a storage electrode contact plug on the semiconductor substrate having a predetermined lower structure formed thereon;

전체표면 상부에 저장전극으로 예정되는 부분을 노출시키는 트렌치가 구비된 제1희생절연막패턴 및 식각방지막패턴을 형성한 다음, 세정공정을 실시하는 공정과,Forming a first sacrificial insulating film pattern and an etch stop layer pattern having a trench exposing a portion intended as a storage electrode on the entire surface, and then performing a cleaning process;

전체표면 상부에 고농도의 제1비정질실리콘층을 형성하는 공정과,Forming a high concentration of the first amorphous silicon layer on the entire surface,

상기 제1비정질실리콘층 상부에 저농도의 제2비정질실리콘층을 형성하는 공정과,Forming a low concentration of the second amorphous silicon layer on the first amorphous silicon layer;

전체표면 상부에 제2희생절연막을 형성하여 평탄화시킨 후, 상기 제2희생절연막, 제2비정질실리콘층, 제1비정질실리콘층 및 식각방지막패턴을 화학적 기계적 연마공정으로 식각하여 상기 제2비정질실리콘층 및 제1비정질실리콘층의 상부를 분리시키는 공정과,After the second sacrificial insulating film is formed and planarized on the entire surface, the second sacrificial insulating film, the second amorphous silicon layer, the first amorphous silicon layer, and the etch stop layer pattern are etched by chemical mechanical polishing to form the second amorphous silicon layer. And separating an upper portion of the first amorphous silicon layer;

상기 제2희생절연막 및 제1희생절연막패턴을 제거하여 상기 제2비정질실리콘층 및 제1비정질실리콘층으로 형성된 실린더형 저장전극을 형성하는 공정과,Removing the second sacrificial insulating film and the first sacrificial insulating film pattern to form a cylindrical storage electrode formed of the second amorphous silicon layer and the first amorphous silicon layer;

상기 실린더형 저장전극의 내부 및 외부에 준안정다결정실리콘막을 균일한 밀도로 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a metastable polycrystalline silicon film at a uniform density inside and outside the cylindrical storage electrode.

이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.

도 3a 내지 도 3c 는 본 발명에 따른 반도체소자의 저장전극 형성방법을 도시한 단면도이다.3A to 3C are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the present invention.

먼저, 반도체기판(11)에서 소자분리영역으로 예정되는 부분에 소자분리 산화막을 형성하고, 게이트 산화막(도시안됨)을 형성한 다음, 게이트 전극(도시안됨)과 소오스/드레인전극(도시안됨)으로 구성되는 모스 전계효과 트랜지스터와 비트라인(도시안됨)을 형성하고, 전체표면 상부에 저장전극콘택으로 예정되는 부분에 접속하는 저장전극 콘택플러그(15)가 구비된 층간절연막(13)을 형성한다.First, a device isolation oxide film is formed on a portion of the semiconductor substrate 11 to be a device isolation region, a gate oxide film (not shown) is formed, and then a gate electrode (not shown) and a source / drain electrode (not shown) are formed. A MOS field effect transistor and a bit line (not shown) are formed, and an interlayer insulating film 13 having a storage electrode contact plug 15 connected to a portion intended as a storage electrode contact is formed on the entire surface.

다음, 전체표면 상부에 희생절연막과 식각방지막을 순차적으로 형성하고, 저장전극으로 예정되는 부분을 노출시키는 저장전극마스크를 식각마스크로 상기 식각방지막과 희생절연막을 식각하여 상기 저장전극콘택플러그(15)를 노출시키는 희생절연막패턴(17)과 식각방지막패턴(19)을 형성한다. (도 3a 참조)Next, the sacrificial insulating film and the etch stop layer are sequentially formed on the entire surface, and the etch stop layer and the sacrificial insulating layer are etched using a storage electrode mask that exposes a portion intended to be a storage electrode as an etch mask. The sacrificial insulating layer pattern 17 and the etch stop layer pattern 19 exposing the portions are formed. (See Figure 3A)

그 다음, 전체표면 상부에 저장전극으로 사용될 도전층을 형성한다. 이때, 상기 도전층은 2단계로 증착되며, 증착조건은 다음과 같다.Next, a conductive layer to be used as a storage electrode is formed on the entire surface. At this time, the conductive layer is deposited in two steps, the deposition conditions are as follows.

먼저, 전체표면 상부에 500 ∼ 550℃의 온도 및 0.5 ∼ 1.5torr의 압력하에서 SiH4/PH3가스 또는 Si2H6/PH3가스를 반응시켜 제1비정질실리콘층(21)을 증착한다. 이때, 상기 제1비정질실리콘층(21)을 형성하는 가스중에서 상기 PH3의 농도는 0.5 ∼ 2.0E20atoms/cc로 하고, 상기 제1비정질실리콘층(21)의 두께는 형성하고자 하는 저장전극 두께의 50 ∼ 90%를 형성한다.First, the first amorphous silicon layer 21 is deposited by reacting SiH 4 / PH 3 gas or Si 2 H 6 / PH 3 gas at a temperature of 500 to 550 ° C. and a pressure of 0.5 to 1.5 torr on the entire surface. In this case, the concentration of the PH 3 in the gas forming the first amorphous silicon layer 21 is 0.5 to 2.0E20 atoms / cc, and the thickness of the first amorphous silicon layer 21 is the thickness of the storage electrode to be formed. It forms 50-90%.

다음, 상기 제1비정질실리콘층(21) 상부에 500 ∼ 550℃의 온도 및 0.5 ∼ 1.5torr의 압력하에서 SiH4/PH3가스 또는 Si2H6/PH3가스를 사용하여 나머지 두께의 제2비정질실리콘층(23)을 형성한다. 이때, 상기 제2비정질실리콘층(23)을 형성하는 가스중에서 상기 PH3의 농도는 상기 제1비정질실리콘층의 형성공정시 사용된 PH3농도의 0 ∼ 50%로 한다. (도 3b 참조)Next, a second thickness of the remaining thickness using SiH 4 / PH 3 gas or Si 2 H 6 / PH 3 gas at a temperature of 500 to 550 ° C. and a pressure of 0.5 to 1.5 torr on the first amorphous silicon layer 21. An amorphous silicon layer 23 is formed. In this case, the concentration of PH 3 in the gas forming the second amorphous silicon layer 23 is 0 to 50% of the concentration of PH 3 used in the process of forming the first amorphous silicon layer. (See Figure 3b)

그 다음, 전체표면 상부에 희생절연막을 형성하여 평탄화시킨 후, CMP공정 또는 전면식각공정으로 상기 희생절연막, 제2비정질실리콘층(23), 제1비정질실리콘층(21) 및 식각방지막패턴(29)을 제거하여 저장전극(25)을 형성한다. 이때, 상기 저장전극(25)은 이너실린더형 저장전극이지만, 아우터실린더형 저장전극도 사용될 수 있다. (도 3c 참조)Next, a sacrificial insulating film is formed on the entire surface of the sacrificial insulating film and planarized, and then the sacrificial insulating film, the second amorphous silicon layer 23, the first amorphous silicon layer 21, and the etch stop layer pattern 29 are formed by a CMP process or an entire surface etching process. ) Is removed to form the storage electrode 25. In this case, the storage electrode 25 is an inner cylinder type storage electrode, but an outer cylinder type storage electrode may also be used. (See Figure 3c)

다음, 상기 저장전극(25)의 표면에 MPS막(도시안됨)을 형성하면, 도 4a 및 도 4b 에 나타난 것과 같이 실린더 내부 및 외부에 균일하게 MPS막이 형성된 것을 알 수 있다.Next, when the MPS film (not shown) is formed on the surface of the storage electrode 25, it can be seen that the MPS film is uniformly formed inside and outside the cylinder as shown in FIGS. 4A and 4B.

그 후, 유전체막 및 상부전극을 형성하여 캐패시터를 완성한다.Thereafter, a dielectric film and an upper electrode are formed to complete the capacitor.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 저장전극 형성방법은, 실린더형 저장전극을 형성하는 공정시 저장전극용 도전층으로 사용될 비정질실리콘층을 2단계로 형성하되, PH3의 농도를 서로 다르게 사용하여 형성함으로써 후속 MPS막이 실린더형 저장전극의 내부 및 외부에 균일한 밀도로 형성되고 그로 인하여 저장전극의 표면적 증가를 더욱 극대화하여 캐패시터의 정전용량을 증가시킬 수 있고, 그에 따른 소자의 특성 및 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 이점이 있다.As described above, in the method of forming the storage electrode of the semiconductor device according to the present invention, the amorphous silicon layer to be used as the conductive layer for the storage electrode in the process of forming the cylindrical storage electrode is formed in two steps, and the concentration of PH 3 By forming differently, the subsequent MPS film is formed at a uniform density inside and outside of the cylindrical storage electrode, thereby maximizing the increase of the surface area of the storage electrode, thereby increasing the capacitance of the capacitor, and thus the characteristics of the device and There is an advantage of improving reliability and enabling high integration of semiconductor devices.

Claims (8)

소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택플러그가 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a storage electrode contact plug on the semiconductor substrate having a predetermined lower structure formed thereon; 전체표면 상부에 저장전극으로 예정되는 부분을 노출시키는 트렌치가 구비된 제1희생절연막패턴 및 식각방지막패턴을 형성한 다음, 세정공정을 실시하는 공정과,Forming a first sacrificial insulating film pattern and an etch stop layer pattern having a trench exposing a portion intended as a storage electrode on the entire surface, and then performing a cleaning process; 전체표면 상부에 고농도의 제1비정질실리콘층을 형성하는 공정과,Forming a high concentration of the first amorphous silicon layer on the entire surface, 상기 제1비정질실리콘층 상부에 저농도의 제2비정질실리콘층을 형성하는 공정과,Forming a low concentration of the second amorphous silicon layer on the first amorphous silicon layer; 전체표면 상부에 제2희생절연막을 형성하여 평탄화시킨 후, 상기 제2희생절연막, 제2비정질실리콘층, 제1비정질실리콘층 및 식각방지막패턴을 화학적 기계적 연마공정으로 식각하여 상기 제2비정질실리콘층 및 제1비정질실리콘층의 상부를 분리시키는 공정과,After the second sacrificial insulating film is formed and planarized on the entire surface, the second sacrificial insulating film, the second amorphous silicon layer, the first amorphous silicon layer, and the etch stop layer pattern are etched by chemical mechanical polishing to form the second amorphous silicon layer. And separating an upper portion of the first amorphous silicon layer; 상기 제2희생절연막 및 제1희생절연막패턴을 제거하여 상기 제2비정질실리콘층 및 제1비정질실리콘층으로 형성된 실린더형 저장전극을 형성하는 공정과,Removing the second sacrificial insulating film and the first sacrificial insulating film pattern to form a cylindrical storage electrode formed of the second amorphous silicon layer and the first amorphous silicon layer; 상기 실린더형 저장전극의 내부 및 외부에 준안정다결정실리콘막을 균일한 밀도로 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 저장전극 형성방법.And forming a metastable polycrystalline silicon film at a uniform density inside and outside the cylindrical storage electrode. 제 1 항에 있어서,The method of claim 1, 상기 제1비정질실리콘층은 500 ∼ 550℃의 온도 및 0.5 ∼ 1.5torr의 압력하에서 SiH4/PH3가스 또는 Si2H6/PH3가스를 사용하여 형성하는 것을 특징으로 하는 반도체소자의 저장전극 형성방법.The first amorphous silicon layer is formed using a SiH 4 / PH 3 gas or a Si 2 H 6 / PH 3 gas at a temperature of 500 to 550 ° C. and a pressure of 0.5 to 1.5 torr. Formation method. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제1비정질실리콘층의 두께는 형성하고자하는 저장전극 두께의 50 ∼ 90%를 형성하는 것을 특징으로 하는 반도체소자의 저장전극 형성방법.The thickness of the first amorphous silicon layer is formed to form a storage electrode of the semiconductor device, characterized in that 50 to 90% of the thickness of the storage electrode to be formed. 제 2 항에 있어서,The method of claim 2, 상기 PH3의 농도는 0.5 ∼ 2.0E20atoms/cc인 것을 특징으로 하는 반도체소자의 저장전극 형성방법.The concentration of the PH 3 is 0.5 to 2.0E20 atoms / cc storage electrode formation method of a semiconductor device, characterized in that. 제 1 항에 있어서,The method of claim 1, 상기 제2비정질실리콘층은 500 ∼ 550℃의 온도 및 0.5 ∼ 1.5torr의 압력하에서 형성하는 것을 특징으로 하는 반도체소자의 저장전극 형성방법.The second amorphous silicon layer is formed under a temperature of 500 to 550 ° C. and a pressure of 0.5 to 1.5 torr. 제 1 항에 있어서,The method of claim 1, 상기 제2비정질실리콘층은 SiH4/PH3가스 또는 Si2H6/PH3가스를 사용하여 형성하는 것을 특징으로 하는 반도체소자의 저장전극 형성방법.The second amorphous silicon layer is formed using a SiH 4 / PH 3 gas or Si 2 H 6 / PH 3 gas, the storage electrode forming method of a semiconductor device. 제 6 항에 있어서,The method of claim 6, 상기 PH3의 농도는 상기 제1비정질실리콘층의 형성공정시 사용된 PH3농도의 0 ∼ 50%인 것을 특징으로 하는 반도체소자의 저장전극 형성방법.Wherein the concentration of PH 3 is 0-50% of the concentration of PH 3 used in the process of forming the first amorphous silicon layer. 제 1 항에 있어서,The method of claim 1, 상기 실린더형 저장전극은 이너실린더형 또는 아우터실린더형 저장전극인 것을 특징으로 하는 반도체소자의 저장전극 형성방법.And the cylindrical storage electrode is an inner cylinder type or an outer cylinder type storage electrode.
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