KR20010058541A - A method for forming metal wire in semiconductor device - Google Patents
A method for forming metal wire in semiconductor device Download PDFInfo
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- KR20010058541A KR20010058541A KR1019990065884A KR19990065884A KR20010058541A KR 20010058541 A KR20010058541 A KR 20010058541A KR 1019990065884 A KR1019990065884 A KR 1019990065884A KR 19990065884 A KR19990065884 A KR 19990065884A KR 20010058541 A KR20010058541 A KR 20010058541A
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- film
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- semiconductor device
- aluminum
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 25
- 239000002184 metal Substances 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010936 titanium Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims 1
- 238000001552 radio frequency sputter deposition Methods 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 7
- 238000005240 physical vapour deposition Methods 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 238000001465 metallisation Methods 0.000 abstract description 2
- 229910008479 TiSi2 Inorganic materials 0.000 abstract 3
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract 3
- 229910010039 TiAl3 Inorganic materials 0.000 abstract 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 15
- 239000010410 layer Substances 0.000 description 13
- 229910008484 TiSi Inorganic materials 0.000 description 9
- 229910010038 TiAl Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- YPSXFMHXRZAGTG-UHFFFAOYSA-N 4-methoxy-2-[2-(5-methoxy-2-nitrosophenyl)ethyl]-1-nitrosobenzene Chemical compound COC1=CC=C(N=O)C(CCC=2C(=CC=C(OC)C=2)N=O)=C1 YPSXFMHXRZAGTG-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 150000003608 titanium Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 제조기술에 관한 것으로, 특히 반사방지막 깨짐 방지를 위한 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a method of forming metal wiring for preventing an antireflection film from breaking.
일반적으로 반도체 소자의 금속배선 공정에서는 금속막의 표면 반사율이 매우 높기 때문에 감광막 도포 전에 배선용 금속 상부에 반사방지막(Anti-Reflective Coating, 이하 ARC라 약칭함)을 사용하고 있다.In general, in the metal wiring process of the semiconductor device, since the surface reflectivity of the metal film is very high, an anti-reflective coating (abbreviated as ARC) is used on the wiring metal before the photosensitive film is applied.
일반적인 ARC의 재료로는 티타늄(Ti)막과 질화티타늄(TiN)막을 적층구조로 형성한 Ti/TiN막을 사용하고 있다.As a general ARC material, a Ti / TiN film having a laminated structure of a titanium (Ti) film and a titanium nitride (TiN) film is used.
도 1a 내지 도 1d는 종래 기술에 따른 금속배선 형성공정을 도시한 도면으로써, 이하 이를 참조하여 설명하기로 한다.1A to 1D illustrate a metal wiring forming process according to the prior art, which will be described below with reference to the drawings.
우선, 도 1a에 도시된 바와 같이 소정의 하부층 공정이 완료된 반도체 기판(10) 상부에 금속배선 형성을 위한 Al막(11)을 형성한다.First, as shown in FIG. 1A, an Al film 11 for forming metal wiring is formed on the semiconductor substrate 10 on which a predetermined lower layer process is completed.
다음으로, 도1b에 도시된 바와 같이 Al막(11) 상부에 Ti막(13) 및 TiN막(14)으로 이루어진 적층구조의 ARC를 형성한다. 이때, 상기 Ti막(13)과 상기 알루미늄막(11)과의 계면에 서로간의 반응으로 인하여 얇은 TiAl3막(12)이 형성된다.Next, as shown in FIG. 1B, an ARC having a laminated structure including a Ti film 13 and a TiN film 14 is formed on the Al film 11. At this time, a thin TiAl 3 film 12 is formed at the interface between the Ti film 13 and the aluminum film 11 by mutual reaction.
다음으로, 도1c에 도시된 바와 같이 TiN막(14)의 상부에 감광막 패턴(15)을 형성하고, 이를 마스크로 하여 도1d에 도시된 바와 같이 TiN막(14), Ti막(13) 및 알루미늄막(11)을 선택식각한 후 감광막 패턴(15)을 제거하여 금속배선 패턴을 형성한다.Next, as shown in FIG. 1C, a photosensitive film pattern 15 is formed on the TiN film 14, and as a mask, the TiN film 14, the Ti film 13, and After etching the aluminum film 11 selectively, the photosensitive film pattern 15 is removed to form a metal wiring pattern.
그러나, 이때 상기 Al막(11) 식각 후 고온에서의 감광막 패턴(15) 제거 시에 상기 Al막(11)과 적층구조의 ARC인 Ti막(13)/TiN막(14)과의 열팽창계수 차이에 의하여 TiN막(14)이 깨지거나 벗겨지는 현상이 발생하게 되는 문제점이 발생하게 된다.However, at this time, when the photoresist layer pattern 15 is removed at a high temperature after etching the Al layer 11, the thermal expansion coefficient difference between the Al layer 11 and the Ti layer 13 / TiN layer 14, which is ARC in a laminated structure, is different. This causes the problem that the TiN film 14 is broken or peeled off.
보다 구체적으로 설명하면, Al막(11)은 Ti막(13) 및 TiN막(14)에 비하여 열팽창계수가 3배정도 크기 때문에 감광막 패턴(15) 제거 시에 발생하는 고온에 의해 Al막(11)이 팽창을 하게되고, Al막(11)상부에 증착되어 있는 얇은 Ti막(13) 및 TiN막(14)이 인장응력을 받게 된다. 그러나, Al막(11)과 Ti막(13)은 서로의 접착력이 TiN막(14)에 비해서 우수하기 때문에, 인장응력을 받게될 경우 TiN막(14)이 벗겨지거나 깨지는 현상이 발생하게 된다.More specifically, the Al film 11 is about three times larger in thermal expansion coefficient than the Ti film 13 and the TiN film 14, and thus the Al film 11 is caused by the high temperature generated when the photosensitive film pattern 15 is removed. This expansion causes the thin Ti film 13 and the TiN film 14 deposited on the Al film 11 to undergo tensile stress. However, since the Al film 11 and the Ti film 13 have superior adhesion to each other than the TiN film 14, the TiN film 14 is peeled off or broken when tensile stress is applied.
이와 같은 문제는, 벗겨지거나 깨진 TiN막(14)이 금속배선에서 떨어져 나가 금속배선간의 단선 및 합선을 초래하는 문제점으로 대두되고 있다.Such a problem has arisen as a problem that the peeled or broken TiN film 14 falls out of the metal wiring and causes disconnection and short circuit between the metal wirings.
본 발명은 금속배선 형성 시 단선 및 합선을 방지할 수 있는 보다 안정된 반도체 소자 제조 방법을 제공하는 데 그 목적이 있다.An object of the present invention is to provide a more stable method for manufacturing a semiconductor device that can prevent disconnection and short-circuit when forming metal wiring.
도1a 내지 도1d는 종래 기술에 따른 금속배선 형성공정을 도시한 도면.1A to 1D illustrate a metal wiring forming process according to the prior art.
도2a 내지 도2e는 본 발명의 일실시예에 따른 금속배선 형성공정을 도시한 도면.2a to 2e are views illustrating a metal wiring forming process according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 간단한 설명* Brief description of symbols for the main parts of the drawings
20 : 반도체 기판 21 : Al막20 semiconductor substrate 21 Al film
22 : TiAl3막 25 : TiSi2막22: TiAl 3 film 25: TiSi 2 film
26 : SiON막26: SiON film
상기 목적을 달성하기 위한 본 발명은, 소정의 하부층 상에 배선용 알루미늄막을 형성하는 제1 단계; 상기 알루미늄막 상에 티타늄실리사이드막을 형성하는 제2 단계; 상기 티타늄실리사이드막 상에 실리콘산화질화막을 형성하는 제3 단계; 상기 실리콘산화질화막 및 상기 티타늄실리사이드막을 반사방지막으로 사용한 상기 알루미늄막을 패터닝하는 제4 단계를 포함하여 이루어진다.The present invention for achieving the above object, the first step of forming a wiring aluminum film on a predetermined lower layer; Forming a titanium silicide film on the aluminum film; Forming a silicon oxynitride layer on the titanium silicide layer; And a fourth step of patterning the aluminum film using the silicon oxynitride film and the titanium silicide film as an anti-reflection film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도 2a 내지 도 2e는 본 발명의 일실시예에 따른 금속배선 형성공정을 도시한 도면이다.2A to 2E are diagrams illustrating a metal wiring forming process according to an embodiment of the present invention.
본 실시예에 따른 공정은 우선, 도 2a에 도시된 바와 같이 소정의 하부층 공정이 완료된 반도체 기판(20) 상부에 금속배선 형성을 위한 알루미늄막(21)을 물리 기상 증착(Physical Vapor Deposition, PVD)법을 사용하여 형성한다.In the process according to the present embodiment, physical vapor deposition (PVD) is performed on the aluminum film 21 for forming metal wiring on the semiconductor substrate 20 on which the predetermined lower layer process is completed, as shown in FIG. 2A. Form using the law.
다음으로, 도 2b에 도시된 바와 같이 알루미늄막(21)의 상부에 접착층 역할을 할 수 있는 Ti막(23)을 100Å 내지 200Å정도 형성한다. 이때, 상기 Ti막(23)과 상기 알루미늄막(11)과의 계면에 서로간의 반응으로 인해 얇은 TiAl3막(22)이 형성된다. 또한, 상기 Ti막(23)의 형성을 인-시츄(IN-SITU)가 아닌 익스-시츄(EX-SITU)로 진행할 경우에는 Ti막(23) 형성 전에 알루미늄막(21) 상부에 남아있을지도 모르는 자연산화막의 제거를 위해서 RF-스퍼터 식각(RF-sputter etch) 공정을 실시한 후 Ti막(23)을 형성한다.Next, as shown in FIG. 2B, a Ti film 23, which may serve as an adhesive layer, is formed on the upper portion of the aluminum film 21 to about 100 μs to 200 μs. At this time, a thin TiAl 3 film 22 is formed at the interface between the Ti film 23 and the aluminum film 11 by mutual reaction. In addition, when the formation of the Ti film 23 proceeds to EX-SITU instead of IN-SITU, the Ti film 23 may remain above the aluminum film 21 before the Ti film 23 is formed. In order to remove the native oxide film, the Ti film 23 is formed after the RF-sputter etching process.
계속하여, 인-시츄로 Ti막(23)상부에 PVD법으로 Si막(24)을 50Å 내지 150Å정도 형성한다. 여기서, Si막(24)을 PVD법으로 형성하는 이유는 화학 기상 증착(Chemical Vapor Deposition, CVD)법은 고온공정으로 이루어지기 때문에 알루미늄막(21)의 플로우(Flow)가 발생할 수 있기 때문이고, 공정시간을 단축하기 위함이다.Subsequently, the Si film 24 is formed on the Ti film 23 by the PVD method by about 50 mV to 150 mV in-situ. Here, the reason why the Si film 24 is formed by the PVD method is that since the chemical vapor deposition (CVD) method is performed at a high temperature process, a flow of the aluminum film 21 may occur. This is to shorten the process time.
다음으로, 도2c에 도시된 바와 같이 400℃ 내지 600℃정도의 온도조건에서N2를 가하면서 0.5 ~ 3시간 동안 열처리(Annealing)을 실시하면, Ti막(23)과 Si막(24)이 반응하여 TiSi2막(25)을 형성하게 된다.Next, as shown in FIG. 2C, when annealing is performed for 0.5 to 3 hours while applying N 2 at a temperature of 400 ° C. to 600 ° C., the Ti film 23 and the Si film 24 are formed. React to form the TiSi 2 film 25.
다음으로, 도2d에 도시된 바와 같이 TiSi2막(25) 상부에 SiON막(26)을 350 ~ 600℃의 온도조건에서 플라즈마여기 화학기상증착(Plasma Enhanced Chemical Vapor Deposition, PE-CVD)법으로 증착한 후 SiON막(26)의 상부에 감광막 패턴(27)을 형성한다.Next, as shown in FIG. 2D, the SiON film 26 is deposited on the TiSi 2 film 25 by a plasma enhanced chemical vapor deposition (PE-CVD) method at a temperature of 350 to 600 ° C. After the deposition, a photosensitive film pattern 27 is formed on the SiON film 26.
다음으로, 도2e에 도시된 바와 같이 감광막 패턴(27)을 식각마스크로 하여 SiON막(26), TiSi2막(25), TiAl3막(22) 및 Al막(21)을 선택식각한 후 감광막 패턴(27)을 제거하여 금속배선 형성공정을 완료한다. 여기서, 상기 선택식각은 건식식각법을 사용하되, SiON막(25) 및 TiSi2막(25)의 식각은 C2F6와 CHF3가스 또는 CF4가스를 단독 혹은 혼합으로 사용하여 식각하고, TiAl3막(22) 및 Al막(21)의 식각은 식각조건을 변경하여 Cl2가스 또는 BCl2가스를 단독 혹은 혼합으로 사용하여 식각한다.Next, as illustrated in FIG. 2E, the SiON film 26, the TiSi 2 film 25, the TiAl 3 film 22, and the Al film 21 are selectively etched using the photoresist pattern 27 as an etching mask. The photosensitive film pattern 27 is removed to complete the metallization forming process. Here, the selective etching is a dry etching method, the etching of the SiON film 25 and the TiSi 2 film 25 is etched using C 2 F 6 and CHF 3 gas or CF 4 gas alone or in combination, The TiAl 3 film 22 and the Al film 21 are etched by changing the etching conditions and using Cl 2 gas or BCl 2 gas alone or in combination.
이렇듯 본 발명은, 종래의 Ti/TiN의 적층구조로 이루어진 ARC 대신에 Ti/Si층을 형성하고, 이를 열처리하여 TiSi2층을 형성한 후 다시 SiON을 증착한 구조의 ARC를 사용하여 이루어진다. 이와 같은 구조로써, 고온공정 시 발생할 수 있는 금속배선과 ARC간의 분리 또는 ARC의 깨짐 등의 현상을 방지할 수 있다. 이는, 통상적인 금속배선 재료인 Al과 TiSi2와는 우수한 결합력을 가지고 있고, TiSi2와 SiON과도 우수한 결합력을 가지고 있기 때문이다.As described above, the present invention is achieved by using an ARC having a structure in which a Ti / Si layer is formed instead of an ARC formed of a conventional Ti / TiN layer, and then heat-treated to form a TiSi 2 layer and then depositing SiON. With such a structure, it is possible to prevent a phenomenon such as separation between metal wiring and ARC or cracking of ARC, which may occur during a high temperature process. This is because Al and TiSi 2 , which are common metal wiring materials, have excellent bonding strength, and TiSi 2 and SiON also have excellent bonding strength.
또한, TiSi2형성을 위한 열처리 동안 금속배선인 Al도 어닐링됨에 따라 그레인 크기(Grain size)가 커지게 되어 금속배선의 응력유도 이탈과 전자이탈효과를 방지할 수 있게 된다.In addition, as the Al wire, which is a metal wiring, is also annealed during the heat treatment for forming TiSi 2 , the grain size becomes large, thereby preventing the stress induced release and electron escape effect of the metal wiring.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 금속배선 형성 시 단선 및 합선을 방지할 수 있는 효과를 얻을 수 있다.The present invention can obtain the effect of preventing the disconnection and short-circuit when forming the metal wiring.
Claims (6)
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| KR1019990065884A KR20010058541A (en) | 1999-12-30 | 1999-12-30 | A method for forming metal wire in semiconductor device |
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| KR1019990065884A KR20010058541A (en) | 1999-12-30 | 1999-12-30 | A method for forming metal wire in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100800819B1 (en) * | 2006-12-27 | 2008-02-01 | 동부일렉트로닉스 주식회사 | Method for providing rework of semiconductor metal pattern |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01253256A (en) * | 1988-03-31 | 1989-10-09 | Nec Corp | Formation of wiring |
| JPH06275574A (en) * | 1993-03-18 | 1994-09-30 | Sony Corp | Dry etching method |
| JPH07201859A (en) * | 1993-12-29 | 1995-08-04 | Sony Corp | Wiring formation method and semiconductor device |
| KR970052340A (en) * | 1995-12-23 | 1997-07-29 | 김주용 | Metal wiring formation method of semiconductor device |
| KR970052431A (en) * | 1995-12-29 | 1997-07-29 | 김주용 | Metal wiring formation method of semiconductor device |
| KR19980031847A (en) * | 1996-10-31 | 1998-07-25 | 김영환 | Metal wiring formation method of semiconductor device |
-
1999
- 1999-12-30 KR KR1019990065884A patent/KR20010058541A/en not_active Application Discontinuation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01253256A (en) * | 1988-03-31 | 1989-10-09 | Nec Corp | Formation of wiring |
| JPH06275574A (en) * | 1993-03-18 | 1994-09-30 | Sony Corp | Dry etching method |
| JPH07201859A (en) * | 1993-12-29 | 1995-08-04 | Sony Corp | Wiring formation method and semiconductor device |
| KR970052340A (en) * | 1995-12-23 | 1997-07-29 | 김주용 | Metal wiring formation method of semiconductor device |
| KR970052431A (en) * | 1995-12-29 | 1997-07-29 | 김주용 | Metal wiring formation method of semiconductor device |
| KR19980031847A (en) * | 1996-10-31 | 1998-07-25 | 김영환 | Metal wiring formation method of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100800819B1 (en) * | 2006-12-27 | 2008-02-01 | 동부일렉트로닉스 주식회사 | Method for providing rework of semiconductor metal pattern |
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