KR20010057734A - Method of forming a copper thin film - Google Patents

Method of forming a copper thin film Download PDF

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KR20010057734A
KR20010057734A KR1019990061129A KR19990061129A KR20010057734A KR 20010057734 A KR20010057734 A KR 20010057734A KR 1019990061129 A KR1019990061129 A KR 1019990061129A KR 19990061129 A KR19990061129 A KR 19990061129A KR 20010057734 A KR20010057734 A KR 20010057734A
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copper
film
forming
substrate
surface catalyst
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KR1019990061129A
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Korean (ko)
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고원용
박형상
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이경수
지니텍 주식회사
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Priority to KR1019990061129A priority Critical patent/KR20010057734A/en
Priority to JP2001545352A priority patent/JP3925780B2/en
Priority to PCT/KR2000/001474 priority patent/WO2001045149A1/en
Priority to DE60041522T priority patent/DE60041522D1/en
Priority to KR10-2002-7007693A priority patent/KR100465982B1/en
Priority to EP00983564A priority patent/EP1247292B1/en
Priority to US09/738,213 priority patent/US6720262B2/en
Publication of KR20010057734A publication Critical patent/KR20010057734A/en
Priority to JP2006336416A priority patent/JP4792379B2/en
Priority to JP2006336417A priority patent/JP2007123924A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN

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  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A method for forming a copper(Cu) film is provided to be capable of forming a continuous Cu film even in a narrow hole or a narrow drain by chemical vapor deposition method using surface catalyst. CONSTITUTION: A method for forming a copper(Cu) film forms an insulating film(120) on a substrate(110). The insulating film(120) is etched to form a hole(A) through which the substrate(110) is exposed. An anti-diffusion film(130) made of TiN or TaN is formed on the resulting surface in which the hole(A) is formed. A surface catalyst containing B or iodine is introduced on the resulting surface in which the anti-diffusion film(130) is formed and (hfac) Cu (vtms) as a chemical vapor deposition material of Cu is supplied to deposit Cu by chemical vapor deposition method, thus forming the first Cu film(140).

Description

구리막 형성방법 {Method of forming a copper thin film}Method of forming a copper thin film

본 발명은 구리막 형성방법에 관한 것으로서, 특히 표면촉매를 이용한 화학증착방법으로 평탄하고 연속적인 구리막을 형성하는 방법에 관한 것이다.The present invention relates to a method for forming a copper film, and more particularly, to a method for forming a flat and continuous copper film by chemical vapor deposition using a surface catalyst.

반도체 소자의 고집적화에 따라 금속배선의 최소 선폭은 계속적으로 축소되고 있으며, 이에 따라, RC 지연에 따른 동작속도의 저하가 문제점으로 대두되고 있다. 따라서, 최근에는 반도체 소자의 고속동작에 대한 요구를 만족시키기 위해 도전율이 높은 구리가 종래의 알루미늄을 대체할 재료로서 사용되기 시작했다.Due to the high integration of semiconductor devices, the minimum line width of metal wiring is continuously reduced, and as a result, a decrease in operating speed due to RC delay has become a problem. Therefore, recently, copper having high conductivity has begun to be used as a material to replace conventional aluminum in order to satisfy the demand for high speed operation of semiconductor devices.

구리는 도전율이 높기 때문에 반도체 소자의 고속화로 인해 도선에 흐르는 전자량이 증대하더라도 이에 따른 내성을 유지할 수 있다는 이점을 가진다. 그러나, 구리는 알루미늄에 비해 식각하기가 어렵고, 또한 고온에서 증착이 이루어지기 때문에 PR 마스크(photoresist mask)를 이용한 선택적 증착이 어려운 난점이 있다. 따라서, 구리배선을 형성시키는 방법으로, 구리배선의 하부에 위치할 절연막에 미리 회로 도선부에 대응하는 도랑(trench)을 형성하고 그곳에 구리를 채워넣는 다마신(damascene) 공정이 적용되고 있다. 또한, 아래층 도선부와의 연결에 필요한 비아홀을 도랑과 함께 형성하고 비아홀과 도랑을 한꺼번에 채우는 이중 다마신 공정(dual damascene)도 적용되고 있다.Since copper has high conductivity, it has the advantage that the resistance can be maintained even if the amount of electrons flowing through the conductive wire increases due to the high speed of the semiconductor device. However, since copper is more difficult to etch than aluminum and is deposited at a high temperature, selective deposition using a PR mask (photoresist mask) is difficult. Therefore, as a method of forming copper wiring, a damascene process is formed in which trenches corresponding to circuit lead portions are formed in advance in an insulating film to be positioned below the copper wiring and filled with copper therein. In addition, a dual damascene process has been applied, in which via holes necessary for connection with the lower conductive parts are formed together with the trenches, and the via holes and the trenches are simultaneously filled.

다마신 또는 이중 다마신 공정의 간단한 일 예를 살펴보면 다음과 같다. 먼저, 절연막에 구멍이나 도랑을 형성한 다음에, 구리와 절연막과의 상호반응을 방지하기 위하여 질화탄탈륨(TaN)으로 이루어진 확산방지막을 형성한다. 이어서, 확산방지막이 형성된 결과물상에 구리 씨앗층을 스퍼터링방법으로 형성한 후에, 구리 씨앗층을 전극으로 사용하여 전기도금방법으로 웨이퍼 전면을 구리막으로 덮는다.A simple example of a damascene or dual damascene process is as follows. First, holes or trenches are formed in the insulating film, and then a diffusion barrier film made of tantalum nitride (TaN) is formed to prevent mutual reaction between copper and the insulating film. Subsequently, after forming the copper seed layer by the sputtering method on the resultant on which the diffusion barrier film is formed, the entire surface of the wafer is covered with the copper film by the electroplating method using the copper seed layer as an electrode.

이와 같은 방법으로 현재 250nm 및 180nm 폭을 가지는 구리배선을 효과적으로 형성하고는 있지만, 앞으로 배선폭이 더욱 작아지면 전기도금의 전극으로 사용하기 위한 구리 씨앗층을 스퍼터링방법으로 형성하는 것은 바람직하지 않게 된다. 왜냐하면, 스퍼터링방법은 직시형(line of sight) 증착특성을 가져서단차도포성(step coverage)이 나쁘기 때문이다. 즉, 스퍼터링방법에 의할 경우에는 큰 종횡비(aspect ratio)를 가지는 구멍이나 트렌치의 내부에 구리 씨앗층이 제대로 형성되지 않기 때문이다. 따라서, 구리 씨앗층을 형성함에 있어서는 단차도포성이 좋은 화학기상증착방법을 이용하는 것이 바람직하다.Although copper wires having 250 nm and 180 nm widths are effectively formed by the above method, it is not preferable to form a copper seed layer for use as an electrode for electroplating by sputtering method when the wire width becomes smaller in the future. This is because the sputtering method has a line of sight deposition characteristic and thus poor step coverage. That is, in the case of the sputtering method, the copper seed layer is not properly formed in the hole or the trench having the large aspect ratio. Therefore, in forming the copper seed layer, it is preferable to use a chemical vapor deposition method having good step coverage.

따라서, 본 발명이 이루고자 하는 기술적 과제는, 대한민국 특허출원 제 98-53575호에 개시된 바 있는 표면촉매를 이용한 화학기상증착방법으로 전기도금의 전극 등으로 쓸 수 있는 평탄하고 연속적인 구리막을 형성하는 방법을 제공하는 데 있다.Accordingly, a technical problem to be achieved by the present invention is a method of forming a flat and continuous copper film which can be used as an electrode of electroplating by chemical vapor deposition using a surface catalyst as disclosed in Korean Patent Application No. 98-53575. To provide.

도 1은 내지 도 4는 본 발명에 따른 구리막 형성방법을 적용하여 전기도금방법으로 구멍에 구리를 채워넣는 방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views for explaining a method of filling copper into a hole by an electroplating method by applying the copper film forming method according to the present invention.

< 도면의 주요 부분에 대한 참조번호의 설명 ><Description of Reference Numbers for Main Parts of Drawings>

110: 기판 120: 절연막110: substrate 120: insulating film

130: 확산방지막 140: 제1 구리막130: diffusion barrier 140: first copper film

150: 제2 구리막150: second copper film

상기 기술적 과제를 달성하기 위한 본 발명의 일 예에 따른 구리막 형성방법은 기판상에 표면촉매를 도입하는 단계와 화학기상증착방법으로 구리를 증착하는 단계를 번갈아가며 2회 이상 반복하여 수행하는 것을 특징으로 한다.Copper film forming method according to an embodiment of the present invention for achieving the above technical problem is to repeat the step of introducing a surface catalyst on a substrate and the step of depositing copper by chemical vapor deposition alternately two or more times It features.

기판표면이 표면촉매가 잘 흡착되지 아니하는 물질로 이루어져 있거나, 또는 표면촉매가 잘 흡착되는 물질로 이루어져 있다 할지라도 공기중에 노출되어 그 표면에 산화막이 형성되어 있다면, 단 한번의 표면촉매 도입만으로는 구리의 화학기상증착반응을 활성화시키기 위한 표면촉매의 양이 충분하지 못할 수 있다. 따라서, 표면촉매의 양이 충분하도록, 상기와 같이 표면촉매의 도입과 구리의 증착을 번갈아 가며 수행한다.If the surface of the substrate is made of a material that is not easily adsorbed by the surface catalyst or is formed of a material that is well adsorbed by the surface catalyst, the surface of the substrate is exposed to the air and an oxide film is formed on the surface thereof. The amount of surface catalyst to activate the chemical vapor deposition reaction may not be sufficient. Therefore, the surface catalyst is alternately introduced and the copper is deposited as described above so that the amount of the surface catalyst is sufficient.

여기서, 상기 표면촉매는 대한민국 특허출원 제98-53575호에 개시된 바 와 같이 증착되는 구리막에 매몰되지 아니하고, 그 막의 표면으로 이동하여 화학기상증착반응을 촉진하는 역할을 한다. 본 발명에서는 상기 표면촉매가 아이오딘 또는 브롬을 함유하는 것이 바람직하다.Here, the surface catalyst is not buried in the copper film deposited as disclosed in Korean Patent Application No. 98-53575, and serves to promote the chemical vapor deposition reaction by moving to the surface of the film. In the present invention, it is preferable that the surface catalyst contains iodine or bromine.

그리고, 상기 표면촉매를 도입하는 단계와 구리를 증착하는 단계 사이에서는 상기 기판이 장입된 반응기를 진공으로 만들거나 비활성 기체로 씻어내는 것이 바람직하다.In addition, between the step of introducing the surface catalyst and the step of depositing copper, it is preferable to make the reactor loaded with the substrate in a vacuum or flush with inert gas.

또한, 구리와 기판사이의 상호반응을 방지하기 위하여 상기 기판상에 질화티타늄(TiN)이나 질화탄탈륨(TaN) 등으로 이루어진 확산방지막을 더 형성한 다음에, 상기 표면촉매를 도입하는 것이 바람직하다.In addition, in order to prevent interaction between copper and the substrate, it is preferable to further form a diffusion barrier film made of titanium nitride (TiN), tantalum nitride (TaN), or the like on the substrate, and then introduce the surface catalyst.

이하에서, 본 발명의 바람직한 실시예를 첨부한 도면들을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

도 1은 내지 도 4는 본 발명에 따른 구리막 형성방법을 적용하여 전기도금방법으로 구멍에 구리를 채워넣는 방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views for explaining a method of filling copper into a hole by an electroplating method by applying the copper film forming method according to the present invention.

도 1은 구멍(A)을 형성하는 단계를 설명하기 위한 단면도로서, 기판(110) 상에 절연막(120)을 형성한 후, 절연막(120)을 식각함으로써 기판(110)을 노출시키는 구멍(A)을 형성한다.1 is a cross-sectional view illustrating a step of forming the hole A. After forming the insulating film 120 on the substrate 110, the hole A exposing the substrate 110 by etching the insulating film 120. ).

도 2는 확산방지막(130)을 형성하는 단계를 설명하기 위한 단면도로서, 구멍(A)이 형성된 결과물 전면에 질화티타늄(TiN)이나 질화탄탈륨(TaN) 등으로 이루어진 확산방지막(130)을 형성한다. 이는 후속되어 형성되는 구리와 기판(110) 및 절연막(120) 사이의 상호반응을 방지하기 위한 것이다.FIG. 2 is a cross-sectional view illustrating a step of forming the diffusion barrier 130, and forms a diffusion barrier 130 formed of titanium nitride (TiN), tantalum nitride (TaN), or the like on the entire surface of the resultant hole A formed therein. . This is to prevent mutual reaction between the subsequently formed copper and the substrate 110 and the insulating film 120.

도 3은 본 발명에 해당하는 공정으로써 제1 구리막(140)을 형성하는 단계를 설명하기 위한 단면도이다. 구체적으로, 확산방지막(130)이 형성된 결과물상에 브롬 또는 아이오딘을 함유하는 표면촉매를 먼저 도입한 후에, 구리의 화학기상증착원료로서 (hfac)Cu(vtms)를 공급하여 화학기상증착방법으로 구리를 증착한다.3 is a cross-sectional view for explaining a step of forming the first copper film 140 as a process corresponding to the present invention. Specifically, a surface catalyst containing bromine or iodine is first introduced onto the resultant on which the diffusion barrier layer 130 is formed, and then (hfac) Cu (vtms) is supplied as a chemical vapor deposition raw material of copper by chemical vapor deposition. Copper is deposited.

표면촉매가 잘 흡착되지 않는 경우를 고려하여, 표면촉매의 양이 충분하도록 상기와 같은 표면촉매의 도입과 구리의 증착을 번갈아 2회 이상 반복함으로써 제1 구리막(140)을 형성한다. 여기서, 표면촉매는 증착되는 구리막에 매몰되지 아니하고, 그 막의 표면으로 계속 이동하여 구리의 화학기상증착반응을 촉진하는 역할을 한다. 그리고, 상기 표면촉매를 도입하는 단계와 구리를 증착하는 단계 사이에서는 상기 기판이 장입된 반응기를 진공으로 만들거나 비활성 기체로 씻어낸다.In consideration of the case where the surface catalyst is hardly adsorbed, the first copper film 140 is formed by repeating the introduction of the surface catalyst and the deposition of copper two or more times so that the amount of the surface catalyst is sufficient. Here, the surface catalyst is not buried in the deposited copper film, and continues to move to the surface of the film to serve to promote chemical vapor deposition of copper. Then, between the step of introducing the surface catalyst and the step of depositing copper, the reactor loaded with the substrate is evacuated or washed with inert gas.

스퍼터링방법으로는 연속적인 구리막을 형성시킬 수 없을 만큼 구멍이나 도랑의 폭이 좁더라도, 표면촉매의 도입과 구리의 화학기상증착을 교번하여 2회 이상 수행하는 본 발명에 의하면, 제1 구리막(140)을 연속적으로 형성시킬 수 있다.According to the present invention in which the introduction of the surface catalyst and the chemical vapor deposition of copper are alternately performed two or more times even if the width of the holes or the trenches is small so that a continuous copper film cannot be formed by the sputtering method, the first copper film ( 140 can be formed continuously.

도 4는 제2 구리막(150)을 형성하는 단계를 설명하기 위한 단면도로서, 제1 구리막(140)을 전극으로 사용하여 전기도금방법으로 제2 구리막(150)을 형성함으로써 구멍을 구리로 채워넣는다.4 is a cross-sectional view for explaining a step of forming the second copper film 150. The hole is formed by forming the second copper film 150 by the electroplating method using the first copper film 140 as an electrode. Fill it with.

상술한 바와 같은 본 발명에 따른 구리막 형성방법에 의하면, 표면촉매의 도입과 구리의 화학기상증착을 교번하여 2회 이상 수행함으로써, 스퍼터링방법으로는 연속적인 구리막을 형성시킬 수 없을 만큼 폭이 좁은 구멍이나 도랑에도, 연속적인 구리막의 형성이 가능하다.According to the method for forming a copper film according to the present invention as described above, by introducing the surface catalyst and chemical vapor deposition of copper alternately two or more times, the sputtering method is narrow enough to form a continuous copper film Continuous formation of a copper film is possible also in a hole and a trench.

따라서, 본 발명에 의해 형성된 구리막을 전기도금의 전극으로 사용하게 되면, 전기도금법으로도 미세한 구멍이나 도랑에 구리를 공극없이 채워넣을 수 있다.Therefore, when the copper film formed by the present invention is used as an electrode for electroplating, it is possible to fill copper into pores or grooves without pores even by the electroplating method.

본 발명은 상기 실시예에만 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

Claims (4)

기판상에 표면촉매를 도입하는 단계와 화학기상증착방법으로 구리를 증착하는 단계를 번갈아가며 2회 이상 반복하여 수행하는 것을 특징으로 하는 구리막 형성방법.A method of forming a copper film, characterized in that the step of introducing a surface catalyst on the substrate and the step of depositing copper by chemical vapor deposition alternately repeated two or more times. 제 1항에 있어서, 상기 표면촉매는 아이오딘 또는 브롬을 함유하는 것을 특징으로 하는 구리막 형성방법.The method of claim 1, wherein the surface catalyst contains iodine or bromine. 제 1항에 있어서, 상기 표면촉매를 도입하는 단계와 구리를 증착하는 단계 사이에 상기 기판이 장입된 반응기를 진공으로 만들거나 비활성 기체로 씻어내는 것을 특징으로 하는 구리막 형성방법.The method according to claim 1, wherein the reactor loaded with the substrate is evacuated or washed with an inert gas between the step of introducing the surface catalyst and the deposition of copper. 제 1항에 있어서, 상기 표면촉매를 도입하는 단계는 상기 기판상에 확산방지막을 더 형성한 후에 행해지는 것을 특징으로 하는 구리막 형성방법.The method of claim 1, wherein the introducing of the surface catalyst is performed after further forming a diffusion barrier film on the substrate.
KR1019990061129A 1999-12-15 1999-12-23 Method of forming a copper thin film KR20010057734A (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
KR1019990061129A KR20010057734A (en) 1999-12-23 1999-12-23 Method of forming a copper thin film
JP2001545352A JP3925780B2 (en) 1999-12-15 2000-12-15 Method for forming copper wiring and thin film using catalyst and chemical vapor deposition
PCT/KR2000/001474 WO2001045149A1 (en) 1999-12-15 2000-12-15 Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst
DE60041522T DE60041522D1 (en) 1999-12-15 2000-12-15 METHOD FOR PRODUCING COPPER INTERCONNECTIONS AND THIN FILMS BY CVD AND A CATALYST
KR10-2002-7007693A KR100465982B1 (en) 1999-12-15 2000-12-15 Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst
EP00983564A EP1247292B1 (en) 1999-12-15 2000-12-15 Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst
US09/738,213 US6720262B2 (en) 1999-12-15 2000-12-15 Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst
JP2006336416A JP4792379B2 (en) 1999-12-15 2006-12-13 Method for forming copper wiring and thin film using catalyst and chemical vapor deposition
JP2006336417A JP2007123924A (en) 1999-12-15 2006-12-13 Method of forming copper interconnection and thin film using catalyst and chemical vapor deposition method

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