KR20010028986A - method for manufacturing via contact in semiconductor device - Google Patents
method for manufacturing via contact in semiconductor device Download PDFInfo
- Publication number
- KR20010028986A KR20010028986A KR1019990041548A KR19990041548A KR20010028986A KR 20010028986 A KR20010028986 A KR 20010028986A KR 1019990041548 A KR1019990041548 A KR 1019990041548A KR 19990041548 A KR19990041548 A KR 19990041548A KR 20010028986 A KR20010028986 A KR 20010028986A
- Authority
- KR
- South Korea
- Prior art keywords
- via contact
- etching
- semiconductor device
- film
- interlayer insulating
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 보다 상세하게는 반도체 장치의 비아 콘택 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a via contact of a semiconductor device.
반도체 장치가 고집적화 및 고속화됨에 따라, 미세 패턴의 형성이 요구되고 있으며 배선의 폭(width) 뿐만 아니라 배선과 배선 사이의 간격(space)도 현저하게 감소하고 있다. 특히, 반도체 기판 내에 형성되어 있는 고립된 활성 영역들을 고전도성 박막을 사용하여 연결시키는 콘택은 얼라인 마진(align margin), 소자분리 마진(isolation margin) 등을 확보하면서 이루어져야 하므로, 소자의 구성에 있어서 상당한 면적을 차지하게 된다. 따라서, 다이내믹 랜덤 억세스 메모리(dynamic random access memory; DRAM)이나 스태틱 랜덤 억세스 메모리(static random access memory; SRAM)과 같은 메모리 소자에 있어서 이러한 콘택은 메모리 셀의 면적을 결정하는 주요 요인으로 작용한다.As semiconductor devices become more integrated and faster, formation of fine patterns is required, and not only the width of the wiring but also the space between the wiring and the wiring is significantly reduced. In particular, the contact connecting the isolated active regions formed in the semiconductor substrate by using a highly conductive thin film should be made while securing an alignment margin, an isolation margin, and the like. It will occupy a considerable area. Thus, in memory devices such as dynamic random access memory (DRAM) or static random access memory (SRAM), these contacts serve as a major factor in determining the area of memory cells.
도 1은 종래 방법에 따라 비아 콘택이 형성되어 있는 반도체 장치의 단면도이다.1 is a cross-sectional view of a semiconductor device in which a via contact is formed according to a conventional method.
도면을 참조하면, 층간절연막(10)의 소정영역에 하부배선인 알루미늄 배선(12)이 형성되어 있으며, 상기 알루미늄 배선(12) 상부에는 FOx(Flowable Oxide;14)막이 형성되어 있다. 상기 알루미늄 배선(12) 및 FOx(14) 형성되어 있는 층간절연막(10)의 상부에 TEOS(Tetra-Ethyl-Ortho-Silicate;16)가 형성되어 있으며, 상기 TEOS(16)의 소정영역에는 상기 알루미늄 배선(12)에 이르는 비아 콘택이 형성되어 있다.Referring to the drawings, an aluminum wiring 12 as a lower wiring is formed in a predetermined region of the interlayer insulating film 10, and a FOx (Flowable Oxide) film 14 is formed on the aluminum wiring 12. TEOS (Tetra-Ethyl-Ortho-Silicate) 16 is formed on the interlayer insulating film 10 on which the aluminum wiring 12 and the FOx 14 are formed, and the aluminum is formed in a predetermined region of the TEOS 16. Via contacts leading to the wiring 12 are formed.
상기한 바와 같이, 종래에는 층간절연막으로서 유전특성이 우수한 FOx(14)을 알루미늄(12) 상부에 형성하였으며, 이러한 FOx(14)를 식각하기 위한 식각에천트로서는 C4F8/Ar/O2를 사용하였다. 그러나, FOx(14)는 유전특성이 우수한 장점이 있는 반면 다공질이므로 식각이 진행되는 과정에서 보잉(bowing) 프로파일 및 스타핑(stopping) 프로파일이 발생되고, 상기 C4F8/Ar/O2로 이루어진 식각에천트는 상기 FOx(14)에 대한 식각속도가 느려 전체 공정이 길어지는 단점이 있었다.As described above, FOx 14 having excellent dielectric properties was formed on the aluminum 12 as an interlayer insulating film. C4F8 / Ar / O2 was used as an etching etchant for etching the FOx 14. However, since FOx 14 is porous and has excellent dielectric properties, a bowing profile and a stopping profile are generated during the etching process, and the etch cloth made of C4F8 / Ar / O2 is used. There is a disadvantage that the entire process is long because the etching rate for the FOx (14) is slow.
이러한 단점을 보완하기 위한 새로운 식각에천트로서, 탄소와 불소의 비율이 낮은 CF4/CO 가스에 CHF3 가스를 혼합하여 사용하였다. 이처럼 CF4/CO/CHF3로 이루어진 혼합가스를 식각에천트로 사용함에 따라 FOx(14)에 대한 식각속도를 높이고 보잉 프로파일 및 스타핑 프로파일이 발생되는 문제점은 해소하였다. 그러나, 상기 알루미늄(12) 상부에 캡핑막으로 기능하는 티타늄나이트라이드(TiN)와 티타늄(Ti)에 대한 식각선택비가 낮아 VEST(Via Etch Stop on TiN) 프로파일을 구현하지 못하고 도 1에 도시되어 있는 것과 같이, VESA(Via Etch Stop on Al) 프로파일을 구현하게 되었다. 이러한 VESA 프로파일은 식각이 하부배선인 알루미늄(12)에까지 진행되므로 하부배선으로서 기능하는 알루미늄의 손상되는 문제점이 있다.As a new etching etchant to compensate for this disadvantage, CHF3 gas was mixed with CF4 / CO gas having a low ratio of carbon and fluorine. As such, by using the mixed gas composed of CF 4 / CO / CHF 3 as an etching etchant, the problem of increasing the etching rate for the FOx 14 and generating a boeing profile and a stepping profile is solved. However, the etching selectivity for titanium nitride (TiN) and titanium (Ti), which functions as a capping layer on the aluminum 12, is low, thereby failing to implement a VEST (Via Etch Stop on TiN) profile. As such, we have implemented a Via Etch Stop on Al (VESA) profile. The VESA profile has a problem that the etching proceeds to the lower wiring aluminum 12, so that the aluminum functioning as the lower wiring is damaged.
한편, 씨피유 제품 및 MDL(Merged Dram Logic) 디바이스의 디자인룰이 감소하면서 비아 콘택과의 오버랩되는 메탈 패턴의 피치의 감소에 따라 오버랩 마진도 감소하여 250nm이하의 콘택에서는 오버랩 마진이 제로(zero)가 된다. 비아 콘택의 사이즈가 400nm 이상인 경우에는 약 50% 정도 미스 얼라인이 발생하여도 비아 콘택 저항에는 크게 영향을 미치지 않지만, 약 250nm 이하의 미세한 비아 콘택을 형성하고자 하는 경우 미스 얼라인이 발생하면 콘택홀 내부에 텅스텐이 충진되지 않거나 메탈 측벽의 절연막이 에칭되는 등의 페일을 가져오게 된다. 그러므로, 상기와 같은 CF4/CO/CHF3를 식각에천트로서 이용하여 VESA 프로파일을 적용할 경우, 이러한 문제점이 더욱 심화되어 반도체 장치의 신뢰성을 더욱 저하시키게 된다.On the other hand, as the design rules of CPI products and MDL (Merged Dram Logic) devices decrease, the overlap margin also decreases as the pitch of the metal pattern overlapping with the via contact decreases, resulting in a zero overlap margin for contacts below 250 nm. do. When the via contact size is 400 nm or more, about 50% of misalignment does not significantly affect the via contact resistance.However, in the case of forming a fine via contact of about 250 nm or less, when a misalignment occurs, a contact hole occurs. This results in a failure such that tungsten is not filled inside or the insulating film on the metal sidewall is etched. Therefore, when the VESA profile is applied using the above CF4 / CO / CHF3 as an etching etchant, this problem is further exacerbated, which further lowers the reliability of the semiconductor device.
따라서, 본 발명의 목적은, 상기한 종래의 문제점을 해소하기 위한 반도체 장치의 비아 콘택 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a via contact of a semiconductor device for solving the above-mentioned conventional problems.
본 발명의 다른 목적은, 비아 콘택의 페일을 유발시키지 않는 반도체 장치의 비아 콘택 제조방법을 제공함에 있다.Another object of the present invention is to provide a method for manufacturing a via contact of a semiconductor device that does not cause a fail of the via contact.
상기 목적들을 달성하기 위해서 본 발명에서는, 반도체 장치의 비아 콘택 제조방법에 있어서: 캡핑막을 구비한 하부도전막 상부에 유전특성이 우수한 층간절연막을 형성하는 단계와; 상기 층간절연막에 대한 식각속도가 높은 식각에천트를 이용하여 상기 층간절연막의 소정영역에 비아 콘택용 비아 콘택홀을 형성하는 단계와; 상기 비아 콘택홀에 도전물을 충진하는 단계를 포함함을 특징으로 하는 반도체 장치의 비아 콘택 제조방법을 제공한다.SUMMARY OF THE INVENTION In order to achieve the above objects, the present invention provides a method of manufacturing a via contact in a semiconductor device, comprising the steps of: forming an interlayer insulating film having excellent dielectric properties on a lower conductive film having a capping film; Forming a via contact hole for a via contact in a predetermined region of the interlayer insulating layer by using an etching etchant having a high etching rate with respect to the interlayer insulating layer; A method of manufacturing a via contact in a semiconductor device, the method comprising filling a via contact hole with a conductive material.
바람직하게는, 상기 캡핑막은 티타늄과 티타늄나이트라이드로 이루어진 혼합막으로 형성한다.Preferably, the capping film is formed of a mixed film made of titanium and titanium nitride.
바람직하게는, 상기 식각에천트로서는 C4F8/Ar/O2/N2로 이루어진 혼합 가스를 이용한다.Preferably, a mixed gas composed of C 4 F 8 / Ar / O 2 / N 2 is used as the etching etchant.
또한, 바람직하게는, 상기 층간절연막의 식각공정은 약 20∼150mT의 압력과 약 1000∼1500W의 RF 전력하, 그리고 약 40∼80 ℃의 전극 온도하에서 실시한다.Preferably, the etching process of the interlayer insulating film is performed under a pressure of about 20 to 150 mT, an RF power of about 1000 to 1500 W, and an electrode temperature of about 40 to 80 ° C.
도 1은 종래 방법에 따라 비아 콘택이 형성되어 있는 반도체 장치의 단면도이다.1 is a cross-sectional view of a semiconductor device in which a via contact is formed according to a conventional method.
도 2 내지 도 5는 본 발명의 바람직한 실시예에 따른 VEST 프로파일의 비아 콘택 제조방법을 설명하기 위한 단면도들이다.2 to 5 are cross-sectional views illustrating a method for manufacturing a via contact of a VEST profile according to a preferred embodiment of the present invention.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2 내지 도 5는 본 발명의 바람직한 실시예에 따른 VEST 프로파일의 비아 콘택 제조방법을 설명하기 위한 단면도들이다.2 to 5 are cross-sectional views illustrating a method for manufacturing a via contact of a VEST profile according to a preferred embodiment of the present invention.
먼저, 도 2를 참조하면, 하부배선인 알루미늄(100)층 상부에 후속의 공정을 통해 형성되어질 물질막과 알루미늄(100)층의 접착력을 강화시키고 여러 가지 단위 공정으로부터 알루미늄(100)층을 보호하는 티타늄나이트라이드(TiN)와 티타늄(Ti)으로 이루어진 캡핑막(102)을 형성한다. 그리고 나서, 상기 캡핑막(102) 상부에 제1층간절연막으로서 FOx(104) 및 제2층간절연막으로서 TEOS(106)을 차례로 형성한다. 상기 TEOS(106) 상부에 감광막(108)을 형성한 뒤, 이를 노광 및 현상하여 약 0.20㎛의 개구(110)를 형성한다.First, referring to FIG. 2, the adhesion between the material layer and the aluminum 100 layer to be formed through a subsequent process on the upper portion of the aluminum 100 layer, which is the lower wiring, is protected, and the aluminum 100 layer is protected from various unit processes. The capping film 102 made of titanium nitride (TiN) and titanium (Ti) is formed. Then, the FOx 104 as a first interlayer insulating film and the TEOS 106 as a second interlayer insulating film are sequentially formed on the capping film 102. After the photoresist layer 108 is formed on the TEOS 106, the photoresist layer 108 is exposed and developed to form an opening 110 having a thickness of about 0.20 μm.
도 3을 참조하면, 상기 개구(110)가 형성되어 있는 감광막(108) 패턴을 자기정렬된 식각마스크로서 이용하여 상기 TEOS(106) 및 FOx(104)을 식각한다. 그 결과, 상기 TEOS(106) 및 FOx(104)를 관통하여 캡핑막(102)에 이르는 비아 콘택 형성을 위한 비아 콘택홀(112)이 형성된다.Referring to FIG. 3, the TEOS 106 and the FOx 104 are etched using the photoresist layer 108 having the opening 110 as a self-aligned etching mask. As a result, via contact holes 112 are formed through the TEOS 106 and the FOx 104 to form via contacts reaching the capping layer 102.
본 발명에서는 상기 TEOS(106) 및 FOx(104)을 식각하기 위한 에천트로서 종래의 CF4/CO/CHF3 가스 대신 C4F8/Ar/O2/N2로 이루어진 혼합가스를 이용한다. 이러한 C4F8/Ar/O2/N2 혼합가스를 식각에천트로서 사용하여 비아 콘택홀(112)을 형성할 경우, 비아 콘택홀(112)의 측벽에 폴리머를 발생시켜 패시베이션 효과를 일으켜 다공질의 FOx(104)에 발생되는 보잉 프로파일을 개선할 수 있는 장점이 있다. 또한, 상기 TEOS(106) 및 FOx(104)에 대한 상기 티타늄나이트라이드/티타늄으로 이루어진 캡핑막(102)의 식각선택비를 높이기 위해 탄소와 불소의 비율이 높은 가스를 식각에천트로서 사용함에 의해 스타핑 프로파일이 나타나는데, 본 발명에서와 같이 C4F8/Ar/O2 가스에 N2 가스를 혼합하여 사용함으로써, 이러한 문제점은 충분히 해소될 수 있다.In the present invention, a mixed gas made of C4F8 / Ar / O2 / N2 is used as an etchant for etching the TEOS 106 and the FOx 104 instead of the conventional CF4 / CO / CHF3 gas. When the via contact hole 112 is formed using the C4F8 / Ar / O2 / N2 mixed gas as an etching etchant, a polymer is generated on the sidewall of the via contact hole 112 to cause a passivation effect, thereby forming a porous FOx (104). ), There is an advantage to improve the boeing profile generated. Further, in order to increase the etching selectivity of the capping film 102 made of titanium nitride / titanium with respect to the TEOS 106 and the FOx 104, a gas having a high ratio of carbon and fluorine is used as an etching etchant. A staring profile appears, and this problem can be sufficiently solved by mixing N2 gas with C4F8 / Ar / O2 gas as in the present invention.
여기서, 상기 TEOS(106) 및 FOx(104) 식각은 MERIE 타입의 식각장비를 이용하여 약 20∼150mT의 압력과 약 1000∼1500W의 RF 전력하에서 실시하며, 웨이퍼가 놓여지는 전극의 온도는 약 40∼80℃로 유지하는 것이 바람직하다.The etching of the TEOS 106 and the FOx 104 is performed using a MERIE type etching equipment under a pressure of about 20 to 150 mT and an RF power of about 1000 to 1500 W, and the temperature of the electrode on which the wafer is placed is about 40. It is preferable to maintain at -80 degreeC.
도 4를 참조하면, 에싱 및 스트립 공정을 실시하여 상기 감광막(108) 패턴을 완전히 제거한다.Referring to FIG. 4, an ashing and strip process is performed to completely remove the photoresist layer 108 pattern.
도 5를 참조하면, 후속의 공정으로부터 상기 비아 콘택(114)을 보호하기 위한 티타늄나이트라이드(114)를 형성한 뒤, 상기 비아 콘택홀(112) 내부에 도전물을 충진하여 약 0.20㎛의 면적을 가지는 비아 콘택(116)을 형성한다. 그리고 나서, 상기 비아 콘택(116)이 형성되어 있는 결과물의 상부에 예컨대, 알루미늄등의 금속물을 이용하여 상부도전막(118)을 형성한다.Referring to FIG. 5, after forming a titanium nitride 114 to protect the via contact 114 from a subsequent process, an area of about 0.20 μm is filled by filling a conductive material in the via contact hole 112. A via contact 116 is formed. Then, the upper conductive layer 118 is formed on the resultant in which the via contact 116 is formed using, for example, metal such as aluminum.
상술한 바와 같이, 본 발명의 바람직한 실시예를 참조하여 설명하였지만 해당 기술 분야의 숙련된 당업자라면 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.
상술한 바와 같이 본 발명에서는, 티타늄/티타늄나이트라이드로 이루어진 캡핑층을 구비한 알루미늄 배선 상부에 형성되어 있는 TEOS 및 FOx을 식각하여 비아 콘택홀을 형성함에 있어서, C4F8/Ar/O2/N2로 이루어진 혼합가스를 식각에천트로 이용한다. 그 결과, 전체적인 식각속도가 향상되고 FOx에서 발생되던 보잉 프로파일 및 스타핑 프로파일 문제를 해소할 수 있다.As described above, in the present invention, in forming the via contact hole by etching TEOS and FOx formed on the aluminum wiring having the capping layer made of titanium / titanium nitride, C 4 F 8 / Ar / O 2 A mixed gas consisting of / N 2 is used as an etchant. As a result, the overall etching rate is improved and the problem of the bowing profile and the stepping profile generated in the FOx can be solved.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990041548A KR20010028986A (en) | 1999-09-28 | 1999-09-28 | method for manufacturing via contact in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990041548A KR20010028986A (en) | 1999-09-28 | 1999-09-28 | method for manufacturing via contact in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010028986A true KR20010028986A (en) | 2001-04-06 |
Family
ID=19613060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990041548A KR20010028986A (en) | 1999-09-28 | 1999-09-28 | method for manufacturing via contact in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010028986A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720401B1 (en) * | 2001-06-01 | 2007-05-22 | 매그나칩 반도체 유한회사 | Method for Forming Cu lines in Semiconductor Device |
-
1999
- 1999-09-28 KR KR1019990041548A patent/KR20010028986A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720401B1 (en) * | 2001-06-01 | 2007-05-22 | 매그나칩 반도체 유한회사 | Method for Forming Cu lines in Semiconductor Device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6881659B2 (en) | Methods of forming self-aligned contact structures in semiconductor integrated circuit devices | |
| US5854119A (en) | Robust method of forming a cylinder capacitor for DRAM circuits | |
| US6461977B1 (en) | Method of manufacturing semiconductor device | |
| US6080662A (en) | Method for forming multi-level contacts using a H-containing fluorocarbon chemistry | |
| KR20010063765A (en) | Fabricating method for semiconductor device | |
| US6225203B1 (en) | PE-SiN spacer profile for C2 SAC isolation window | |
| KR100334572B1 (en) | Method of forming a self aligned contact in a semiconductor device | |
| KR950000519B1 (en) | Manufacturing method of self align contact using poly-silicon layer | |
| KR20010028986A (en) | method for manufacturing via contact in semiconductor device | |
| KR100366634B1 (en) | Method for manufacturing semiconductor device | |
| KR100376986B1 (en) | Manufacturing method for semiconductor device | |
| KR100382730B1 (en) | Metal contact structure in semiconductor device and forming method thereof | |
| KR100576083B1 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| KR100469914B1 (en) | A method for forming a semiconductor device | |
| KR20030041550A (en) | Method for fabricating semiconductor device | |
| JPH11251553A (en) | Contact forming method of semiconductor storage device and its structure | |
| KR100532954B1 (en) | Method for forming contact of semiconductor device | |
| KR100429008B1 (en) | Method of forming contact hole of semiconductor device | |
| KR19990001921A (en) | Metal contact hole formation method of semiconductor device | |
| KR100427035B1 (en) | Method for fabricating semiconductor device with improved protection capability of fail in self align contact | |
| KR100402935B1 (en) | Method for manufacturing semiconductor device | |
| KR19980083674A (en) | Microcontact and charge storage electrode formation method of semiconductor device | |
| KR100191779B1 (en) | Semiconductor device and its fabrication method | |
| KR20020030567A (en) | Method for fabricating semiconductor device using self-aligned contact process | |
| KR100546275B1 (en) | Method for etching Pt layer of semicondutcor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |