KR20010026987A - Method for forming gate oxide layer of semiconductor device - Google Patents

Method for forming gate oxide layer of semiconductor device Download PDF

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Publication number
KR20010026987A
KR20010026987A KR1019990038530A KR19990038530A KR20010026987A KR 20010026987 A KR20010026987 A KR 20010026987A KR 1019990038530 A KR1019990038530 A KR 1019990038530A KR 19990038530 A KR19990038530 A KR 19990038530A KR 20010026987 A KR20010026987 A KR 20010026987A
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South Korea
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oxide film
oxide layer
forming
semiconductor device
gate
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KR1019990038530A
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Korean (ko)
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이금범
박성훈
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박종섭
현대전자산업 주식회사
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Publication of KR20010026987A publication Critical patent/KR20010026987A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: A method for fabricating a gate oxide layer of a semiconductor device is provided to eliminate a defect in a semiconductor substrate itself by growing a chemical oxide layer after the chemical oxide layer is formed by using NH4OH, and to decrease a threshold voltage of a gate by reducing a gate oxide layer in thickness. CONSTITUTION: An isolating process is performed to form a field oxide layer in a field region on a semiconductor substrate(20). A sacrificial oxide layer is formed on the entire structure having the field oxide layer. A cleaning process using high-temperature cleaning liquid is performed regarding a wafer having the sacrificial layer to form a chemical oxide layer(21). An upper portion of the structure having the chemical oxide layer is annealed in a high temperature gas atmosphere. An oxynitride layer(22) is formed on the entire structure having the chemical oxide layer.

Description

반도체소자의 게이트산화막 형성방법{Method for forming gate oxide layer of semiconductor device}Method for forming gate oxide layer of semiconductor device

본 발명은 반도체소자의 게이트산화막 형성방법에 관한 것으로, 특히 과수비율이 높고 고온인 NH4OH를 적용하여 캐미컬산화막을 형성한 후, 그 캐미컬산화막을 버퍼로 이용하여 질화산화막을 성장시킴으로써 반도체기판 자체내의 결함을 제거하고 아울러 게이트산화막의 두께를 낮추어 게이트의 문턱전압을 낮출 수 있도록 한 반도체소자의 게이트산화막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate oxide film of a semiconductor device. In particular, a chemical oxide film is formed by applying NH 4 OH having a high overratio and high temperature, and then the nitride oxide film is grown using the chemical oxide film as a buffer. The present invention relates to a method for forming a gate oxide film of a semiconductor device which eliminates defects in the substrate itself and lowers a gate voltage by reducing a thickness of the gate oxide film.

일반적으로 반도체소자에 있어서 MOS트랜지스터의 게이트를 형성하는 공정에 있어서, 반도체기판과 게이트전극간의 절연을 위한 절연막을 형성하게 되는데, 이 절연막은 반도체소자의 동작시 전기적으로 중요한 역할을 하게 된다. 이러한 절연막으로는 예를 들어 게이트산화막이 사용될 수 있다.In general, in the process of forming a gate of a MOS transistor in a semiconductor device, an insulating film for insulating between the semiconductor substrate and the gate electrode is formed, which plays an important role in the operation of the semiconductor device. For example, a gate oxide film may be used as the insulating film.

도 1a 내지 도 1g는 종래의 반도체소자의 게이트산화막을 형성하는 방법을 보인 단면도들이다.1A to 1G are cross-sectional views illustrating a method of forming a gate oxide film of a conventional semiconductor device.

먼저 도 1a 내지 도 1e에 도시된 바와 같은 ISO공정을 실시하여 필드산화막(15)을 형성한다.First, an ISO process as shown in FIGS. 1A to 1E is performed to form a field oxide film 15.

즉, 도 1a에 도시된 바와 같이, 반도체기판(10) 위에 패드산화막(11)을 50Å 내지 100Å의 두께로 증착한 후 질화막(12)을 900Å 내지 2000Å 정도의 두께로 증착한다. 여기서, 패드산화막(11)은 질화막(12)과 반도체기판(10)의 열팽창 계수차이로 인하여 반도체기판(10) 표면에 가해지는 응력(stress)을 완화시키기 위하여 형성하는 것이고, 질화막(12)은 ISO공정에서 필드산화막(15)에 대한 마스크역할을 하게 된다.That is, as illustrated in FIG. 1A, the pad oxide film 11 is deposited on the semiconductor substrate 10 to a thickness of 50 kPa to 100 kPa, and the nitride film 12 is deposited to a thickness of about 900 kPa to 2000 kPa. Here, the pad oxide film 11 is formed to relieve stress applied to the surface of the semiconductor substrate 10 due to the difference in thermal expansion coefficient between the nitride film 12 and the semiconductor substrate 10. It serves as a mask for the field oxide film 15 in the ISO process.

그 다음, 도 1b에 도시된 바와 같이, 상기 질화막(12) 위에 포토레지스터(13)를 도포한 후 패터닝하여 활성영역과 필드영역으로 나누어지도록 한다. 어어서, 도 1c 및 도 1d와 같이, 도 1b의 구조전면에 스페이서질화막(14)을 증착한 후 플랭킷(blancket) 에칭하여 측벽스페이서(14a)를 형성한다.Next, as shown in FIG. 1B, the photoresist 13 is coated on the nitride film 12, and then patterned to divide the photoresist 13 into an active region and a field region. For example, as shown in FIGS. 1C and 1D, the spacer nitride film 14 is deposited on the entire surface of FIG. 1B and then blanket etched to form sidewall spacers 14a.

그 다음, 도 1d의 구조를 갖는 웨이퍼를 퍼니스(furnace)에 넣어 질화막(12)이 에칭된 필드영역에 두꺼운 산화막이 성장되도록 한 후, 인산용액을 이용하여 질화막(12) 및 패드산화막(11)을 제거한다. 그 결과, 도 1e에 도시된 바와 같은 필드산화막(15)의 형성이 완료되어 소자분리가 이루어진다.Then, a wafer having the structure of FIG. 1D is placed in a furnace so that a thick oxide film is grown in a field region where the nitride film 12 is etched, and then the nitride film 12 and the pad oxide film 11 are formed using a phosphoric acid solution. Remove it. As a result, formation of the field oxide film 15 as shown in FIG. 1E is completed, and device isolation is performed.

상기와 같은 ISO공정을 수행한 다음, 도 1f에 도시된 바와 같이, 도 1e의 구조 전면에 희생산화막(16)을 증착한다. 여기서, 희생산화막(16)은 상기 질화막(12)의 잔여물에 의하여 발생되는 화이트 리본(white ribbon)을 제거하고 웨이퍼의 표면을 보호하기 위하여 증착한 것이다. 그 후, 상온에서 NH4OH을 이용한 세정공정을 실시하여 희생산화막(16)을 제거한다.After performing the above ISO process, as shown in FIG. 1F, a sacrificial oxide film 16 is deposited on the entire structure of FIG. 1E. Here, the sacrificial oxide film 16 is deposited to remove the white ribbon generated by the residue of the nitride film 12 and to protect the surface of the wafer. Thereafter, the sacrificial oxide film 16 is removed by performing a washing process using NH 4 OH at room temperature.

그 다음, 도 1g에 도시된 바와 같이, 열(thermal) 산화에 의하여 게이트산화막(17)을 증착함으로써, 게이트산화막의 형성이 완료된다.Then, as shown in Fig. 1G, by depositing the gate oxide film 17 by thermal oxidation, the formation of the gate oxide film is completed.

그러나, 상기와 같은 종래의 게이트산화막 형성방법에 있어서는, 게이트산화막(17)이 형성되기 전의 공정들을 거치는 동안 반도체기판(10) 자체내의 결함들이 반도체기판(10)의 상부로 확산되는데, 이러한 결함들은 소자특성을 저하시키는 요인이 된다. 또한, 종래에는 게이트산화막(17)의 형성전에 NH4OH를 이용한 세정공정을 상온에서 실시하기 때문에, 반도체기판(10)의 상부로 확산되는 상기 결함들을 제거할 수 없었고 반도체기판(10)의 표면에 존재하는 금속성 불순물을 제거하는 효과가 감소하는 단점이 있었다. 또한, 종래에는 열 산화에 의하여 게이트산화막(17)을 성장시키기 때문에 소자축소시에 게이트산화막(17)의 두께가 감소하고 이에 따라 절연특성이 악화되는 단점이 있었다.However, in the conventional method of forming a gate oxide film as described above, defects in the semiconductor substrate 10 itself diffuse into the upper portion of the semiconductor substrate 10 during the processes before the gate oxide film 17 is formed. It becomes a factor which reduces a device characteristic. In addition, conventionally, since the cleaning process using NH 4 OH is performed at room temperature before the gate oxide film 17 is formed, the defects diffused to the upper portion of the semiconductor substrate 10 cannot be removed and the surface of the semiconductor substrate 10 can be removed. There was a disadvantage in that the effect of removing the metallic impurities present in the decrease. In addition, in the related art, since the gate oxide film 17 is grown by thermal oxidation, the thickness of the gate oxide film 17 is reduced during device reduction, and thus, the insulating property is deteriorated.

따라서, 본 발명은 이와 같은 문제점을 해결하기 위해 안출한 것으로서, 과수비율이 높고 고온인 NH4OH를 적용하여 캐미컬산화막을 형성한 후 그 캐미컬산화막을 버퍼로 이용하여 질화산화막을 성장시킴으로써, 반도체기판 자체내의 결함을 제거하고 아울러 게이트산화막의 두께를 낮추어 게이트의 문턱전압을 낮출 수 있도록 한 반도체소자의 게이트산화막 형성방법을 제공하는 데 그 목적이 있다.Accordingly, the present invention has been made to solve such a problem, by forming a chemical oxide film by applying a high NH 4 OH and a high fruit ratio, and by growing the nitride oxide film using the chemical oxide film as a buffer, It is an object of the present invention to provide a method for forming a gate oxide film of a semiconductor device in which a defect in the semiconductor substrate itself is eliminated and the thickness of the gate oxide film is reduced to lower the threshold voltage of the gate.

도 1a 내지 도 1e는 종래의 반도체소자의 게이트산화막 형성방법을 설명하기 위한 단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a gate oxide film of a conventional semiconductor device.

도 2a 및 도 2b는 본 발명에 따른 반도체소자의 게이트산화막 형성방법을 설명하기 위한 단면도이다.2A and 2B are cross-sectional views illustrating a method for forming a gate oxide film of a semiconductor device according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10,20:반도체기판 11:패드산화막10,20: semiconductor substrate 11: pad oxide film

12:질화막 13:포토레지스터12: nitride film 13: photoresist

14:스페이스질화막 14a:측벽스페이서14: space nitride film 14a: side wall spacer

15,21:필드산화막 16:희생산화막15, 21: field oxide film 16: rare production film

17:게이트산화막 22:캐미컬(chemical)산화막17: gate oxide film 22: chemical oxide film

22:질화산화막(oxynitride)막22: oxynitride film

이와 같은 목적을 달성하기 위한 본 발명은 소자분리를 위한 아이솔레이션 공정을 실시하여 반도체기판상의 필드영역에 필드산화막을 형성하는 단계; 상기 필드산화막이 형성된 구조 전면에 희생산화막을 형성하는 단계; 상기 희생산화막이 형성된 웨이퍼에 대하여 고온의 세정용액을 이용한 세정을 실시하여 캐미컬산화막을 형성하는 단계; 상기 캐미컬산화막이 형성된 구조의 상부에 대하여 고온의 가스분위기에서 어닐링을 실시하는 단계; 및 상기 캐미컬산화막이 형성된 구조의 전면에 질화산화막을 형성하는 단계;를 포함하여 구성되는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming a field oxide film in the field region on the semiconductor substrate by performing an isolation process for device isolation; Forming a sacrificial oxide film over the entire structure of the field oxide film; Performing a cleaning using a high temperature cleaning solution on the wafer on which the sacrificial oxide film is formed to form a chemical oxide film; Annealing the upper portion of the structure in which the chemical oxide film is formed in a hot gas atmosphere; And forming a nitride oxide film on the entire surface of the structure in which the chemical oxide film is formed.

이하, 본 발명의 바람직한 실시예를 첨부 도면을 참조하여 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

먼저, 도 1 내지 도 1e에 도시된 바와 같이 종래와 동일한 공정을 실시하여, 반도체기판(20) 위에 필드산화막(21)을 2000Å 내지 3500Å 정도의 두께로 형성한다. 그 다음, 종래와 같이 희생산화막(미도시)을 성장시켜 화이트리본을 제거한다.First, as shown in FIGS. 1 to 1E, the same process as in the related art is performed to form a field oxide film 21 on the semiconductor substrate 20 in a thickness of about 2000 to 3500 Å. Then, the white ribbon is removed by growing a sacrificial oxide film (not shown) as in the related art.

이어서, 80℃ 이상의 고온의 NH4OH를 사용하는 세정공정을 실시하여 상기 희생산화막을 제거하는데, 이때 세정용액은 NH4OH, H2O2, H2O로 구성되고 그 조성비율은 4:6:1로 유지된다. 이와 같은 세정공정에서는 NH4OH의 과수비율을 높게 조정함으로써, 후술하는 캐미컬산화막(22)의 성장이 용이하도록 한다.Subsequently, to conduct a cleaning process using a 80 ℃ the above high-temperature NH 4 OH to remove the sacrificial oxide layer, wherein the cleaning solution is composed of NH 4 OH, H 2 O 2, H 2 O the composition is 4: Retained at 6: 1. In such a washing process, by adjusting the ratio of NH 4 OH to high, the growth of the chemical oxide film 22 described later is facilitated.

이러한 고온의 NH4OH를 사용하는 세정공정을 20 내지 30분간 유지함으로써, 반도체기판(20)의 표면에 존재하는 불순물을 제거하여 그 불순물들이 확산되는 것을 방지할 수 있고, H2O2에 의하여는 캐미컬산화막(22)이 성정하게 된다. 이에 따라, 도 2a에 도시된 바와 같이, 필드산화막(21)이 형성된 구조의 전면에 캐미컬산화막(22)이 20Å 내지 30Å 두께로 형성된다.By maintaining the cleaning process using such a high temperature NH 4 OH for 20 to 30 minutes, it is possible to remove impurities present on the surface of the semiconductor substrate 20 to prevent the impurities from being diffused, by the H 2 O 2 The chemical oxide film 22 is established. Accordingly, as shown in FIG. 2A, the chemical oxide film 22 is formed to have a thickness of 20 kPa to 30 kPa on the entire surface of the structure in which the field oxide film 21 is formed.

또한, 고온의 NH4OH를 이용함으로써 반도체기판(20)에 대한 식각율을 높여 세정공정시 반도체기판(20)을 10Å정도 식각함으로써 반도체기판(20) 자체의 결함을 10E1 차수(order) 이상 줄일 수 있다. 또한 세정공정시 상기와 같은 고온의 NH4OH를 이용하면, 반도체기판(20)의 유동이온(Na+,K+)을 줄여서 게이트산화막의 질을 높일 수 있게 된다.In addition, by using high temperature NH 4 OH, the etching rate of the semiconductor substrate 20 is increased, and the semiconductor substrate 20 is etched by about 10 Å during the cleaning process, thereby reducing defects of the semiconductor substrate 20 itself by more than 10E1 orders. Can be. In addition, when the high temperature NH 4 OH is used in the cleaning process, the quality of the gate oxide film can be improved by reducing the flow ions Na + and K + of the semiconductor substrate 20.

이와 같이 형성된 캐미컬산화막(22)의 위 부분에 대하여 1000℃ 이상의, 예를 들어 1050℃의 N2가스 분위기에서 10분이상 어닐링을 실시하는데, 이때 0.4ℓ 이상의 DCS가스를 버블링(bubbling)시켜서 캐미컬산화막(20)을 두껍게 하면서 C??기를 이용하여 캐미컬산화막(22)속에 있는 불순물을 제거한다.The upper portion of the chemical oxide film 22 formed as described above is annealed for at least 10 minutes in an N 2 gas atmosphere of 1000 ° C. or higher, for example, 1050 ° C., in which 0.4 C or more DCS gas is bubbling While the curl oxide film 20 is thickened, impurities in the chemical oxide film 22 are removed using C ??.

그 후 온도를 750℃ 내지 900℃로 낮추어, 도 2b에 도시된 바와 같은 유전상수가 커서 절연특성이 우수산 질화산화막(23)을 30Å 내지 50Å 두께로 성장시킨다. 여기서, 질화산화막(23)은 필요에 따라 20Å 이하로 성장시킬 수 있다. 이러한 질화산화막(23)의 형성시 캐미컬산화막(22)은 응력을 완화시키기 위한 버퍼역할을 하게 된다. 질화산화막(23)을 형성하기 위한 공정은 30분 이상 실시되고, 질화산화막(23) 형성시 사용되는 가스는 NO, N2O 그리고 NxOy로 이루어진다.Thereafter, the temperature is lowered to 750 ° C to 900 ° C, and the dielectric constant as shown in FIG. 2B is large, so that the excellent acid nitride oxide film 23 is grown to have a thickness of 30 kPa to 50 kPa. Here, the nitride oxide film 23 can be grown to 20 kPa or less as needed. When the nitride oxide film 23 is formed, the chemical oxide film 22 serves as a buffer to relieve stress. The process for forming the nitride oxide film 23 is performed for 30 minutes or more, and the gas used for forming the nitride oxide film 23 is composed of NO, N 2 O, and N x O y .

이와 같이 캐미컬산화막(22)과 질화산화막(23)을 순차적으로 적층하여 이를 게이트산화막(30)으로 사용하게 되면, 상기와 같이 종래의 단점들을 해결할 수 있고, 아울러 게이트산화막의 두께를 감소시켜 게이트의 문턱전압(Vt)값을 낮출 수 있어 소자축소를 용이하게 할 수 있다.As such, when the chemical oxide film 22 and the nitride oxide film 23 are sequentially stacked and used as the gate oxide film 30, the conventional disadvantages as described above can be solved, and the thickness of the gate oxide film is reduced to reduce the gate. The threshold voltage (Vt) value of can be lowered, so that device reduction can be facilitated.

이상에서 살펴 본 바와 같이, 본 발명은 캐미컬산화막(22) 및 질화산화막(23)의 형성 전에 고온의 NH4OH를 적용하여 세정공정을 실시한다. 이 세정공정에서는 응력에 대한 버퍼역할을 하는 캐미컬산화막(22)이 소정의 두께로 성장됨과 아울러, 게이트산화막(30)의 형성 전에 여러 공정을 거치면서 반도체기판(20)의 상부로 확산되는 결함들이 제거되어 소자특성을 향상시킬 수 있고, 반도체기판(20)의 표면에 존재하는 불순물을 제거할 수 있으며, 질화산화막(23)의 형성시 발생되는 응력을 완화할 수 있다. 또한 본 발명은 게이트산화막(30)을 형성하기 위하여 유전상수가 커서 절연특성이 우수한 질화산화막(23)을 이용하기 때문에 게이트산화막(30)의 두께를 감소시켜 게이트의 문턱전압을 낮출 수 있고 이에 따라 소자축소가 용이하게 된다.As described above, in the present invention, a high temperature NH 4 OH is applied to the cleaning process before the chemical oxide film 22 and the nitride oxide film 23 are formed. In this cleaning process, the chemical oxide film 22, which acts as a buffer for stress, is grown to a predetermined thickness, and the defect is diffused to the upper portion of the semiconductor substrate 20 through various processes before the gate oxide film 30 is formed. These components can be removed to improve device characteristics, to remove impurities present on the surface of the semiconductor substrate 20, and to relieve stress generated when the nitride oxide film 23 is formed. In addition, in the present invention, since the nitride oxide film 23 having a high dielectric constant is used to form the gate oxide film 30 and having excellent insulation characteristics, the gate voltage of the gate 30 can be reduced, thereby reducing the threshold voltage of the gate. Device reduction is easy.

Claims (6)

소자분리를 위한 아이솔레이션 공정을 실시하여 반도체기판상의 필드영역에 필드산화막을 형성하는 단계;Forming a field oxide film in the field region on the semiconductor substrate by performing an isolation process for device isolation; 상기 필드산화막이 형성된 구조 전면에 희생산화막을 형성하는 단계;Forming a sacrificial oxide film over the entire structure of the field oxide film; 상기 희생산화막이 형성된 웨이퍼에 대하여 고온의 세정용액을 이용한 세정을 실시하여 캐미컬산화막을 형성하는 단계;Performing a cleaning using a high temperature cleaning solution on the wafer on which the sacrificial oxide film is formed to form a chemical oxide film; 상기 캐미컬산화막이 형성된 구조의 상부에 대하여 고온의 가스분위기에서 어닐링을 실시하는 단계; 및Annealing the upper portion of the structure in which the chemical oxide film is formed in a hot gas atmosphere; And 상기 캐미컬산화막이 형성된 구조의 전면에 질화산화막을 형성하는 단계;를 포함하여 구성되는 반도체소자의 게이트산화막 형성방법.Forming a nitride oxide film on the entire surface of the structure where the chemical oxide film is formed. 제1항에 있어서, 상기 세정용액은The method of claim 1, wherein the cleaning solution NH4OH, H2O로 이루어지고 그 조성비율은 4:6:1로 유지되는 것을 특징으로 하는 반도체소자의 게이트산화막 형성방법.A method of forming a gate oxide film of a semiconductor device, comprising: NH 4 OH, H 2 O, and the composition ratio of which is maintained at 4: 6: 1. 제 1항에 있어서, 상기 어닐링을 실시하는 단계는The method of claim 1, wherein performing the annealing N2가스 분위기에서 1000℃ 이상에서 10분이상 실시되고, 0.4ℓ이상의 DCS가스가 버블링(bubbling)되어 실시되는 것을 특징으로 하는 반도체소자의 게이트산화막 형성방법.A method of forming a gate oxide film of a semiconductor device, characterized in that carried out for 10 minutes or more at 1000 ° C. or more in an N 2 gas atmosphere, followed by bubbling of 0.4 L or more DCS gas. 제1항에 있어서, 상기 질화산화막은The method of claim 1, wherein the nitride oxide film NO, N2O 그리고 NxOy로 구성되는 가스를 이용하여 형성되는 것을 특징으로 하는 반도체소자의 게이트산화막 형성방법.A method of forming a gate oxide film of a semiconductor device, characterized in that formed using a gas consisting of NO, N 2 O and N x O y . 제1항에 있어서, 상기 질화산화막을 형성하는 단계는The method of claim 1, wherein forming the nitride oxide film 750℃ 내지 900℃의 온도에서 30분 이상 실시되는 것을 특징으로 하는 반도체소자의 게이트산화막 형성방법.The method of forming a gate oxide film of a semiconductor device, characterized in that carried out for 30 minutes or more at a temperature of 750 ℃ to 900 ℃. 제1항에 있어서, 상기 세정용액은The method of claim 1, wherein the cleaning solution 80℃ 이상의 고온인 것을 특징으로 하는 반도체소자의 게이트산화막 형성방법.A method of forming a gate oxide film of a semiconductor device, characterized in that the high temperature of 80 ℃ or more.
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