KR20010019770A - Fabrication method of wafer-level flip chip packages using pre-coated Anisotropic Conductive Adhesives - Google Patents
Fabrication method of wafer-level flip chip packages using pre-coated Anisotropic Conductive Adhesives Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000000853 adhesive Substances 0.000 title claims abstract description 36
- 230000001070 adhesive effect Effects 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910000679 solder Inorganic materials 0.000 claims abstract description 30
- 239000010931 gold Substances 0.000 claims abstract description 25
- 229910052737 gold Inorganic materials 0.000 claims abstract description 24
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 15
- 229920000642 polymer Polymers 0.000 claims abstract description 7
- 239000002904 solvent Substances 0.000 claims abstract description 5
- 239000003822 epoxy resin Substances 0.000 claims abstract description 4
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 4
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 3
- 238000003475 lamination Methods 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- 239000002245 particle Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 230000005499 meniscus Effects 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 239000007921 spray Substances 0.000 claims description 2
- 238000010345 tape casting Methods 0.000 claims description 2
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 claims 3
- 239000000758 substrate Substances 0.000 abstract description 18
- 239000000463 material Substances 0.000 abstract description 9
- 238000002161 passivation Methods 0.000 abstract description 3
- 238000007772 electroless plating Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 39
- 238000005516 engineering process Methods 0.000 description 25
- 239000004065 semiconductor Substances 0.000 description 9
- 230000004907 flux Effects 0.000 description 8
- 238000011161 development Methods 0.000 description 3
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000004100 electronic packaging Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 235000011201 Ginkgo Nutrition 0.000 description 1
- 241000218628 Ginkgo Species 0.000 description 1
- 235000008100 Ginkgo biloba Nutrition 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000000637 aluminium metallisation Methods 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
본 발명은 도포된 이방성 전도 접착제 (Anisotropic Conductive Adhesives)를 이용한 웨이퍼형 플립 칩 패키지 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a wafer type flip chip package using coated anisotropic conductive adhesives.
전자 패키지 기술은 반도체 소자에서부터 최종제품까지의 모든 단계를 포함하는 매우 광범위하고 다양한 시스템 제조기술로서 최근 급속히 발전하는 반도체기술은 이미 백만 개 이상의 셀(cell) 집적, 비메모리 소자의 경우 I/O 핀 개수의 다수화, 다이 크기의 대형화, 대량의 열 방출, 고전기적 성능 등의 경향으로 발전하고 있다. 그러나 상대적으로 이런 소자를 패키지하기 위한 전자 패키징 기술은 급속한 반도체 발전을 따라가지 못하고 있다.Electronic package technology is a very broad and diverse system manufacturing technology that covers all stages from semiconductor devices to end products. The rapidly developing semiconductor technology already has more than one million cell integrated and I / O pins for non-memory devices. The trend is to increase the number of pieces, increase the size of dies, dissipate large amounts of heat, and achieve high electric performance. Relatively, however, electronic packaging technologies for packaging these devices have not kept up with rapid semiconductor development.
전자 패키지기술은 최종전자 제품의 성능, 크기, 가격 및 신뢰성 등을 결정하는 매우 중요한 기술이다. 특히 고전기적 성능, 극소형/고밀도, 저 전력, 다기능, 초고속 신호 처리, 영구적 신뢰성을 추구하는 최근의 전자제품에 있어 극소형 패키지 부품은 컴퓨터, 정보통신, 이동 통신, 고급 가전제품 등의 필수 부품으로서, 이 중 칩을 기판에 실장하는 기술 중의 하나인 플립 칩(Flip Chip) 기술은 현재 스마트 카드(Smart Cards), LCD, PDP 등의 디스플레이 패키징(Display Packaging), 컴퓨터, 휴대용 전화기, 통신시스템 등에 그 활용 범위를 넓혀 가고 있다. 이러한 플립칩 기술은 기존의 솔더를 이용한 복잡한 접속공정, 즉 솔더 플럭스 도포, 칩/기판 정렬, 솔더 범프 리플로우, 플럭스 제거, 언더필 충진 및 경화 등의 공정을 거치게 됨으로 인하여 공정의 복잡성 및 원가상승의 문제점이 있다.Electronic package technology is a very important technology that determines the performance, size, price and reliability of the final electronic product. Particularly in today's electronics that pursue high performance, ultra small / high density, low power, multifunction, ultra-fast signal processing, and permanent reliability, ultra-small packaged parts are essential parts for computers, telecommunications, mobile communications, and high-end consumer electronics. Among them, flip chip technology, which is one of the technologies for mounting a chip on a substrate, is currently used in display packaging such as smart cards, LCDs, and PDPs, computers, mobile phones, and communication systems. The range of application is expanding. This flip-chip technology uses complex soldering processes, such as solder flux application, chip / substrate alignment, solder bump reflow, flux removal, underfill filling and hardening, resulting in increased complexity and cost. There is a problem.
따라서 최근에는 이러한 복잡한 공정을 줄이기 위해 웨이퍼 상태에서 플럭스와 언더필의 기능을 갖는 폴리머 재료를 도포하여 가공하는 웨이퍼 차원 패키지 기술에 많은 관심을 가지고 있다. 또한 최근에는 일반적인 솔더 플립 칩에 비해 저가이며 극미세의 전극 피치가 가능하고 리드 프리(lead free), 환경친화적인 플럭스리스(fluxless) 공정, 저온 공정 등의 장점을 가지는 전도성 접착제를 이용한 플립 칩 접속 기술개발이 진행되고 있다.Therefore, in recent years, there has been a great deal of interest in wafer dimension package technology in which a polymer material having a function of flux and underfill is applied and processed in a wafer state to reduce such a complicated process. In recent years, compared to conventional solder flip chips, flip chip connections using conductive adhesives have the advantages of low-cost, ultra-fine electrode pitch, and lead-free, environmentally friendly fluxless and low temperature processes. Technology development is in progress.
전도성 접착제는 크게 이방성 도전 접착제/필름(Anisotropic Conductive Adhesive/Flim), 등방성 도전 접착제(Isotropic Conductive Adhesive) 등의 형태가 있으며 기본적으로 니켈, 금/폴리머, 은(Ni, Au/polymer, Ag) 등의 도전성 입자들과 열경화성, 열가소성의 절연수지(insulating resin)로 구성되어 있다. 저가의 접착제 제조공정과 이러한 접착제를 이용한 저가의 플립 칩 공정개발을 위하여 경화가 빠른 열경화성 에폭시 레진을 이용한 ACA의 개발이 필요하게 되었다. ACA도 필름 형태(Anisotropic Conductive Adhesive Film; ACAF)와 페이스트(Anisotropic Conductive Adhesive Paste; ACAP) 형태로 구분할 수 있으며, 접속공정과 접착제의 제조공정의 간편성을 위해 최근 페이스트 형태의 접착제가 개발되고 있다.Conductive adhesives come in the form of anisotropic conductive adhesives / films and isotropic conductive adhesives, and are basically nickel, gold / polymers, silver (Ni, Au / polymer, Ag), etc. Consists of conductive particles, thermosetting and thermoplastic insulating resin. In order to develop a low cost adhesive manufacturing process and a low cost flip chip process using such an adhesive, it is necessary to develop an ACA using a fast curing thermosetting epoxy resin. ACA can be classified into anisotropic conductive adhesive film (ACAF) and paste (anisotropic conductive adhesive paste) (ACAP), and paste-type adhesives have recently been developed for simplicity of the connecting process and the adhesive manufacturing process.
이러한 환경 친화적인 이방성 전도성 필름이나 페이스트를 접속 재료로 하는 플립 칩 기술에 대한 기술적인 연구가 활발히 이루어져 왔지만, ACA용 플립 칩 형태의 패키지를 위한 칩의 설계 및 범프 형성 공정, 접속재료의 대량생산 및 접속 공정의 자동화에 소요되는 모든 공정은 많은 공정 단계를 거치게 되며 결과적으로 고가의 기술이 되어 그 범용성에 한계가 있었다.Although technical research on flip chip technology using an environmentally friendly anisotropic conductive film or paste as a connection material has been actively conducted, the chip design and bump forming process for ACA flip chip type packages, mass production of connection material, All the processes required for the automation of the connection process go through many process steps, and as a result, they become expensive technologies and have limited utility.
본 발명과 관련된 종래기술로서, 미국특허 5,323,051(Semiconductor wafer level package, 6/21/1994)는 웨이퍼 상태에서 또 다른 cap wafer를 유리 접착제로 접착시킨 후 웨이퍼를 각각의 칩으로 절단하는 기술로서 본 발명의 ACA를 도포하여 이를 패키지 접속용으로 사용하는 것과는 매우 다른 특허이다. 또 다른 미국특허 5,918,113(Process for producing a semiconductor device using anisotropic conductive adhesive, 6/29/1999)은 ACA를 기판에 부착시킨 후 반도체 칩을 열과 압력으로 기판에 접촉시킴으로 전기적으로 연결시키는 방법이나, 본 발명은 ACA를 웨이퍼 상태에서 비솔더 범프 형성된 칩에 미리 도포하는 면에서 매우 다른 기술 방법이다. 문헌으로서는 시(S.H.Shi, T. Yamashita and C.P.Wong. "Development of the Wafer Level Compressive-Flow Underfill Process and Its Required Materials" 1999 ECTC, pp.961-966)등이 발표한 솔더 범프가 형성된 웨이퍼 위에 솔더 플럭스 기능을 포함한 언더필 재료를 도포한 뒤 각 칩을 다이싱한 후 기존의 SMT 어셈브리(assembly) 장치를 이용하여 기판에 정열한다. 이로 말미암아 기존의 솔더 리플로우 접속 후 언더필 재료를 칩과 기판 사이에 넣는 공정을 간소화한 방법을 소개한 내용이다. 그러나 기존의 솔더범프가 아닌 전해 또는 스터드(Stud) 금 범프, 무전해 니켈 또는 구리 범프 등의 비솔더 범프가 형성된 웨이퍼 위에 이방성 전도 접착제를 용액 또는 필름으로 도포한 후 웨이퍼 상태에서 각 칩을 다이싱한 후 바로 기판에 열과 압력으로 도포한 이방성 전도 접착제를 사용하여 접착함으로써 기존의 솔더와 언더필 재료를 사용한 접속 공정보다 매우 간단하고 가장 저렴한 공정이다.As a related art related to the present invention, US Patent No. 5,323,051 (Semiconductor wafer level package, 6/21/1994) is a technology for cutting another wafer into a chip after adhering another cap wafer with a glass adhesive in a wafer state. This is a very different patent from the application of ACA and the use of it for package connection. Another US Pat. No. 5,918,113 (Process for producing a semiconductor device using anisotropic conductive adhesive, 6/29/1999) discloses a method of electrically connecting a semiconductor chip by contacting the substrate with heat and pressure after attaching the ACA to the substrate. Is a very different technique in terms of pre-applying ACA to a nonsolder bump formed chip in wafer state. Literature includes solder on wafers with solder bumps published by SHShi, T. Yamashita and CPWong. "Development of the Wafer Level Compressive-Flow Underfill Process and Its Required Materials" 1999 ECTC, pp.961-966. After applying the underfill material including the flux function, each chip is diced and aligned on the substrate using a conventional SMT assembly apparatus. This shows how to simplify the process of placing underfill material between the chip and the substrate after conventional solder reflow connections. However, anisotropic conductive adhesive is applied as a solution or film on a wafer on which nonsolder bumps, such as electrolytic or stud gold bumps, electroless nickel or copper bumps, are formed instead of conventional solder bumps, and each chip is diced in the wafer state. It is then very simple and inexpensive compared to the conventional solder and underfill material connection process by using an anisotropic conductive adhesive applied to the substrate by heat and pressure.
상기한 바와 같이 전자 패키징 기술은 사용재료의 선택, 공정개발 및 환경 친화적인 제품의 경향에 발맞추어 기존의 솔더 접속을 대체할 수 있는 전도성 접착제의 활용을 앞 당겨야 할 것이다.As mentioned above, electronic packaging technology will have to push ahead with the use of conductive adhesives that can replace conventional solder connections in line with the choice of materials used, process development and environmentally friendly products.
본 발명은 웨이퍼형의 비솔더 범프 플립 칩 패키지를 제조하여 종래의 솔더 범프 플립 칩 패키지 제조 후 기판 접속 시 발생되는 후속공정인 솔더 플럭스 도포, 플립 칩/기판 정렬, 솔더 리플로우, 플럭스 청정, 언더필 충진 및 경화 등의 공정을 단순화시켜 저가형 웨이퍼형 플립 칩 기술을 제공하는 데 있다.The present invention manufactures a wafer-type non-solder bump flip chip package, and after the conventional solder bump flip chip package manufacturing, solder flux coating, flip chip / substrate alignment, solder reflow, flux clean, underfill It is to provide a low-cost wafer type flip chip technology by simplifying the filling and curing process.
도 1a는 반도체 웨이퍼.1A is a semiconductor wafer.
도 1b는 도 1a의 A-A' 단면도이다.FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A.
도 2a는 저가형 비솔더 범프 형성 공정 중 한가지인 무전해 니켈/금 도금방법을 통해 범프를 형성시킨 후의 웨이퍼.2A is a wafer after bump formation through an electroless nickel / gold plating method, one of the low cost non-solder bump formation processes.
도 2b는 도 2a의 A-A' 단면도이다.FIG. 2B is a cross-sectional view taken along the line AA ′ of FIG. 2A.
도 3a는 이방성 도전성 접착제를 범프가 형성된 웨이퍼 위에 용액으로 도포하거나 또는 필름상태로 라미네이션 방법으로 도포한 후의 웨이퍼.3A is a wafer after applying an anisotropic conductive adhesive as a solution on a bumped wafer or by lamination in a film state.
도 3b는 도 3a의 A-A' 단면도이다.3B is a cross-sectional view taken along the line A-A 'of FIG. 3A.
도 4a는 웨이퍼 다이싱 공정을 나타낸다.4A shows a wafer dicing process.
도 4b는 웨이퍼 다이싱 공정 후의 칩의 단면도이다.4B is a cross-sectional view of the chip after the wafer dicing process.
도 5는 상기에서 제조된 개별 칩을 기판 위에 정렬한 후 열과 압력을 가해 칩과 기판을 전기적으로 연결시키는 플립칩 제조공정을 나타낸다.5 illustrates a flip chip manufacturing process in which the individual chips prepared above are aligned on a substrate and then electrically connected the chip and the substrate by applying heat and pressure.
도 6은 플립칩 사진이다.6 is a flip chip photograph.
＜도면의 주요부분에 대한 부호의 설명 ＞<Description of the code | symbol about the principal part of drawing>
1: 웨이퍼 2: I/O 패드1: wafer 2: I / O pad
3: 패시베이션층 4: 무전해도금 니켈/금 범프3: passivation layer 4: electroless nickel / gold bump
5: 보호층 6: ACA5: protective layer 6: ACA
7: 다이싱 처리된 칩7: Diced Chip
본 발명은 종래의 솔더 범프 플립 칩 패키지 제조 후 기판 접속 시 발생되는 후속공정인 솔더 플럭스 도포, 플립 칩/기판 정렬, 솔더 리플로우, 플럭스 청정, 언더필 충진 및 경화 등의 공정을 단순화시켜 저가의 웨이퍼형 플립 칩 기술을 완성하였다. 특히 비솔더 범프 기술인 금 스터드(stud) 범프, 무전해 Ni/Au 범프 등을 사용한 웨이퍼형 플립 칩 패키지 기술을 개발하고, 저가형 비솔더 범프 기술과 이방성 전도 접착제 재료기술을 사용하여 웨이퍼 상에서 가공함으로써 새로운 웨이퍼 차원 플립 칩 패키지 기술을 구현한다. 또한 웨이퍼 상태에서 다이싱된 칩을 기판에 정렬시킨 후 열과 압력만을 가함으로써 이방성 전도 접착제 내의 도전 입자들을 통해 전기적으로 접속되며 폴리머 수지를 통해 기계적으로 접속시키며 저가형 비솔더 범프 기술과 이방성 전도 접착제를 웨이퍼 상태에서 구현하여 새로운 웨이퍼형 패키지를 제조한다. 이하 실시예를 통하여 보다 상세히 설명하고 자 한다.The present invention simplifies low cost wafers by simplifying processes such as solder flux application, flip chip / substrate alignment, solder reflow, flux cleaning, underfill filling and curing, which are the subsequent processes that occur when connecting a substrate after manufacturing a conventional solder bump flip chip package. Complete flip chip technology. In particular, we developed wafer-type flip chip package technology using non-solder bump technology such as gold stud bump and electroless Ni / Au bump, and processed on wafer using low cost non-solder bump technology and anisotropic conductive adhesive material technology. Implement wafer-dimensional flip chip package technology. In addition, by aligning the diced chip in the wafer state to the substrate and applying only heat and pressure, the chip is electrically connected through the conductive particles in the anisotropic conductive adhesive, mechanically connected through the polymer resin, and the low-cost non-solder bump technology and the anisotropic conductive adhesive Implement in state to manufacture new wafer-type packages. Through the following examples will be described in more detail.
＜실시예 ＞<Example>
일반적인 반도체 공정을 통해 제조된 웨이퍼는 도 1에 나타난 바와 같이 많은 칩들이 있고 각 칩 마다 신호의 연결을 위한 입출력단자(I/O pad)들이 있으며 각 칩의 단면을 보면 Al I/O 패드와 표면안정화(passivation) 층을 볼 수 있다. 이 웨이퍼의 각 칩의 I/O 위에 저가형 비솔더 범프를 형성한다.As shown in FIG. 1, a wafer manufactured by a general semiconductor process has many chips, and each chip has input / output terminals (I / O pads) for signal connection. A passivation layer can be seen. Low cost non-solder bumps are formed on the I / O of each chip of the wafer.
* 비솔더 범프 형성공정* Non-solder bump forming process
도 2에서는 웨이퍼의 각 칩의 I/O 위에 저가형 비솔더 범프를 형성하기 위하여 무전해 니켈/금 도금방법 또는 금 스터드 범프, 동 범프 등도 형성이 가능함을 알 수 있다. 일반적인 Al metallization이 사용되는 반도체 제조공정에 의해 제조된 웨이퍼는 Al I/O를 가지고 있다.In FIG. 2, it can be seen that an electroless nickel / gold plating method, a gold stud bump, a copper bump, or the like may be formed to form a low-cost non-solder bump on the I / O of each chip of the wafer. A wafer manufactured by a semiconductor manufacturing process using general Al metallization has Al I / O.
웨이퍼에 형성된 저가형 비솔더 범프는 금 스터드 범프의 경우, 금 본딩 와이어(bonding wire) 본더를 사용하여 금 범프를 형성하고,무전해 니켈/금 도금방법을 사용한 경우는 니켈도금 전에 Al을 활성화시키기 위하여 징케이트로 처리한다. 니켈도금은 90℃에서 20~30 분 정도 도금을 하여 10~15 ㎛의 높이를 갖도록 하고, 금 도금은 60℃에서 30분간 도금을 하여 니켈의 산화를 방지한다.Low-cost non-solder bumps formed on the wafer are used for gold stud bumps, gold bonding wire bonders to form gold bumps, and electroless nickel / gold plating methods to activate Al before nickel plating. Treat it as a ginkgo. Nickel plating should be plated at 90 ° C. for 20-30 minutes to have a height of 10-15 μm, and gold plating should be plated at 60 ° C. for 30 minutes to prevent oxidation of nickel.
* 이방성 도전성 접착제 도포공정* Anisotropic conductive adhesive coating process
도 3과 같이 범프가 형성된 웨이퍼 위에 ACA를 용액으로 스프레이, 닥터 블레이드(doctor blade), 메니스커스(meniscus) 방법 등을 사용하여 도포할 수도 있으나 본 발명에서는 ACAF의 경우를 고려하여 라미네이션 방법으로 이방성 도전성 접착 필름을 두께 약 20~25 ㎛으로 도포한다. 저가형 비솔더 범프가 형성된 웨이퍼를 진공상태에 70℃~80℃에서 5~10 초간 1~2 kgf/㎤의 압력으로 ACF를 만들기 위해 보이드(void)가 없도록 웨이퍼 전체에 20~25 ㎛ 두께가 되도록 라미네이션 방법으로 도포한다. 이때 ACA의 레진은 50% 정도의 경화가 된 반경화 상태를 유지한다. ACA는 니켈 또는 금이 코팅된 폴리머 볼(Au-coated polymer ball)을 2~15 wt% 섞은 에폭시 레진과 솔벤트, 이미다졸(imidazole)계의 경화제를 에폭시 100g 당 7∼10 g을 섞은 혼합물을 웨이퍼보다 큰 이형지 필름 위에 닥터 블레이딩 방법으로 필름을 형성한 후 오븐을 이용하여 80℃에서 1∼2분간 솔벤트를 제거하여 웨이퍼 레벨 패키지에 적합한 형태의 ACF로 제조한다. 이 ACF는 150℃에서 5분내에 경화가 가능한 경화특성을 갖는다. 라미네이션 후 각 범프 주위에 보이드가 생기는 현상 (shadowing)을 일으키지 않도록 라미네이션 장비와 필름의 특성을 조절하는 것이 필요하며 라미네이션은 진공 중에서 가압할 수 있도록 설계하였다. 라미네이터에서 웨이퍼를 꺼내 이형지 필름을 제거하여 다이싱 공정으로 보낸다.ACA may be applied onto the bump-formed wafer as shown in FIG. 3 using a spray, a doctor blade, a meniscus method, or the like, but the present invention is anisotropic in a lamination method in consideration of the case of ACAF. A conductive adhesive film is applied with a thickness of about 20 to 25 μm. Low-cost non-solder bumps are 20-25 μm thick throughout the wafer so that there is no void to make the ACF at a pressure of 1-2 kgf / cm3 for 5-10 seconds at 70 ℃ ~ 80 ℃ under vacuum. Apply by lamination method. At this time, the resin of the ACA maintains the semi-cured state of about 50%. ACA is a wafer containing a mixture of epoxy resin mixed with 2-15 wt% of nickel- or gold-coated polymer balls, 7-10 g per 100 g of epoxy, solvent and imidazole-based curing agent. After the film is formed on the larger release paper film by the doctor blading method, the solvent is removed at 80 ° C. for 1 to 2 minutes using an oven to prepare an ACF in a form suitable for a wafer level package. This ACF has a curing property that can be cured at 150 ° C. within 5 minutes. After lamination, it is necessary to adjust the characteristics of the lamination equipment and the film so as not to cause shadowing around each bump, and the lamination is designed to pressurize in vacuum. The wafer is taken out of the laminator and the release paper film is removed and sent to the dicing process.
* 웨이퍼 다이싱 공정* Wafer dicing process
웨이퍼 다이싱 머신에 ACA가 미리 부착된 웨이퍼를 장착시켜 웨이퍼의 스크라이브 라인을 확인한 후 다이싱 머신을 통해 개별 칩을 얻기 위해 다이싱을 시행한다. ACA를 도포한 후 웨이퍼를 다이싱하고 개별 칩을 플립 칩 공정을 하여 기판과 정렬시키기 위해서는 ACA를 통해서 스크라이빙 라인 및 정렬 패드를 인식할 수 있도록 ACA는 투명해야한다. 이때 웨이퍼에 도포된 이방성 전도 접착제는 다이싱 공정에서 분리(delamination)되지 않도록 웨이퍼와 높은 접착력을 가져야 하며 다이싱 공정과 본딩 공정시 스크라이빙 라인 (scribing line) 검사 및 기판과의 정렬이 가능할 정도의 투명성을 갖기위하여 ACA 내에 도전입자로 니켈 또는 금 코팅된 폴리머 입자의 양은 2~15 wt%를 첨가한다. 다이싱 후의 각 칩은 하나의 플립 칩 패키지로서 사용될 수 있다.The wafer is pre-attached with an ACA attached to the wafer dicing machine to check the scribe line of the wafer and then dicing to obtain individual chips through the dicing machine. After applying the ACA, the ACA must be transparent so that the scribing lines and alignment pads can be recognized by the ACA in order to dice the wafer and align the individual chips with the substrate by flip chip processing. At this time, the anisotropic conductive adhesive applied to the wafer should have high adhesion with the wafer so as not to be delaminated in the dicing process, and the scribing line inspection and the alignment with the substrate during the dicing process and the bonding process can be performed. In order to have a transparency of 2-15 wt%, the amount of polymer particles coated with nickel or gold with conductive particles in the ACA is added. Each chip after dicing can be used as one flip chip package.
* ACA가 한 면에 부착된 칩의 플립 칩 접속공정* Flip chip connection process of chip with ACA attached on one side
다이싱한 개별 칩은 이미 ACA가 도포되어 있으므로 기판에 정렬한 후 열과 압력을 가해 경화됨으로서 기계적, 전기적 조립이 일어나도록 한다. 도 5는 보존층을 제거한 후 ACA가 부착되어 있는 칩을 여러 가지 형태의 기판 위에 전극과 정렬시킨 후 플립 칩 본더를 사용하여 150℃, 5분에 경화되도록 열압착시킨다.The individual chips that have been diced are already coated with ACA, which is then aligned with the substrate and cured by applying heat and pressure to allow mechanical and electrical assembly. 5, after removing the preservation layer, the ACA-attached chips are aligned with the electrodes on various substrates, and then thermocompressed to be cured at 150 ° C. for 5 minutes using a flip chip bonder.
본 발명의 이방성 전도성 접착제를 이용한 웨이퍼형 플립 칩 패키지 기술은 공정이 간단하여 경제적이고 기술적 파급효과가 크며 부가가치가 높다. 또한 환경친화적인 공정을 채택하고 있으므로 실용성이 높은 기술이다.The wafer-type flip chip package technology using the anisotropic conductive adhesive of the present invention has a simple process, economical, high technical ripple effect and high added value. It is also a highly practical technology because it adopts environmentally friendly processes.
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| KR100398314B1 (en) * | 2001-07-19 | 2003-09-19 | 한국과학기술원 | High Adhesion Triple layered anisotropic conductive adhesive film |
| KR100821962B1 (en) * | 2007-06-19 | 2008-04-15 | 한국과학기술원 | Fabrication method of wafer-level flip chip package using acf/ncf solution |
| KR100833937B1 (en) * | 2002-03-28 | 2008-05-30 | 삼성테크윈 주식회사 | Anisotropic conductive adhesive |
| KR100838647B1 (en) * | 2007-07-23 | 2008-06-16 | 한국과학기술원 | Wafer-level acf flip chip package using double-layered acf/ncf |
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| KR101156177B1 (en) * | 2010-06-16 | 2012-06-18 | 한국생산기술연구원 | Anisotropic Conductive Film Having Containing Groove of Conductive Material, Joining Method of Flip Chip Using Epoxy Resin Having Containing Groove of Conductive Material and Flip Chip Package Using the Same |
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| JPH04292803A (en) * | 1991-03-20 | 1992-10-16 | Hitachi Ltd | Anisotropic conductive film |
| JP3408894B2 (en) * | 1995-05-17 | 2003-05-19 | 日東電工株式会社 | Manufacturing method of semiconductor chip |
| KR970073941A (en) * | 1996-05-16 | 1997-12-10 | 김광호 | Chip Scale Package Using Anisotropic Conductive Film |
| JP3526731B2 (en) * | 1997-10-08 | 2004-05-17 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP3663938B2 (en) * | 1997-10-24 | 2005-06-22 | セイコーエプソン株式会社 | Flip chip mounting method |
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| KR100398314B1 (en) * | 2001-07-19 | 2003-09-19 | 한국과학기술원 | High Adhesion Triple layered anisotropic conductive adhesive film |
| KR100833937B1 (en) * | 2002-03-28 | 2008-05-30 | 삼성테크윈 주식회사 | Anisotropic conductive adhesive |
| KR100842921B1 (en) * | 2007-06-18 | 2008-07-02 | 주식회사 하이닉스반도체 | Method for fabricating of semiconductor package |
| US7498199B2 (en) | 2007-06-18 | 2009-03-03 | Hynix Semiconductor Inc. | Method for fabricating semiconductor package |
| KR100821962B1 (en) * | 2007-06-19 | 2008-04-15 | 한국과학기술원 | Fabrication method of wafer-level flip chip package using acf/ncf solution |
| KR100838647B1 (en) * | 2007-07-23 | 2008-06-16 | 한국과학기술원 | Wafer-level acf flip chip package using double-layered acf/ncf |
| CN101790781B (en) * | 2007-08-29 | 2012-06-13 | 飞思卡尔半导体公司 | Method of packaging an integrated circuit die |
| KR101156177B1 (en) * | 2010-06-16 | 2012-06-18 | 한국생산기술연구원 | Anisotropic Conductive Film Having Containing Groove of Conductive Material, Joining Method of Flip Chip Using Epoxy Resin Having Containing Groove of Conductive Material and Flip Chip Package Using the Same |
| WO2015170800A1 (en) * | 2014-05-09 | 2015-11-12 | 주식회사 동부하이텍 | Method for packaging semiconductor elements and apparatus for carrying out the method |
| WO2015170792A1 (en) * | 2014-05-09 | 2015-11-12 | 주식회사 동부하이텍 | Method for packaging semiconductor elements and apparatus for carrying out the method |
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