CN112769411A - Wafer-level packaging method and device for surface acoustic wave chip - Google Patents
Wafer-level packaging method and device for surface acoustic wave chip Download PDFInfo
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- CN112769411A CN112769411A CN202011621779.0A CN202011621779A CN112769411A CN 112769411 A CN112769411 A CN 112769411A CN 202011621779 A CN202011621779 A CN 202011621779A CN 112769411 A CN112769411 A CN 112769411A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/64—Filters using surface acoustic waves
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
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- Acoustics & Sound (AREA)
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Abstract
The invention discloses a wafer-level packaging method and a wafer-level packaging device for a surface acoustic wave chip, wherein the method comprises the following steps: covering a cavity protection layer on the wafer substrate; covering a packaging top cover on the cavity protection layer; forming a plurality of through holes on the packaging top cover, wherein the positions of the through holes respectively correspond to the positions right above the pin bonding pads; electrically connecting each through hole with the corresponding pin bonding pad; and cutting the wafer substrate to obtain a plurality of packaging components containing single surface acoustic wave chips. The embodiment of the invention can simplify the process flow, thereby improving the chip packaging efficiency and reducing the chip packaging cost.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a wafer-level packaging method and device for a surface acoustic wave chip.
Background
A wafer-level packaging method of a traditional Surface Acoustic Wave (SAW) chip adopts a Die to substrate (chip-substrate) process method, specifically, gold ball planting balls are firstly made on the SAW chip, then a plurality of SAW chips are ultrasonically attached to a ceramic substrate, and then packaging of the SAW chip is achieved through processes of plastic package, cutting and the like. When the process method is adopted for chip packaging, a plurality of chips need to be respectively pasted on the substrate one by one, the pasting efficiency is low, and the process is complicated, so that the packaging efficiency is correspondingly low, and the packaging cost is high.
Disclosure of Invention
The embodiment of the invention provides a wafer-level packaging method and device of a surface acoustic wave chip, which simplify the process flow, thereby improving the chip packaging efficiency and reducing the chip packaging cost.
A first aspect of the embodiments of the present application provides a wafer-level packaging method for a surface acoustic wave chip, including:
covering a cavity protection layer on the wafer substrate; the wafer substrate is provided with a plurality of surface acoustic wave chips; the cavity protection layer does not cover the sound wave filtering function areas of the multiple surface acoustic wave chips and the pin bonding pads of the multiple surface acoustic wave chips, and the height of the cavity protection layer is larger than that of the multiple surface acoustic wave chips;
covering a packaging top cover on the cavity protection layer, so that the packaging top cover covers the cavity protection layer, the sound wave filtering function areas of the multiple surface acoustic wave chips and the pin bonding pads of the multiple surface acoustic wave chips at the same time;
forming a plurality of through holes on the packaging top cover, wherein the positions of the through holes respectively correspond to the positions right above the pin bonding pads;
electrically connecting each through hole with the corresponding pin bonding pad;
and cutting the wafer substrate to obtain a plurality of packaging components containing single surface acoustic wave chips.
In a possible implementation manner of the first aspect, the electrically connecting each through hole with its corresponding pin pad specifically includes:
the through holes are filled in a heating curing or reflow mode of a conductive material or a metal plating mode, so that the through holes are in contact with the pin pads through the conductive material or the metal plating, and each through hole is electrically connected with the corresponding pin pad.
In a possible implementation manner of the first aspect, a package top cover covers the cavity protection layer, specifically: the packaging top cover covers the cavity protective layer in a mode of mutually bonding with the cavity protective layer.
In one possible implementation form of the first aspect, the package cap is an organic board package cap, an organic film package cap, a ceramic board package cap, a glass board package cap, a metal board package cap, or a composite board package cap.
In one possible implementation manner of the first aspect, the cavity protection layer is made of a photosensitive material.
A second aspect of the embodiments of the present application provides a wafer level packaging apparatus for a surface acoustic wave chip, including: the cutting device comprises a first covering module, a second covering module, a hole opening module, an electric connection module and a cutting module.
The first covering module is used for covering a cavity protection layer on the wafer substrate; the wafer substrate is provided with a plurality of surface acoustic wave chips; the cavity protection layer does not cover the sound wave filtering function areas of the multiple surface acoustic wave chips and the pin bonding pads of the multiple surface acoustic wave chips, and the height of the cavity protection layer is larger than that of the multiple surface acoustic wave chips;
the second covering module is used for covering a packaging top cover on the cavity protection layer, so that the packaging top cover covers the cavity protection layer, the sound wave filtering function areas of the multiple surface acoustic wave chips and the pin bonding pads of the multiple surface acoustic wave chips at the same time;
the hole opening module is used for forming a plurality of through holes on the packaging top cover, and the positions of the through holes respectively correspond to the positions right above the pin bonding pads;
the electrical connection module is used for electrically connecting each through hole with the corresponding pin bonding pad;
the cutting module is used for cutting the wafer substrate to obtain a plurality of packaging components containing single surface acoustic wave chips.
In a possible implementation manner of the second aspect, the electrical connection module is configured to electrically connect each through hole with its corresponding pin pad, specifically:
the through holes are filled in a heating curing or reflow mode of a conductive material or a metal plating mode, so that the through holes are in contact with the pin pads through the conductive material or the metal plating, and each through hole is electrically connected with the corresponding pin pad.
In one possible implementation form of the second aspect, the package cap is an organic board package cap, an organic film package cap, a ceramic board package cap, a glass board package cap, a metal board package cap, or a composite board package cap.
In one possible implementation manner of the second aspect, the cavity protection layer is made of a photosensitive material.
Compared with the prior art, the wafer-level packaging method and device for the surface acoustic wave chip provided by the embodiment of the invention have the beneficial effects that: according to the packaging method provided by the embodiment of the invention, a cavity protection layer is covered on a wafer substrate containing a plurality of surface acoustic wave chips, a packaging top cover is covered on the cavity protection layer, a plurality of through holes corresponding to positions right above a plurality of pin bonding pads are formed in the packaging top cover, each through hole is electrically connected with the corresponding pin bonding pad, and finally the wafer substrate is cut to obtain a plurality of packaging components containing single surface acoustic wave chips. The above method does not require the following steps as in the conventional chip packaging method: the multiple chips are respectively pasted on the ceramic substrate one by one and then packaged, so that the step of pasting is omitted, and the process flow is simplified; meanwhile, the packaging of a plurality of surface acoustic wave chips can be realized at one time, the chip packaging efficiency is improved, and the chip packaging cost is reduced.
Drawings
Fig. 1 is a schematic flowchart of a wafer-level packaging method for a saw chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram after S1 in the wafer-level packaging method for implementing the saw chip according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram after S2 in the wafer-level packaging method for implementing the saw chip according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram after S3 in the wafer-level packaging method for implementing the saw chip according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram after S4 in the wafer-level packaging method for implementing the saw chip according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram after S5 in the wafer-level packaging method for implementing the saw chip according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a surface wave chip wafer level package apparatus according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a schematic flow chart of a wafer-level packaging method for a surface acoustic wave chip according to an embodiment of the present invention is shown, including:
s1: a cavity protection layer is covered on the wafer substrate.
In this embodiment, a plurality of saw chips are fabricated on a wafer substrate; the cavity protection layer does not cover the sound wave filtering function areas of the plurality of surface acoustic wave chips and the pin bonding pads of the plurality of surface acoustic wave chips, and the height of the cavity protection layer is larger than that of the plurality of surface acoustic wave chips.
In this embodiment, the cavity protection layer is made of a photosensitive material.
In one embodiment, the material used for the cavity protection layer may be a photoresist or a dry film.
In an embodiment, a layer of photoresist is coated on a wafer substrate by spin coating, and the height of the photoresist is greater than the height of a plurality of surface acoustic wave chips on the wafer substrate. And secondly, preparing patterns on the photoresist layer in an exposure and development mode, and exposing the sound wave filtering function areas of the multiple surface acoustic wave chips and the pin bonding pads of the multiple surface acoustic wave chips, so that the cavity protection layer does not cover the sound wave filtering function areas of the multiple surface acoustic wave chips and the pin bonding pads of the multiple surface acoustic wave chips.
S2: and covering a packaging top cover on the cavity protection layer.
In this embodiment, the package top cover covers the cavity protection layer, the acoustic wave filter function regions of the plurality of saw chips, and the pin pads of the plurality of saw chips at the same time.
In this embodiment, the package cap is a organic board package cap, an organic film package cap, a ceramic board package cap, a glass board package cap, a metal board package cap, or a composite board package cap.
In one embodiment, the material used for the top cover of the package is PI resin, BT resin, LCP liquid crystal polymer, etc. with certain mechanical strength.
In this embodiment, the cover of the cavity protection layer by the package top cover is realized by bonding the package top cover to each other, that is, the package top cover or the cavity protection layer has an adhesion layer on a contact surface with each other, and the package top cover and the cavity protection layer can be bonded to each other by the adhesion layer, so that the cover of the package top cover to the cavity protection layer is realized.
In one embodiment, the package cap may be pressed on the cavity protection layer by vacuum lamination.
S3: and a plurality of through holes are formed in the packaging top cover.
In this embodiment, the positions of the through holes respectively correspond to the positions right above the pin pads.
In one embodiment, the vias are formed by laser drilling at locations on the top cover of the package corresponding to the pin pads.
In a specific embodiment, a plurality of through holes may be formed in the package top cover, and then a layer of the package top cover may be covered on the cavity protection layer.
S4: and electrically connecting each through hole with the corresponding pin bonding pad.
In this embodiment, the through holes are filled with a conductive material by thermal curing or reflow or by a metal plating, so that the through holes are in contact with the pin pads through the conductive material or the metal plating, thereby electrically connecting each through hole with the corresponding pin pad.
In this embodiment, the conductive material may be silver paste, tin-silver-copper alloy, etc., and the plating metal may be Cu, Ag, Zn, Cd, Sb, Bi, Mn, Co, Ni, etc.
In one embodiment, a layer of copper is deposited as a metal seed layer on the inner wall of the via hole by magnetron sputtering. And electroplating metal copper in the through hole by using an electroplating technology to realize the electrical connection between the pin bonding pad and the through hole.
S5: and cutting the wafer substrate.
In this embodiment, a plurality of packaged devices including a single saw chip can be obtained after the wafer substrate is diced.
To more intuitively describe a specific flow of the wafer-level packaging method for the saw chip, please refer to fig. 2 to 6, and fig. 2 to 6 are schematic diagrams of specific structures obtained after steps S1 to S5 in the wafer-level packaging method for implementing the saw chip according to an embodiment of the present invention, where the specific structures include: the surface acoustic wave chip packaging structure comprises a wafer substrate 1, an acoustic wave filtering functional area 2 of a surface acoustic wave chip, a pin bonding pad 3 of the surface acoustic wave chip, a cavity protection layer 4, a packaging top cover 5 and a through hole 6.
After the step of S1 is performed, and a cavity protection layer is covered on the wafer substrate, please refer to fig. 2, where fig. 2 is a schematic structural diagram after S1 in the wafer level packaging method for implementing the saw chip according to an embodiment of the present invention.
In this embodiment, it can be intuitively obtained from fig. 2 that the cavity protection layer 4 does not cover the acoustic wave filtering function region 2 of the plurality of surface acoustic wave chips and the pin pads 3 of the plurality of surface acoustic wave chips, and the height of the cavity protection layer 4 is greater than the height of the plurality of surface acoustic wave chips.
After the step of S2 is performed, and a package top cover is covered on the cavity protection layer, please refer to fig. 3, where fig. 3 is a schematic structural diagram after S2 in the wafer level packaging method for implementing the saw chip according to an embodiment of the present invention.
In this embodiment, as can be intuitively seen from fig. 3, the package top cover 5 covers the cavity protection layer 4, the acoustic wave filter function regions 2 of the plurality of saw chips, and the pin pads 3 of the plurality of saw chips at the same time.
After the step of S3 is performed, and a plurality of through holes are formed in the package top cover, please refer to fig. 4, where fig. 4 is a schematic structural diagram after S3 in the wafer level packaging method for implementing the saw chip according to an embodiment of the present invention.
In the present embodiment, as can be seen from fig. 4, the positions of the through holes 6 correspond to positions directly above the lead pads 3, respectively.
Step S4 is implemented, and when each through hole is electrically connected to its corresponding pin pad, please refer to fig. 5, where fig. 5 is a schematic structural diagram after S4 in the wafer level packaging method for implementing a surface acoustic wave chip according to an embodiment of the present invention.
In the present embodiment, as can be seen from fig. 5, the through holes 6 are filled with a conductive material or a plated metal, so that each through hole can be electrically connected to its corresponding pin pad.
After the step of S5 is performed, that is, after the wafer substrate is cut, referring to fig. 6, fig. 6 is a schematic structural diagram after S5 in the wafer level packaging method for implementing the saw chip according to an embodiment of the present invention.
In this embodiment, as can be intuitively obtained from fig. 6, the package component containing a single saw chip obtained by cutting the wafer substrate 1 includes: the surface acoustic wave chip comprises a surface acoustic wave chip, two through holes 6, pin bonding pads 3 of the two surface acoustic wave chips, a cavity protection layer 4, a packaging top cover 5 and a wafer substrate 1.
To further explain the surface wave chip wafer level package apparatus, please refer to fig. 7, fig. 7 is a schematic structural diagram of a surface wave chip wafer level package apparatus according to an embodiment of the present invention, which includes: the module comprises a first covering module 701, a second covering module 702, an opening module 703, an electrical connection module 704 and a cutting module 705.
The first covering module 701 is used for covering a cavity protection layer on a wafer substrate.
Specifically, a plurality of surface acoustic wave chips are prepared on a wafer substrate; the cavity protection layer does not cover the sound wave filtering function areas of the plurality of surface acoustic wave chips and the pin bonding pads of the plurality of surface acoustic wave chips, and the height of the cavity protection layer is larger than that of the plurality of surface acoustic wave chips.
Specifically, the cavity protection layer is made of a photosensitive material.
The second covering module 702 is used to cover a package top cover on the cavity protection layer.
Specifically, the encapsulation top cover covers the cavity protection layer, the acoustic wave filtering function regions of the multiple acoustic surface wave chips, and the pin pads of the multiple acoustic surface wave chips at the same time.
Specifically, the package top cover is an organic board package top cover, an organic film package top cover, a ceramic board package top cover, a glass board package top cover, a metal board package top cover, or a composite board package top cover.
The opening module 703 opens a plurality of through holes on the top cover of the package.
Specifically, the positions of the plurality of through holes respectively correspond to right above the plurality of pin pads.
The electrical connection module 704 is used to electrically connect each via with its corresponding pin pad.
Specifically, the through holes are filled by heating, curing or reflowing a conductive material or by electroplating metal, so that the conductive material or the electroplated metal of the through holes is in contact with the pin pads, and each through hole is electrically connected with the corresponding pin pad.
The cutting module 705 is configured to cut the wafer substrate to obtain a plurality of packaged components including a single surface acoustic wave chip.
According to the embodiment of the invention, a first covering module 701 is used for covering a cavity protection layer on a wafer substrate containing a plurality of surface acoustic wave chips, a second covering module 702 is used for covering a packaging top cover on the cavity protection layer, a plurality of through holes are formed in the packaging top cover through a hole opening module 703, each through hole is electrically connected with a corresponding pin pad through an electric connection module 704, and finally the wafer substrate is cut through a cutting module 705 to obtain a plurality of packaging components containing single surface acoustic wave chips. By the device, the following steps are not needed like the traditional chip packaging method: the multiple chips are respectively pasted on the ceramic substrate one by one and then packaged, so that the step of pasting is omitted, and the process flow is simplified; meanwhile, the packaging of a plurality of surface acoustic wave chips can be realized at one time, the chip packaging efficiency is improved, and the chip packaging cost is reduced.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (9)
1. A wafer-level packaging method of a surface acoustic wave chip is characterized by comprising the following steps:
covering a cavity protection layer on the wafer substrate; the wafer substrate is provided with a plurality of surface acoustic wave chips; the cavity protection layer does not cover the sound wave filtering function areas of the multiple surface acoustic wave chips and the pin bonding pads of the multiple surface acoustic wave chips, and the height of the cavity protection layer is larger than that of the multiple surface acoustic wave chips;
covering a packaging top cover on the cavity protection layer, so that the packaging top cover covers the cavity protection layer, the sound wave filtering function areas of the multiple surface acoustic wave chips and the pin bonding pads of the multiple surface acoustic wave chips at the same time;
forming a plurality of through holes on the packaging top cover, wherein the positions of the through holes respectively correspond to the positions right above the pin bonding pads;
electrically connecting each through hole with the corresponding pin bonding pad;
and cutting the wafer substrate to obtain a plurality of packaging components containing single surface acoustic wave chips.
2. The wafer-level packaging method for surface acoustic wave chips as claimed in claim 1, wherein said electrically connecting each through hole with its corresponding pin pad specifically comprises:
the through holes are filled in a heating curing or reflow mode of a conductive material or a metal plating mode, so that the through holes are in contact with the pin pads through the conductive material or the metal plating, and each through hole is electrically connected with the corresponding pin pad.
3. The wafer-level packaging method for the surface acoustic wave chip as claimed in claim 1, wherein a packaging top cover is covered on the cavity protection layer, specifically: the packaging top cover covers the cavity protective layer in a mode of mutually bonding with the cavity protective layer.
4. The wafer-level packaging method for SAW chips as claimed in claim 1 or 2, wherein said packaging cap is an organic board packaging cap, an organic film packaging cap, a ceramic board packaging cap, a glass board packaging cap, a metal board packaging cap or a composite board packaging cap.
5. The wafer-level packaging method for the SAW chip as claimed in claim 1 or 2, wherein the cavity protection layer is made of photosensitive material.
6. A wafer level packaging apparatus of a surface acoustic wave chip is characterized by comprising: the cutting device comprises a first covering module, a second covering module, a hole opening module, an electrical connection module and a cutting module;
the first covering module is used for covering a cavity protection layer on the wafer substrate; the wafer substrate is provided with a plurality of surface acoustic wave chips; the cavity protection layer does not cover the sound wave filtering function areas of the multiple surface acoustic wave chips and the pin bonding pads of the multiple surface acoustic wave chips, and the height of the cavity protection layer is larger than that of the multiple surface acoustic wave chips;
the second covering module is used for covering a packaging top cover on the cavity protection layer, so that the packaging top cover covers the cavity protection layer, the sound wave filtering function areas of the multiple surface acoustic wave chips and the pin bonding pads of the multiple surface acoustic wave chips at the same time;
the hole opening module is used for forming a plurality of through holes on the packaging top cover, and the positions of the through holes respectively correspond to the positions right above the pin bonding pads;
the electrical connection module is used for electrically connecting each through hole with the corresponding pin bonding pad;
the cutting module is used for cutting the wafer substrate to obtain a plurality of packaging components containing single surface acoustic wave chips.
7. The wafer-level package device for surface acoustic wave chips of claim 6, wherein the electrical connection module is configured to electrically connect each through hole with its corresponding pin pad, specifically:
the through holes are filled in a heating curing or reflow mode of a conductive material or a metal plating mode, so that the through holes are in contact with the pin pads through the conductive material or the metal plating, and each through hole is electrically connected with the corresponding pin pad.
8. The wafer-level package for saw chips as claimed in claim 6 or 7, wherein said package top cover is an organic board package top cover, an organic film package top cover, a ceramic board package top cover, a glass board package top cover, a metal board package top cover or a composite board package top cover.
9. The wafer-level package device for saw chips as claimed in claim 6 or 7, wherein the cavity protection layer is made of photosensitive material.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011621779.0A CN112769411A (en) | 2020-12-30 | 2020-12-30 | Wafer-level packaging method and device for surface acoustic wave chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011621779.0A CN112769411A (en) | 2020-12-30 | 2020-12-30 | Wafer-level packaging method and device for surface acoustic wave chip |
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| CN202011621779.0A Pending CN112769411A (en) | 2020-12-30 | 2020-12-30 | Wafer-level packaging method and device for surface acoustic wave chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114079000A (en) * | 2022-01-19 | 2022-02-22 | 深圳新声半导体有限公司 | Packaging system of SAW filter |
| CN117013974A (en) * | 2023-10-08 | 2023-11-07 | 深圳新声半导体有限公司 | Wafer-level packaging method of BAW filter |
| CN117118384A (en) * | 2023-10-23 | 2023-11-24 | 北京超材信息科技有限公司 | Acoustic wave element, acoustic wave filter and radio frequency module |
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| CN109286385A (en) * | 2018-09-13 | 2019-01-29 | 中国电子科技集团公司第二十六研究所 | A kind of SAW device wafer level packaging structure and its packaging method |
| CN110649909A (en) * | 2019-09-30 | 2020-01-03 | 中国电子科技集团公司第二十六研究所 | Surface acoustic wave filter device wafer level packaging method and structure thereof |
| CN110943710A (en) * | 2019-11-18 | 2020-03-31 | 王之奇 | Filter chip packaging structure and wafer level packaging method thereof |
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| CN107919862A (en) * | 2017-12-28 | 2018-04-17 | 中国电子科技集团公司第二十六研究所 | Surface acoustic wave device air tightness wafer level packaging structure and process |
| CN109286385A (en) * | 2018-09-13 | 2019-01-29 | 中国电子科技集团公司第二十六研究所 | A kind of SAW device wafer level packaging structure and its packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114079000A (en) * | 2022-01-19 | 2022-02-22 | 深圳新声半导体有限公司 | Packaging system of SAW filter |
| CN117013974A (en) * | 2023-10-08 | 2023-11-07 | 深圳新声半导体有限公司 | Wafer-level packaging method of BAW filter |
| CN117013974B (en) * | 2023-10-08 | 2024-01-30 | 深圳新声半导体有限公司 | Wafer-level packaging method of BAW filter |
| CN117118384A (en) * | 2023-10-23 | 2023-11-24 | 北京超材信息科技有限公司 | Acoustic wave element, acoustic wave filter and radio frequency module |
| CN117118384B (en) * | 2023-10-23 | 2024-03-22 | 北京超材信息科技有限公司 | Acoustic wave element, acoustic wave filter and radio frequency module |
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