KR20010016808A - Capacitor in a semiconductor device and method of manufacturing thereof - Google Patents

Capacitor in a semiconductor device and method of manufacturing thereof Download PDF

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KR20010016808A
KR20010016808A KR1019990031946A KR19990031946A KR20010016808A KR 20010016808 A KR20010016808 A KR 20010016808A KR 1019990031946 A KR1019990031946 A KR 1019990031946A KR 19990031946 A KR19990031946 A KR 19990031946A KR 20010016808 A KR20010016808 A KR 20010016808A
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high dielectric
semiconductor device
capacitor
layer
dielectric film
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KR1019990031946A
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Korean (ko)
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홍권
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박종섭
현대전자산업 주식회사
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Publication of KR20010016808A publication Critical patent/KR20010016808A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to guarantee a dielectric characteristic, by forming a storage electrode with a material having the same chemical structure as a high dielectric material, so that a lattice mismatch occurs on an interface between the storage electrode and a high dielectric layer. CONSTITUTION: A semiconductor substrate(1) is prepared which has a contact hole in an interlayer dielectric(2). A contact plug(3) is formed inside the contact hole. A Ti layer(4), a barrier metal layer(5) and an oxide superconductor layer(6) are sequentially formed on the entire structure having the contact plug, and are patterned to form a storage electrode(10) connected to the contact plug. A high dielectric layer(20) and a plate electrode(30) are formed on the entire structure having the storage electrode.

Description

반도체 소자의 캐패시터 및 그 제조 방법{Capacitor in a semiconductor device and method of manufacturing thereof}Capacitor in semiconductor device and method for manufacturing thereof

본 발명은 반도체 소자의 캐패시터 및 그 제조 방법에 관한 것으로, 특히 BST, SBT, PZT와 같은 고유전체를 적용하는 반도체 소자의 캐패시터 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same, and more particularly to a capacitor of a semiconductor device to which a high dielectric material such as BST, SBT, and PZT is applied, and a method of manufacturing the same.

일반적으로, DRAM용 고유전체 BST 캐패시터, FeRAM용 SBT 캐패시터, FeRAM용 PZT 캐패시터 등과 같은 고유전체 캐패시터는 Pt, Ir, Ru 등과 같은 귀금속류를 사용하여 상부 전극 및 하부 전극을 형성한다. 이러한 귀금속류는 헥사고날 (hexagonal) 구조 및 테트라고날 (tetragonal) 구조를 이루고 있는 반면, BST, SBT, PZT와 같은 고유전체는 페로프스카이트 구조를 이루고 있다. 이러한 화학 구조 차이로 인하여 하부 전극상에 증착되는 고유전체막은 증착 초기에 하부 전극의 구조에 영향을 받아 하부 전극과 고유전체막과의 계면에서 격자 부조화 (lattice mismatch)가 일어나 본질적인 유전 특성을 확보할 수 없다.In general, high-k dielectric capacitors such as high-k dielectric BST capacitors for DRAM, SBT capacitors for FeRAM, PZT capacitors for FeRAM, and the like form upper and lower electrodes using precious metals such as Pt, Ir, and Ru. These precious metals have a hexagonal structure and a tetragonal structure, while high dielectric materials such as BST, SBT, and PZT form a perovskite structure. Due to this chemical structure difference, the high dielectric film deposited on the lower electrode is affected by the structure of the lower electrode at the initial stage of deposition, and lattice mismatch occurs at the interface between the lower electrode and the high dielectric film, thereby obtaining essential dielectric properties. Can't.

최근, 반도체 소자가 고집적화 및 소형화되어 감에 따라 디자인 룰이 감소되고, 이에 따라 캐패시터가 차지하는 면적 또한 줄어들게 된다. 면적이 줄어듦에도 불구하고 소자 동작에 필요한 캐패시터의 정전 용량은 확보되어야 한다. 특히, DRAM용 고유전체 BST 캐패시터는, 소자 동작에 필요한 정전 용량을 확보하기 위해, 귀금속류로 3차원 구조의 하부 전극을 형성하고, 이러한 3차원 구조의 하부 전극상에 고유전체를 이용한 화학기상증착법으로 200 내지 500Å 두께의 고유전체막을 형성하고, 고유전체막상에 귀금속류로 상부 전극을 형성하여 이루어진다. 그런데, 하부 전극과 고유전체막과의 계면에 발생되는 격자 부조화는 고유전체막의 두께가 얇아질수록 유전 특성에 미치는 영향이 상대적으로 커져 충분한 정전 용량을 확보할 수 없게 할 뿐만 아니라 누설 전류의 특성 저하를 초래하게 된다.Recently, as semiconductor devices are highly integrated and miniaturized, design rules are reduced, and thus the area occupied by capacitors is also reduced. Although the area is reduced, the capacitance of the capacitor required for device operation must be ensured. In particular, in order to secure the capacitance required for device operation, a high dielectric BST capacitor for DRAM forms a lower electrode having a three-dimensional structure with precious metals, and a chemical vapor deposition method using a high dielectric material on the lower electrode having such a three-dimensional structure. A high dielectric film having a thickness of 200 to 500 을 is formed, and an upper electrode is formed of precious metals on the high dielectric film. However, the lattice mismatch generated at the interface between the lower electrode and the high dielectric film has a relatively large effect on the dielectric properties as the thickness of the high dielectric film becomes thinner, which makes it impossible to secure sufficient capacitance and degrades the leakage current characteristics. Will result.

상기한 바와 같이, 귀금속류를 캐패시터의 전극으로 사용하고, 고유전체를 캐패시터의 유전체막으로 사용하는 고유전체 캐패시터는 일반적인 캐패시터보다 정전 용량 확보라는 측면에서 유리하지만, 하부 전극과 고유전체막과의 계면에 발생되는 격자 부조화로 인해 반도체 소자의 고집적화 및 소형화 실현에 한계가 있다.As described above, the high-k dielectric capacitor using noble metals as the electrode of the capacitor and the high-k dielectric as the dielectric film of the capacitor is advantageous in terms of securing the capacitance than the general capacitor, but at the interface between the lower electrode and the high-k dielectric film. Due to the lattice mismatch generated, there is a limit in realizing high integration and miniaturization of semiconductor devices.

따라서, 본 발명은 하부 전극과 고유전체막과의 계면에 격자 부조화가 일어나지 않도록 하여, 상기한 문제점을 해결할 수 있는 반도체 소자의 캐패시터 및 그 제조 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a capacitor of a semiconductor device and a method of manufacturing the same, which can solve the above problems by preventing lattice mismatch at an interface between a lower electrode and a high dielectric film.

이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 캐패시터 제조 방법은 층간 절연막에 콘택 홀이 형성된 반도체 기판이 제공되는 단계; 상기 콘택 홀 내부에 콘택 플러그를 형성하는 단계; 상기 콘택 플러그를 포함한 전체 구조상에 Ti 층, 베리어 메탈층 및 산화물 초전도체층을 순차적으로 형성한 후, 이 층들을 패터닝하여 상기 콘택 플러그와 연결되는 하부 전극을 형성하는 단계; 및 상기 하부 전극을 포함한 전체 구조상에 고유전체막 및 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.A method of manufacturing a capacitor of a semiconductor device of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate having a contact hole formed in the interlayer insulating film; Forming a contact plug in the contact hole; Sequentially forming a Ti layer, a barrier metal layer, and an oxide superconductor layer on the entire structure including the contact plug, and patterning the layers to form a lower electrode connected to the contact plug; And forming a high dielectric film and an upper electrode on the entire structure including the lower electrode.

또한, 본 발명의 캐패시터는 산화물 초전도체 물질로 형성된 하부 전극; 고유전체 물질로 상기 하부 전극상에 형성된 고유전체막; 및 귀금속류로 상기 고유전체막상에 형성된 상부 전극을 포함하여 구성된 것을 특징으로 한다.In addition, the capacitor of the present invention includes a lower electrode formed of an oxide superconductor material; A high dielectric film formed on the lower electrode with a high dielectric material; And an upper electrode formed of the noble metal on the high dielectric film.

도 1a 내지 1d는 본 발명의 실시 예에 따른 반도체 소자의 캐패시터 및 그 제조 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a capacitor and a method of manufacturing the same according to an embodiment of the present invention.

〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1: 반도체 기판 2: 층간 절연막1: semiconductor substrate 2: interlayer insulating film

3: 콘택 플러그 4: Ti 층3: contact plug 4: Ti layer

5: 베리어 메탈층 6: 산화물 초전도체층5: Barrier Metal Layer 6: Oxide Superconductor Layer

10: 하부 전극 20: 고유전체막10: lower electrode 20: high dielectric film

30: 상부전극30: upper electrode

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 1d는 본 발명의 실시 예에 따른 반도체 소자의 캐패시터 및 그 제조 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for describing a capacitor and a method of manufacturing the semiconductor device according to the embodiment of the present invention.

도 1a를 참조하며, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(1)이 제공되고, 이 반도체 기판(1)상에 층간 절연막(2)을 형성한다. 층간 절연막(2)의 일부분을 식각하여 콘택 홀을 형성한 후, 콘택 홀 내부에 콘택 플러그(3)를 형성한다.Referring to FIG. 1A, a semiconductor substrate 1 having various elements for forming a semiconductor element is provided, and an interlayer insulating film 2 is formed on the semiconductor substrate 1. A portion of the interlayer insulating film 2 is etched to form a contact hole, and then a contact plug 3 is formed inside the contact hole.

상기에서, 콘택 플러그(3)는 도프트 다결정 실리콘을 화학기상증착법 (CVD)으로 500 내지 3000Å 두께로 증착하여 콘택 홀을 충분히 매립되도록 한 후, 화학적 기계적 연마 (CMP) 공정을 실시하여 도프트 다결정 실리콘이 콘택 홀 내에만 남도록 하여 형성된다.In the above, the contact plug 3 deposits the doped polycrystalline silicon to a thickness of 500 to 3000 mm by chemical vapor deposition (CVD) to sufficiently fill the contact holes, and then performs a chemical mechanical polishing (CMP) process to perform the doped polycrystalline. Silicon is formed so as to remain only in the contact hole.

도 1b를 참조하면, 콘택 플러그(3)를 포함한 전체 구조상에 Ti 층(4), 베리어 메탈층(5) 및 산화물 초전도체층(6)을 순차적으로 형성한다.Referring to FIG. 1B, the Ti layer 4, the barrier metal layer 5, and the oxide superconductor layer 6 are sequentially formed on the entire structure including the contact plug 3.

상기에서, Ti 층(4)은 하부층인 콘택 플러그(3)와 상부층인 산화물 초전도체층(6)과의 접촉을 강화시켜 콘택 저항을 낮추는 역할을 한다. 베리어 메탈층(5)은 TiSiN, TiAlN, TaSiN 및 TaAlN 중 어느 한 물질을 물리기상증착법 (PVD)이나 화학기상증착법 (CVD)으로 300 내지 1000Å 두께로 증착하여 형성되며, 하부층인 콘택 플러그(3)와 상부층인 산화물 초전도체층(6)과의 사이에서 이온이 확산되는 것을 방지하는 역할을 한다. 산화물 초전도체층(6)은 CaRuO3, LaSrCoO3, LaSrMnO3, SrRuO3, SrRuO4, YBa2Cu3Ox 등과 같은 페로프스카이트 구조를 갖으면서 전도성이 우수한 물질 중 어느 한 물질을 물리기상증착법이나 화학기상증착법으로 1000 내지 3000Å 두께로 증착하여 형성된다.In the above, the Ti layer 4 serves to lower the contact resistance by strengthening contact between the contact plug 3 as the lower layer and the oxide superconductor layer 6 as the upper layer. The barrier metal layer 5 is formed by depositing any one of TiSiN, TiAlN, TaSiN, and TaAlN to a thickness of 300 to 1000 mm by physical vapor deposition (PVD) or chemical vapor deposition (CVD), and the contact plug 3 as a lower layer. And the diffusion of ions between the oxide superconductor layer 6 as the upper layer. An oxide superconducting layer 6 CaRuO 3, LaSrCoO 3, LaSrMnO 3 , SrRuO 3, SrRuO 4, YBa 2 Cu 3 Ox page rope sky while gateu the tree structure body to which a material of high conductivity material vapor deposition, such as or It is formed by depositing a thickness of 1000 to 3000Å by chemical vapor deposition.

도 1c를 참조하면, 포토마스크 공정 및 건식 식각 공정을 실시하여 산화물 초전도체층(6), 메탈 베리어층(5) 및 Ti 층(4)을 순차적으로 식각하고, 이로 인하여 콘택 플러그(3)와 연결되는 Ti 층(4), 메탈 베리어층(5) 및 산화물 초전도체층(6)이 적층된 구조의 하부 전극(10)이 형성된다.Referring to FIG. 1C, the oxide superconductor layer 6, the metal barrier layer 5, and the Ti layer 4 are sequentially etched by performing a photomask process and a dry etching process, thereby connecting with the contact plug 3. A lower electrode 10 having a structure in which a Ti layer 4, a metal barrier layer 5, and an oxide superconductor layer 6 are stacked is formed.

상기에서, 하부 전극(10)을 형성하기 위한 건식 식각 공정시 하드 마스크 (Hard mask)로 TiN 또는 SiO2를 사용할 수 있다.In the above, TiN or SiO 2 may be used as a hard mask in a dry etching process for forming the lower electrode 10.

도 1d를 참조하면, 하부 전극(10)을 포함한 전체 구조상에 고유전체막(20)을 형성하고, 고유전체막(20)상에 상부 전극(30)을 형성하여 본 발명의 고유전체 캐패시터가 완성된다.Referring to FIG. 1D, the high dielectric film 20 is formed on the entire structure including the lower electrode 10, and the upper electrode 30 is formed on the high dielectric film 20 to complete the high dielectric capacitor of the present invention. do.

상기에서, 고유전체막(20)은 BST, SBT 및 PZT와 같은 페로프스카이트 구조를 갖는 고유전체 물질 중 어느 하나를 300 내지 500Å 두께로 증착하여 형성된다. 이러한 고유전체 물질을 적용하는 고유전체 캐패시터는 DRAM용 고유전체 BST 캐패시터, FeRAM용 SBT 캐패시터, FeRAM용 PZT 캐패시터 등이 있다. 고유전체 캐패시터의 상부 전극(30)은 다양한 전도성 물질을 사용하여 형성할 수 있는데, 최근 추세는 Pt, Ir, Ru 등과 같은 귀금속류를 500 내지 2000Å 두께로 증착하여 형성하며, 하부 전극(10)에 적용된 산화물 초전도체를 사용하여 형성할 수도 있다.In the above, the high-k dielectric film 20 is formed by depositing any one of the high-k dielectric material having a perovskite structure such as BST, SBT and PZT to a thickness of 300 to 500Å. The high-k dielectric capacitors applying such high-k dielectric materials include high-k dielectric BST capacitors for DRAM, SBT capacitors for FeRAM, and PZT capacitors for FeRAM. The upper electrode 30 of the high-k dielectric capacitor may be formed using various conductive materials. A recent trend is formed by depositing noble metals such as Pt, Ir, Ru, etc. to a thickness of 500 to 2000Å, and applied to the lower electrode 10. It can also be formed using an oxide superconductor.

전술한 본 발명의 실시 예에 따른 방법으로 제조된 고유전체 캐패시터는 Ti 층(4), 베리어 메탈층(5) 및 산화물 초전도체층(6)이 적층된 하부 전극(10)과, BST, SBT, PZT와 같은 고유전체 물질로 형성된 고유전체막(20)과, 귀금속류, 산화물 초전도체 물질 및 기타 전도성 물질중 어느 하나로 형성된 상부 전극(30)으로 구성된다. 여기서 중요한 것은 하부 전극(10)과 고유전체막(20)과의 계면에 격자 부조화가 일어나는 것을 방지하기 위하여, 고유전체막(20)에 적용되는 고유전체 물질과 같은 화학 구조를 갖는 물질로 하부 전극(10)을 형성해야 한다는 것이다. 따라서, 고유전체막(20)에 적용되는 BST, SBT, PZT와 같은 고유전체 물질은 페로프스카이트 구조를 이루고 있기 때문에, 이러한 화학 구조를 갖으면서 전도성이 우수한 CaRuO3, LaSrCoO3, LaSrMnO3, SrRuO3, SrRuO4, YBa2Cu3Ox 등과 같은 산화물 초전도체 물질로 하부 전극(10)을 형성한다.The high-k dielectric capacitor manufactured by the method according to the embodiment of the present invention described above includes a lower electrode 10 having a Ti layer 4, a barrier metal layer 5, and an oxide superconductor layer 6 stacked thereon, BST, SBT, A high dielectric film 20 formed of a high dielectric material such as PZT, and an upper electrode 30 formed of any one of noble metals, oxide superconductor materials, and other conductive materials. In this case, in order to prevent lattice mismatch at the interface between the lower electrode 10 and the high dielectric film 20, the lower electrode is a material having the same chemical structure as the high dielectric material applied to the high dielectric film 20. (10) should be formed. Therefore, since the high dielectric materials such as BST, SBT, and PZT applied to the high dielectric film 20 have a perovskite structure, they have CaCuO 3 , LaSrCoO 3 , LaSrMnO 3 , The lower electrode 10 is formed of an oxide superconductor material such as SrRuO 3 , SrRuO 4 , YBa 2 Cu 3 Ox, or the like.

상술한 바와 같이, 본 발명은 고유전체 캐패시터를 제조함에 있어, 고유전체막이 형성될 하부 전극을 고유전체 물질과 같은 화학 구조를 갖는 물질로 형성하므로써, 하부 전극과 고유전체막과의 계면에 격자 조화가 일어나 본질적인 유전 특성을 확보할 수 있어, 캐패시터의 특성을 향상시킬 수 있을 뿐만 아니라, 고유전체막을 300Å 이하의 얇은 두께로 형성하더라도 고집적 메모리 반도체의 캐패시터 특성을 쉽게 확보할 수 있고, 누설 전류 특성이 우수한 캐패시터의 제조를 실현할 수 있다.As described above, in the present invention, in manufacturing a high dielectric capacitor, the lower electrode on which the high dielectric film is to be formed is formed of a material having the same chemical structure as that of the high dielectric material, thereby lattice matching to the interface between the lower electrode and the high dielectric film. Inherent dielectric properties can be obtained, and the characteristics of the capacitor can be improved, and even when the high dielectric film is formed to a thin thickness of 300 Å or less, the capacitor characteristics of the highly integrated memory semiconductor can be easily obtained, and the leakage current characteristics are The production of excellent capacitors can be realized.

Claims (11)

층간 절연막에 콘택 홀이 형성된 반도체 기판이 제공되는 단계;Providing a semiconductor substrate having contact holes formed in the interlayer insulating film; 상기 콘택 홀 내부에 콘택 플러그를 형성하는 단계;Forming a contact plug in the contact hole; 상기 콘택 플러그를 포함한 전체 구조상에 Ti 층, 베리어 메탈층 및 산화물 초전도체층을 순차적으로 형성한 후, 이 층들을 패터닝하여 상기 콘택 플러그와 연결되는 하부 전극을 형성하는 단계; 및Sequentially forming a Ti layer, a barrier metal layer, and an oxide superconductor layer on the entire structure including the contact plug, and patterning the layers to form a lower electrode connected to the contact plug; And 상기 하부 전극을 포함한 전체 구조상에 고유전체막 및 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.And forming a high dielectric film and an upper electrode on the entire structure including the lower electrode. 제 1 항에 있어서,The method of claim 1, 상기 베리어 메탈층은 TiSiN, TiAlN, TaSiN 및 TaAlN 중 어느 한 물질을 증착하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The barrier metal layer is a capacitor manufacturing method of a semiconductor device, characterized in that formed by depositing any one of TiSiN, TiAlN, TaSiN and TaAlN material. 제 1 항에 있어서,The method of claim 1, 상기 산화물 초전도체층은 CaRuO3, LaSrCoO3, LaSrMnO3, SrRuO3, SrRuO4및 YBa2Cu3Ox 와 같은 페로프스카이트 구조를 갖는 물질 중 어느 한 물질을 증착하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.It said oxide superconductor layer is a semiconductor device, characterized in that formed by CaRuO 3, LaSrCoO 3, LaSrMnO 3 , SrRuO 3, SrRuO 4 and YBa 2 Fe rope such as Cu 3 Ox deposition of any one material selected from the group consisting of a material having a Sky bit structure Capacitor manufacturing method. 제 1 항에 있어서,The method of claim 1, 상기 고유전체막은 BST, SBT 및 PZT와 같은 페로프스카이트 구조를 갖는 물질 중 어느 한 물질을 증착하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The high dielectric film is a capacitor manufacturing method of a semiconductor device, characterized in that formed by depositing any one material having a perovskite structure such as BST, SBT and PZT. 제 1 항에 있어서,The method of claim 1, 상기 상부 전극은 Pt, Ir 및 Ru 와 같은 귀금속류나 산화물 초전도체를 사용하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The upper electrode is a capacitor manufacturing method of a semiconductor device, characterized in that formed using noble metals such as Pt, Ir and Ru or oxide superconductor. 제 1 항에 있어서,The method of claim 1, 상기 패터닝 공정은 하드 마스크로서 TiN이나 SiO2를 사용하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The patterning process is a capacitor manufacturing method of a semiconductor device, characterized in that using a TiN or SiO 2 as a hard mask. 산화물 초전도체 물질로 형성된 하부 전극;A bottom electrode formed of an oxide superconductor material; 고유전체 물질로 상기 하부 전극상에 형성된 고유전체막; 및A high dielectric film formed on the lower electrode with a high dielectric material; And 귀금속류로 상기 고유전체막상에 형성된 상부 전극을 포함하여 구성된 것을 특징으로 하는 반도체 소자의 캐패시터.A capacitor of a semiconductor device comprising a top electrode formed of the noble metal on the high dielectric film. 제 7 항에 있어서,The method of claim 7, wherein 상기 산화물 초전도체 물질과 상기 고유전체 물질은 유사한 화학 구조를 갖는 것을 특징으로 하는 반도체 소자의 캐패시터.And the oxide superconductor material and the high dielectric material have a similar chemical structure. 제 7 항에 있어서,The method of claim 7, wherein 상기 하부 전극은 CaRuO3, LaSrCoO3, LaSrMnO3, SrRuO3, SrRuO4및 YBa2Cu3Ox 와 같은 페로프스카이트 구조를 갖는 산화물 초전도체 물질 중 어느 한 물질을 증착하여 형성된 것을 특징으로 하는 반도체 소자의 캐패시터.Wherein the lower electrode is a semiconductor device, characterized in that formed CaRuO 3, LaSrCoO 3, LaSrMnO 3 , SrRuO 3, SrRuO 4 and YBa 2 Fe rope such as Cu 3 Ox deposition of any one material selected from the group consisting of an oxide superconducting material having a Sky bit structure Capacitors. 제 7 항에 있어서,The method of claim 7, wherein 상기 고유전체막은 BST, SBT 및 PZT와 같은 페로프스카이트 구조를 갖는 고유전체 물질 중 어느 한 물질을 증착하여 형성된 것을 특징으로 하는 반도체 소자의 캐패시터.The high dielectric film capacitor of the semiconductor device, characterized in that formed by depositing any one of the high dielectric material having a perovskite structure, such as BST, SBT and PZT. 제 7 항에 있어서,The method of claim 7, wherein 상기 상부 전극은 Pt, Ir 및 Ru 와 같은 귀금속류중 어느 하나를 증착하여 형성된 것을 특징으로 하는 반도체 소자의 캐패시터.The upper electrode is a capacitor of the semiconductor device, characterized in that formed by depositing any one of the precious metals such as Pt, Ir and Ru.
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