KR20010004598A - method of forming gate for semiconductor device - Google Patents

method of forming gate for semiconductor device Download PDF

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Publication number
KR20010004598A
KR20010004598A KR1019990025292A KR19990025292A KR20010004598A KR 20010004598 A KR20010004598 A KR 20010004598A KR 1019990025292 A KR1019990025292 A KR 1019990025292A KR 19990025292 A KR19990025292 A KR 19990025292A KR 20010004598 A KR20010004598 A KR 20010004598A
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South Korea
Prior art keywords
film
gate
insulating film
metal film
barrier metal
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KR1019990025292A
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Korean (ko)
Inventor
이성권
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김영환
현대전자산업 주식회사
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Priority to KR1019990025292A priority Critical patent/KR20010004598A/en
Priority to JP2000193495A priority patent/JP2001036083A/en
Publication of KR20010004598A publication Critical patent/KR20010004598A/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28B—SHAPING CLAY OR OTHER CERAMIC COMPOSITIONS; SHAPING SLAG; SHAPING MIXTURES CONTAINING CEMENTITIOUS MATERIAL, e.g. PLASTER
    • B28B3/00—Producing shaped articles from the material by using presses; Presses specially adapted therefor
    • B28B3/02—Producing shaped articles from the material by using presses; Presses specially adapted therefor wherein a ram exerts pressure on the material in a moulding space; Ram heads of special form
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28B—SHAPING CLAY OR OTHER CERAMIC COMPOSITIONS; SHAPING SLAG; SHAPING MIXTURES CONTAINING CEMENTITIOUS MATERIAL, e.g. PLASTER
    • B28B13/00—Feeding the unshaped material to moulds or apparatus for producing shaped articles; Discharging shaped articles from such moulds or apparatus
    • B28B13/04—Discharging the shaped articles
    • B28B13/06—Removing the shaped articles from moulds
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28B—SHAPING CLAY OR OTHER CERAMIC COMPOSITIONS; SHAPING SLAG; SHAPING MIXTURES CONTAINING CEMENTITIOUS MATERIAL, e.g. PLASTER
    • B28B7/00—Moulds; Cores; Mandrels
    • B28B7/0097—Press moulds; Press-mould and press-ram assemblies
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04C—STRUCTURAL ELEMENTS; BUILDING MATERIALS
    • E04C1/00—Building elements of block or other shape for the construction of parts of buildings
    • E04C1/24—Elements for building-up floors, ceilings, roofs, arches, or beams

Abstract

PURPOSE: A gate formation method is provided to be capable of preventing damage of a copper film due to plasma upon etch process, by forming a gate in a copper film using damascene process. CONSTITUTION: A gate insulating film(12) and a polysilicon film are deposited on a semiconductor substrate(10) and are then patterned to form a dummy pattern(13) on a predetermined region for a gate. Source and drain(14A,14B) are formed on both sides of the dummy pattern. The first insulating film(15) is then formed on the dummy pattern and the surface of the substrate. After forming the second insulating film(16) on the first insulating film, the second insulating film and the first insulating film are treated by blanket etch process so that the dummy pattern can be exposed and the exposed dummy pattern is planarized. Next, the dummy pattern is removed to form a trench having a gate shape through which the gate insulating film is exposed. A barrier metal film(17) is formed on the second insulating film and the surface of the trench. A low resistance metal film is formed on the barrier metal film so that the trench in which the barrier metal film is formed can be filled. Thereafter, the low resistance metal film and the barrier metal film are treated by blanket etch process so that the second insulating film can be exposed, thus forming a gate the bottom and the side of which is surrounded by the barrier metal film.

Description

반도체 소자의 게이트 형성방법{method of forming gate for semiconductor device}Method of forming gate for semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 구리와 같은 저저항 금속막을 이용한 반도체 소자의 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate of a semiconductor device using a low resistance metal film such as copper.

반도체 소자의 고집적화에 따라 게이트의 길이가 0.10㎛ 이하로 감소되고 산화막 두께가 50nm 이하로 감소됨에 따라, 문턱전압 변동 및 게이트 산화막 축퇴 (degradation) 및 게이트 저항 증가등과 같은 문제가 야기된다. 이에 대하여, 새로운 게이트 물질로서 저저항을 갖는 구리(Cu)가 제시되었다.As the gate length is reduced to 0.10 μm or less and the oxide thickness is reduced to 50 nm or less with high integration of semiconductor devices, problems such as fluctuations in threshold voltage, gate oxide film degradation, and gate resistance increase are caused. In this regard, copper (Cu) having low resistance has been proposed as a new gate material.

그러가, 상기한 구리는 산소와의 친화력이 크기 때문에 산화분위기에 노출시 쉽게 산화되고, 원자의 크기가 작아서 게이트 산화막 및 기판으로의 침투가 용이할 뿐만 아니라, 게이트 형성을 위한 구리막의 식각시 플라즈마에 손상이 야기되어, 소자의 전기적 특성을 저하시키는 문제가 있다. 이에 따라, 게이트 물질로서 구리를 사용하는 경우에는 재료의 특성상 폴리실리콘과는 다른 공정으로 진행하여야 한다.However, since copper has a high affinity with oxygen, it is easily oxidized when exposed to an oxidizing atmosphere, and because the size of atoms is small, it is easy to penetrate into the gate oxide film and the substrate, and the plasma during etching of the copper film for gate formation. Damage is caused, and there is a problem of lowering the electrical characteristics of the device. Accordingly, when copper is used as the gate material, it is necessary to proceed with a process different from polysilicon due to the properties of the material.

따라서, 본 발명은 게이트 물질로서 구리와 같은 저저항 금속을 사용하면서 소자의 전기적 특성을 저하시키는 것 없이 고집적화를 용이하게 달성할 수 있는 반도체 소자의 게이트 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a gate of a semiconductor device which can easily achieve high integration without lowering the electrical characteristics of the device while using a low resistance metal such as copper as the gate material.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도.1A to 1F are cross-sectional views illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

10 : 반도체 기판 11 : 소자분리막10 semiconductor substrate 11 device isolation film

12 : 게이트 절연막 13 : 더미패턴12 gate insulating film 13 dummy pattern

14A, 14B : 소오스 및 드레인14A, 14B: Source and Drain

15 : 제 1 절연막 16 : 제 2 절연막15: first insulating film 16: second insulating film

17 : 배리어 금속막 18 : 구리막17 barrier metal film 18 copper film

18A : 게이트 100 : 트렌치18A: Gate 100: Trench

상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라, 소자분리막이 형성된 반도체 기판 상에 게이트 절연막 및 폴리실리콘막을 증착하고 패터닝하여, 기판의 게이트 예정영역 상에 더미패턴을 형성한다. 그런 다음, 더미패턴 양 측의 기판에 소오스 및 드레인을 형성하고, 더미 패턴 및 기판의 표면 상에 제 1 절연막을 형성한다. 그 후, 제 1 절연막 상에 제 2 절연막을 형성하고, 제 2 절연막 및 제 1 절연막을 더미패턴이 노출되도록 전면식각하여 표면을 평탄화한 후, 더미패턴을 제거하여 게이트 절연막을 노출시키는 게이트 형태의 트렌치를 형성한다. 그리 고 나서, 트렌치 표면 및 제 2 절연막 상에 배리어 금속막을 형성하고, 배리어 금속막이 형성된 트렌치에 매립되도록 배리어 금속막 상에 저저항 금속막을 형성한 후, 저저항 금속막 및 배리어 금속막을 제 2 절연막이 노출되도록 전면 식각하여 배리어 금속막에 의해 그의 하부 및 측부가 둘러싸인 게이트를 형성한다.In order to achieve the above object of the present invention, according to the present invention, by depositing and patterning a gate insulating film and a polysilicon film on a semiconductor substrate on which the device isolation film is formed, a dummy pattern is formed on the gate predetermined region of the substrate. Then, a source and a drain are formed on the substrates on both sides of the dummy pattern, and a first insulating film is formed on the surface of the dummy pattern and the substrate. Thereafter, a second insulating film is formed on the first insulating film, the surface of the second insulating film and the first insulating film are etched to expose the dummy pattern, and the surface is planarized. Then, the dummy pattern is removed to expose the gate insulating film. Form a trench. Then, a barrier metal film is formed on the trench surface and the second insulating film, and a low resistance metal film is formed on the barrier metal film so as to be embedded in the trench in which the barrier metal film is formed, and then the low resistance metal film and the barrier metal film are formed on the second insulating film. The entire surface is etched so as to be exposed to form a gate surrounded by the barrier metal film at its lower and side portions.

또한, 저저항 금속막은 구리, 플래티늄, 알루미늄, 금 및 은으로 이루어진 그룹으로부터 선택되는 하나의 막, 바람직하게 구리막으로 형성하고, 구리막은 물리기상증착, 화학기상증착 또는 일렉트롤리스 방식으로 형성한다.Further, the low resistance metal film is formed of one film selected from the group consisting of copper, platinum, aluminum, gold and silver, preferably a copper film, and the copper film is formed by physical vapor deposition, chemical vapor deposition or electroless method.

또한, 평탄화를 위한 전면식각 및 저저항 금속막의 전면식각은 화학기계연마로 진행한다.In addition, the front surface etching for planarization and the front surface etching of the low resistance metal film are performed by chemical mechanical polishing.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 구리를 이용한 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도이다.1A to 1F are cross-sectional views illustrating a gate forming method of a semiconductor device using copper according to an embodiment of the present invention.

도 1a를 참조하면, 소자분리막(11)이 형성된 반도체 기판(10) 상에 게이트 절연막(12) 및 폴리실리콘막을 증착하고, 포토리소그라피 및 식각공정으로 패터닝하여, 기판(10)의 게이트 예정영역 상에 더미패턴(13)을 형성한다. 여기서, 소자분리막(11)은 공지된 STI(Shallow Trench Isolation)기술을 이용하여 형성하거나 LOCOS(LOCal Oxidation of Silicon) 기술을 이용하여 형성하고, 게이트 절연막(12)은 SiO2막, TaO5막 또는 SiON막으로 형성한다. 또한, 상기 식각공정은 플라즈마 식각공정으로 형성한다. 그런 다음, 더미패턴(13) 양 측의 기판(10)으로 불순물이온을 주입하여 소오스 및 드레인(14A, 14B)을 형성한다.Referring to FIG. 1A, a gate insulating layer 12 and a polysilicon layer are deposited on a semiconductor substrate 10 on which the device isolation layer 11 is formed, and patterned by photolithography and etching processes to form a gate region of the substrate 10. A dummy pattern 13 is formed in the hole. The device isolation layer 11 may be formed using a well-known shallow trench isolation (STI) technique or may be formed using a LOCOS (LOCal Oxidation of Silicon) technique, and the gate insulating layer 12 may be a SiO 2 layer, a TaO 5 layer, or It is formed of a SiON film. In addition, the etching process is formed by a plasma etching process. Then, impurity ions are implanted into the substrate 10 on both sides of the dummy pattern 13 to form the source and drain 14A and 14B.

도 1b를 참조하면, 더미 패턴(13) 및 기판(10)의 표면 상에 제 1 절연막(15)을 박막으로 형성한다. 바람직하게, 제 1 절연막(15)은 Ta2O5막 또는 SiON막으로 형성한다. 도 1c를 참조하면, 제 1 절연막(15) 상에 제 2 절연막(16)을 증착하고 화학기계연마(Chemical Mechanical Polishing; CMP)로 더미패턴(13)이 노출되도록 제 2 및 제 1 절연막(16, 15)을 전면식각하여 표면을 평탄화시킨다. 바람직하게, 제 2 절연막(16)은 BPSG막, PECVD 산화막 또는 TEOS막으로 형성한다.Referring to FIG. 1B, the first insulating layer 15 is formed as a thin film on the dummy pattern 13 and the surface of the substrate 10. Preferably, the first insulating film 15 is formed of a Ta 2 O 5 film or a SiON film. Referring to FIG. 1C, the second and first insulating layers 16 may be deposited on the first insulating layer 15 so that the dummy pattern 13 is exposed by chemical mechanical polishing (CMP). Planarize the surface by etching the entire surface. Preferably, the second insulating film 16 is formed of a BPSG film, PECVD oxide film or TEOS film.

도 1d를 노출된 더미패턴(13)을 습식식각으로 제거하여 게이트 절연막(12)을 노출시키는 게이트 형태의 트렌치(100)를 형성한다. 도 1e를 참조하면, 트렌치 (100) 표면 및 제 2 절연막(16) 상에 500Å 이하의 두께, 바람직하게 300 내지 500Å의 두께로 배리어 금속막(17)을 형성한다. 여기서, 배리어 금속막(17)은 TiN막, TiW막 또는 WN막으로 형성한다. 그런 다음, 배리어 금속막(17)이 형성된 트렌치(100)에 매립되도록 배리어 금속막(17) 상에 저저항 금속막으로서 구리(Cu), 플래티늄(Pt), 알루미늄(Al), 금(Au) 및 은(Ag)으로 이루어진 그룹으로부터 선택되는 하나의 막, 바람직하게 구리막(18)을 증착한다. 또한, 배리어 금속막(17) 및 구리막(18)은 물리기상증착(Physical Vapor Deposition; PVD), 화학기상증착 (Chemical Vapor Deposition; CVD) 또는 일렉트롤리스(electroless) 방식으로 증착한다.In FIG. 1D, the exposed dummy pattern 13 is removed by wet etching to form a trench 100 having a gate shape exposing the gate insulating layer 12. Referring to FIG. 1E, the barrier metal film 17 is formed on the trench 100 surface and the second insulating film 16 to a thickness of 500 kPa or less, preferably 300 to 500 kPa. The barrier metal film 17 is formed of a TiN film, a TiW film, or a WN film. Then, copper (Cu), platinum (Pt), aluminum (Al), and gold (Au) as low-resistance metal films on the barrier metal film 17 so as to be buried in the trench 100 where the barrier metal film 17 is formed. And one film selected from the group consisting of silver (Ag), preferably a copper film 18. In addition, the barrier metal film 17 and the copper film 18 are deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroless method.

그리고 나서, 도 1f에 도시된 바와 같이, 구리막(18) 및 배리어 금속막(17)을 제 2 절연막(16)이 노출되도록 CMP로 전면식각하여, 배리어 금속막(17)에 의해 그의 하부 및 측부가 둘러싸인 게이트(18A)를 형성한다.Then, as shown in FIG. 1F, the copper film 18 and the barrier metal film 17 are all etched with CMP so that the second insulating film 16 is exposed, so that the lower portion and the lower portion thereof are removed by the barrier metal film 17. The side part forms the gate 18A enclosed.

상기한 본 발명에 의하면, 데머신(damascene) 공정을 이용하여 구리막의 게이트를 형성하기 때문에, 단지 CMP 공정이 요구되므로 식각시 플라즈마에 의한 구리막의 손상이 방지된다.According to the present invention described above, since the gate of the copper film is formed using a damascene process, only a CMP process is required, so that damage to the copper film by plasma during etching is prevented.

또한, 구리막 게이트의 측부 및 저부를 배리어 금속막으로 둘러싸도록 형성함으로써, 구리원자가 게이트 절연막 및 기판으로 침투하는 것이 방지되므로, 소자의 전기적 특성이 향상된다.Further, by forming the side and bottom portions of the copper film gate to surround the barrier metal film, copper atoms are prevented from penetrating into the gate insulating film and the substrate, thereby improving the electrical characteristics of the device.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (13)

소자분리막이 형성된 반도체 기판 상에 게이트 절연막 및 폴리실리콘막을 증착하고 패터닝하여, 상기 기판의 게이트 예정영역 상에 더미패턴을 형성하는 단계;Depositing and patterning a gate insulating film and a polysilicon film on a semiconductor substrate on which the device isolation film is formed, and forming a dummy pattern on a gate predetermined region of the substrate; 상기 더미패턴 양 측의 상기 기판에 소오스 및 드레인을 형성하는 단계;Forming a source and a drain on the substrate on both sides of the dummy pattern; 상기 더미 패턴 및 기판의 표면 상에 제 1 절연막을 형성하는 단계;Forming a first insulating film on a surface of the dummy pattern and the substrate; 상기 제 1 절연막 상에 제 2 절연막을 형성하는 단계;Forming a second insulating film on the first insulating film; 상기 제 2 절연막 및 제 1 절연막을 상기 더미패턴이 노출되도록 전면식각하여 표면을 평탄화하는 단계;Planarizing the surface of the second insulating film and the first insulating film so that the dummy pattern is exposed; 상기 더미패턴을 제거하여 상기 게이트 절연막을 노출시키는 게이트 형태의 트렌치를 형성하는 단계;Forming a gate type trench to expose the gate insulating layer by removing the dummy pattern; 상기 트렌치 표면 및 상기 제 2 절연막 상에 배리어 금속막을 형성하는 단계;Forming a barrier metal film on the trench surface and the second insulating film; 상기 배리어 금속막이 형성된 상기 트렌치에 매립되도록 상기 배리어 금속막 상에 저저항 금속막을 형성하는 단계; 및Forming a low resistance metal film on the barrier metal film so as to fill the trench in which the barrier metal film is formed; And 상기 저저항 금속막 및 배리어 금속막을 상기 제 2 절연막이 노출되도록 전면 식각하여 상기 배리어 금속막에 의해 그의 하부 및 측부가 둘러싸인 게이트를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.And etching the low-resistance metal film and the barrier metal film over the entire surface of the second insulating film so that the second insulating film is exposed to form a gate surrounded by the barrier metal film. 제 1 항에 있어서, 상기 저저항 금속막은 구리, 플래티늄, 알루미늄, 금 및 은으로 이루어진 그룹으로부터 선택되는 하나의 막으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 1, wherein the low resistance metal film is formed of one film selected from the group consisting of copper, platinum, aluminum, gold, and silver. 제 2 항에 있어서, 상기 저저항 금속막은 구리막으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.3. The method of claim 2, wherein the low resistance metal film is formed of a copper film. 제 3 항에 있어서, 상기 구리막은 물리기상증착, 화학기상증착 또는 일렉트롤리스 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 3, wherein the copper film is formed by physical vapor deposition, chemical vapor deposition, or electroless deposition. 제 3 항에 있어서, 상기 게이트를 형성하는 단계에서, 상기 전면식각은 화학기계연마로 진행하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 3, wherein in the forming of the gate, the front surface etching is performed by chemical mechanical polishing. 제 1 항에 있어서, 상기 게이트 절연막은 SiO2막, TaO5막 또는 SiON막으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 1, wherein the gate insulating film is formed of a SiO 2 film, a TaO 5 film, or a SiON film. 제 1 항에 있어서, 상기 제 1 절연막은 Ta2O5막 또는 SiON막으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 1, wherein the first insulating film is formed of a Ta 2 O 5 film or a SiON film. 제 1 항에 있어서, 상기 제 2 절연막은 BPSG막, PECVD 산화막 또는 TEOS막으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 1, wherein the second insulating film is formed of a BPSG film, a PECVD oxide film, or a TEOS film. 제 1 항에 있어서, 상기 평탄화하는 단계에서 상기 전면식각은 화학기계연마로 진행하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 1, wherein the front surface etching is performed by chemical mechanical polishing in the planarization step. 제 1 항에 있어서, 더미패턴을 제거하는 단계는 습식식각으로 진행하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 1, wherein the removing of the dummy pattern is performed by wet etching. 제 1 항에 있어서, 상기 배리어 금속막은 TiN막, TiW막 또는 WN막으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method according to claim 1, wherein the barrier metal film is formed of a TiN film, a TiW film, or a WN film. 제 1 항 또는 제 11 항에 있어서, 상기 배리어 금속막은 500Å 이하의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of forming a gate of a semiconductor device according to claim 1 or 11, wherein the barrier metal film is formed to a thickness of 500 kPa or less. 제 12 항에 있어서, 상기 배리어 금속막은 물리기상증착, 화학기상증착 또는 일렉트롤리스 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성방법.The method of claim 12, wherein the barrier metal film is formed by physical vapor deposition, chemical vapor deposition, or an electroless method.
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KR100349364B1 (en) 2000-11-16 2002-08-21 주식회사 하이닉스반도체 Method for manufacturing gate in semiconductor device
KR100353539B1 (en) 2000-11-24 2002-09-27 주식회사 하이닉스반도체 Method for manufacturing gate in semiconductor device
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KR100380163B1 (en) * 2001-06-29 2003-04-11 주식회사 하이닉스반도체 Method of manufacturing a transistor in a semiconductor device
KR100866113B1 (en) * 2002-06-29 2008-10-31 매그나칩 반도체 유한회사 Method for forming gate in semiconductor device
KR100783989B1 (en) * 2006-06-29 2007-12-07 주식회사 하이닉스반도체 Method for forming metal line in semiconductor device
KR100781888B1 (en) * 2006-12-27 2007-12-05 동부일렉트로닉스 주식회사 Method for fabricating semiconductor device

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