KR20000042485A - Method for forming capacitor of semiconductor device - Google Patents

Method for forming capacitor of semiconductor device Download PDF

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Publication number
KR20000042485A
KR20000042485A KR1019980058652A KR19980058652A KR20000042485A KR 20000042485 A KR20000042485 A KR 20000042485A KR 1019980058652 A KR1019980058652 A KR 1019980058652A KR 19980058652 A KR19980058652 A KR 19980058652A KR 20000042485 A KR20000042485 A KR 20000042485A
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South Korea
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film
forming
capacitor
semiconductor device
tin film
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KR1019980058652A
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Korean (ko)
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김경민
박기선
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김영환
현대전자산업 주식회사
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Publication of KR20000042485A publication Critical patent/KR20000042485A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Abstract

PURPOSE: A method for forming a capacitor of a semiconductor device is provided which improves the electrical characteristics of a capacitor and therefore improves the characteristics and the reliability of the semiconductor device. CONSTITUTION: A method for forming a capacitor improves the electrical characteristics of a capacitor by suppressing the reaction at an interface by preventing the diffusion of Ta or O2 to a polycrystalline silicon layer(15) from a Ta2O5 film(21), by performing plasma processing of a TiN film using O2 or N2O gas, after forming the TiN film of diffusion barrier film on a top of the polycrystalline silicon layer. The polycrystalline silicon layer is used as a bottom electrode and the Ta2O5 film is used as dielectrics.

Description

반도체소자의 캐패시터 형성방법Capacitor Formation Method of Semiconductor Device

본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로서, 특히 캐패시터의 유전체막으로 Ta2O5막을 사용하는 경우 하부전극인 다결정실리콘막 상부에 TiN막을 형성한 다음, 상기 TiN막 표면을 N2O 또는 O2가스로 플라즈마처리하여 막질을 개질함으로써 상기 Ta2O5막에서의 산소 또는 Ta의 확산을 방지하여 계면반응을 억제하여 캐패시터의 전기적 특성을 개선시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor of a semiconductor device. In particular, when a Ta 2 O 5 film is used as a dielectric film of a capacitor, a TiN film is formed on a polysilicon film, which is a lower electrode, and then the surface of the TiN film is N 2 O or Plasma treatment with O 2 gas modifies the film quality to prevent diffusion of oxygen or Ta in the Ta 2 O 5 film, thereby inhibiting interfacial reactions, thereby improving the electrical characteristics of the capacitor and thereby improving the characteristics and reliability of the semiconductor device. It is about how it can be.

최근 반도체소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size.

특히, 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자에서는 캐패시터의 정전용량을 증가시키기 위하여 유전상수가 높은 물질을 유전체막으로 사용하거나, 유전체막의 두께를 얇게하거나 또는 전하저장전극의 표면적을 증가시키는 등의 방법이 있다.In particular, in a DRAM device composed of one MOS transistor and a capacitor, a material having a high dielectric constant is used as the dielectric film, a thickness of the dielectric film is increased, or the surface area of the charge storage electrode is increased to increase the capacitance of the capacitor. There is a way.

도시되어 있지는 않지만, 종래기술에 따른 반도체소자의 캐패시터 제조방법을 살펴보면 다음과 같다.Although not shown, looking at the capacitor manufacturing method of the semiconductor device according to the prior art as follows.

먼저, 반도체기판 상에 소자분리 산화막과 게이트산화막을 형성하고, 게이트전극과 소오스/드레인전극으로 구성되는 모스 전계효과 트랜지스터 및 비트라인을 형성한 후, 상기 구조의 전표면에 층간절연막을 형성한다.First, a device isolation oxide film and a gate oxide film are formed on a semiconductor substrate, a MOS field effect transistor and a bit line including a gate electrode and a source / drain electrode are formed, and then an interlayer insulating film is formed on the entire surface of the structure.

그 다음 상기 소오스/드레인전극 중 전하저장전극 콘택으로 예정되어 있는 부분 상측의 층간절연막을 제거하여 전하저장전극 콘택홀을 형성하고, 상기 콘택홀을 통하여 소오스/드레인전극과 접촉되는 전하저장전극을 다결정실리콘층 패턴으로 형성한다.Next, a charge storage electrode contact hole is formed by removing an interlayer insulating layer on the upper portion of the source / drain electrode, which is intended as a charge storage electrode contact, and a polycrystalline crystal of the charge storage electrode contacting the source / drain electrode through the contact hole. It is formed by a silicon layer pattern.

그 후, 상기 다결정실리콘층 패턴 상부에 산화막-질화막-산화막 구조의 유전체막으로 형성한다.Thereafter, a dielectric film having an oxide film-nitride film-oxide film structure is formed on the polysilicon layer pattern.

다음, 상기 유전체막 상부에 확산방지막 및 플레이트전극을 형성하여 캐패시터를 완성한다.Next, a diffusion barrier layer and a plate electrode are formed on the dielectric layer to complete the capacitor.

상기와 같은 종래기술에 따른 반도체소자의 캐패시터에서 유전체막은 고유전율, 저누설전류밀도, 높은 절연파괴전압 및 상하측 전극과의 안정적인 계면특성 등이 요구되는데, 상기 산화막은 유전상수가 약 3.8 정도이고 질화막은 약 7.2 정도로 비교적 작고, 전극으로 사용되는 다결정실리콘층은 비저항이 800 ∼ 1000μΩ㎝ 정도로 비교적 높아 정전용량이 제한되기 때문에, 산화막-질화막-산화막의 적층구조로된 유전체막 대신에 Ta2O5막과 같은 고유전체막을 사용한다.In the capacitor of the semiconductor device according to the prior art as described above, the dielectric film requires high dielectric constant, low leakage current density, high dielectric breakdown voltage, and stable interfacial characteristics with the upper and lower electrodes. The oxide film has a dielectric constant of about 3.8. Since the nitride film is relatively small at about 7.2 and the polysilicon layer used as an electrode has a relatively high resistivity of about 800 to 1000 μΩcm, and the capacitance is limited, Ta 2 O 5 is used instead of the dielectric film having a laminated structure of oxide film-nitride film-oxide film. A high dielectric film such as a film is used.

소자가 고집적화되어감에 따라 안정된 소자동작을 위해 필요한 셀당 캐패시턴스는 변화가 없지만, 캐패시터의 크기는 점점 줄어들어 30Å 정도의 유효산화막의 두께를 갖는 다결정실리콘층을 하부전극으로 사용하는데 한계에 도달하였기 때문에 하부전극을 금속으로 형성하게 되었다. 그러나, 상기 금속 하부전극과 유전체막인 Ta2O5막의 계면반응 때문에 누설전류가 증가하여 소자에 영향을 미치는 문제점이 있다.As the device is highly integrated, the capacitance per cell required for stable device operation does not change, but the size of the capacitor decreases gradually. The electrode was made of metal. However, the leakage current increases due to the interfacial reaction between the metal lower electrode and the dielectric film Ta 2 O 5 , which affects the device.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 하부전극인 다결정실리콘층 상부에 확산방지막인 TiN막을 형성한 다음, O2또는 N2O가스를 사용하여 상기 TiN막의 표면을 플라즈마처리함으로써 유전체막인 Ta2O5막으로부터 상기 다결정실리콘층으로 Ta 또는 O2가 확산되는 것을 방지하여 계면에서의 반응을 억제함으로써 캐패시터의 전기적 특성을 개선하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, by forming a TiN film as a diffusion barrier layer on the polysilicon layer, which is a lower electrode, and then the plasma surface of the TiN film using O 2 or N 2 O gas to A semiconductor device which improves the electrical characteristics of the capacitor and thereby improves the characteristics and reliability of the capacitor by preventing the diffusion of Ta or O 2 from the Ta 2 O 5 film, which is a film, to the polysilicon layer. It is an object of the present invention to provide a method for forming a capacitor.

도 1 내지 도 4 는 본 발명에 따른 반도체소자의 캐패시터 형성방법을 나타낸 단면도.1 to 4 are cross-sectional views showing a capacitor forming method of a semiconductor device according to the present invention.

<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>

11 : 반도체기판 13 : 층간절연막11 semiconductor substrate 13 interlayer insulating film

15 : 다결정실리콘층 17 : 제1TiN막15 polycrystalline silicon layer 17 first TiN film

19 : TiON 막 21 : Ta2O5막19: TiON membrane 21: Ta 2 O 5 membrane

23 : 제2TiN막23: second TiN film

이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 캐패시터 형성방법은,In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,

소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택홀이 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a storage electrode contact hole on the semiconductor substrate having a predetermined lower structure formed thereon;

상기 층간절연막 상부에 하부전극으로 다결정실리콘층을 형성하는 공정과,Forming a polysilicon layer as a lower electrode on the interlayer insulating film;

상기 다결정실리콘층 상부에 제1TiN막을 형성하는 공정과,Forming a first TiN film on the polycrystalline silicon layer;

상기 제1TiN막 표면을 N2O 또는 O2가스를 사용하여 제1플라즈마처리하는 공정과,Performing a first plasma treatment on the surface of the first TiN film using N 2 O or O 2 gas;

상기 플라즈마처리된 제1TiN막 상부에 유전체막으로 Ta2O5막을 형성하는 공정과,Forming a Ta 2 O 5 film as a dielectric film on the plasma-treated first TiN film;

상기 Ta2O5막을 제2플라즈마처리 및 고온 열처리하는 공정과,A second plasma treatment and a high temperature heat treatment of the Ta 2 O 5 film;

상기 Ta2O5막 상부에 상부전극으로 제2TiN막을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a second TiN film as an upper electrode on the Ta 2 O 5 film.

이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.

도 1 내지 도 4 는 본 발명에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도이다.1 to 4 are cross-sectional views showing a capacitor forming method of a semiconductor device according to the present invention.

먼저, 반도체기판(11)에 소자분리 절연막(도시안됨), 게이트산화막(도시안됨), 게이트전극(도시안됨) 및 비트라인(도시안됨) 등의 하부구조물을 형성한다.First, lower structures such as an isolation layer (not shown), a gate oxide layer (not shown), a gate electrode (not shown), and a bit line (not shown) are formed on the semiconductor substrate 11.

다음, 전체표면에 층간절연막(13)을 형성한다.Next, the interlayer insulating film 13 is formed on the entire surface.

그 다음, 저장전극 콘택마스크를 식각마스크로 이용하여 상기 층간절연막(13)을 식각하여 저장전극 콘택홀(도시안됨)을 형성한다.Next, the interlayer insulating layer 13 is etched using the storage electrode contact mask as an etching mask to form a storage electrode contact hole (not shown).

다음, 상기 층간절연막(13) 상부에 상기 저장전극 콘택홀이 매립되도록 다결정실리콘층(15)을 형성한다.Next, a polysilicon layer 15 is formed on the interlayer insulating layer 13 to fill the storage electrode contact hole.

그 다음, 상기 다결정실리콘층(15) 표면에 형성된 자연산화막(도시안됨)을 제거한다. 상기 자연산화막은 HF 또는 비.오.이.(buffer oxide echant, 이하 BOE 라 함)를 사용하여 제거한다.Next, the natural oxide film (not shown) formed on the surface of the polysilicon layer 15 is removed. The natural oxide film is removed using HF or B. E. (buffer oxide echant, BOE).

다음, 상기 다결정실리콘층(15) 상부에 제1TiN막(17)을 형성한다. 상기 제1TiN막(17)은 확산방지막으로서 400 ∼ 750℃ 온도 및 0.1 ∼ 2torr의 압력하에서 TiCl4가스를 열분해하여 증착한다.Next, a first TiN film 17 is formed on the polysilicon layer 15. The first TiN film 17 is deposited as a diffusion barrier by thermally decomposing TiCl 4 gas at a temperature of 400 to 750 ° C. and a pressure of 0.1 to 2 torr.

그 다음, 상기 제1TiN막(17)의 표면을 N3O 또는 O2가스를 사용하여 제1플라즈마처리하여 TiON막(19)화시킨다.Next, the surface of the first TiN film 17 is subjected to a first plasma treatment using N 3 O or O 2 gas to form a TiON film 19.

상기 제1플라즈마처리공정은 다음과 같이 실시한다.The first plasma treatment step is carried out as follows.

먼저, 챔버내의 압력을 9 ∼ 999 torr로 유지하고, 서브 히터(sub heater)는 100 ∼ 500℃의 온도로 유지한다. 그리고, 알.에프. 파워(radio frequency power, 이하 R.F. 파워 라 함)는 50 ∼ 400 watt로 인가하되, 상기 서브 히터를 접지(ground)로 하고, 샤워 헤드(shower head)를 전극(electrode)으로 한다. 상기 제1플라즈마처리공정은 상기와 같은 조건에서 N3O 농도를 10000 ∼ 200000 ppm으로 하고 1 ∼ 10분간 실시한다.First, the pressure in the chamber is maintained at 9 to 999 torr, and the sub heater is maintained at a temperature of 100 to 500 ° C. And r.f. Power (radio frequency power, hereinafter referred to as RF power) is applied at 50 to 400 watts, with the sub-heater as ground and the shower head as the electrode. In the first plasma treatment step, the concentration of N 3 O is set to 10000 to 200000 ppm under the same conditions as above.

다음, 상기 TiON막(19) 상부에 Ta2O5막(21)을 저압화학기상증착(low presure chemical vapor deposition, 이하 LPCVD 라 함)방법으로 형성한다. 상기 Ta2O5막(21)은 증착할 때 웨이퍼의 온도를 300 ∼ 500℃로 유지하고, 챔버의 압력은 0.1 ∼ 2 torr으로 유지한 다음, 10 ∼ 500sccm의 O2가스와 0.005 ∼ 2cc의 Ta(OC2H5)5를 원료로 사용하여 증착한다.Next, a Ta 2 O 5 film 21 is formed on the TiON film 19 by a low presure chemical vapor deposition (LPCVD) method. When the Ta 2 O 5 film 21 is deposited, the temperature of the wafer is maintained at 300 to 500 ° C., and the pressure of the chamber is maintained at 0.1 to 2 torr, followed by 10 to 500 sccm of O 2 gas and 0.005 to 2 cc. Deposit Ta (OC 2 H 5 ) 5 as a raw material.

한편, 상기 Ta2O5막(21)을 플라즈마 화학기상증착(plasma enhanced chemical vapor deposition, 이하 PECVD 라 함) 방법으로 형성하는 경우, R.F. 파워를 50 ∼ 300watt로 인가한다.On the other hand, when the Ta 2 O 5 film 21 is formed by plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD) method, RF power is applied at 50 to 300 watts.

상기 제1플라즈마처리공정과 Ta2O5막(21)의 형성공정은 인시튜(insitu)방법으로 실시된다.The first plasma treatment step and the step of forming the Ta 2 O 5 film 21 are carried out by an insitu method.

다음, 상기 Ta2O5막(21)은 N2O 플라즈마를 사용하여 300 ∼ 500℃에서 플라즈마 처리한 다음, 750 ∼ 900 ℃에서 급속열산화(rapid thermal oxidation)공정을 실시한다.Next, the Ta 2 O 5 film 21 is plasma treated at 300 to 500 ° C. using N 2 O plasma, and then a rapid thermal oxidation process is performed at 750 to 900 ° C.

다음, 상기 Ta2O5막(21) 상부에 상부전극으로 제2TiN막(23)을 형성하되, 400 ∼ 750℃의 챔버온도 및 0.1 ∼ 2torr의 압력하에서, TiCl4가스 10 ∼ 5000sccm 유량을 사용하여 형성한다.Next, a second TiN film 23 is formed on the Ta 2 O 5 film 21 as an upper electrode, and a TiCl 4 gas 10 to 5000 sccm flow rate is used under a chamber temperature of 400 to 750 ° C. and a pressure of 0.1 to 2 torr. To form.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, Ta2O5막을 유전체막으로 사용하는 캐패시터에서 다결정실리콘층을 하부전극으로 사용하고, 상기 하부전극 상부에 확산방지막으로 TiN막을 형성한 다음, 상기 TiN막의 표면을 N2O가스로 플라즈마처리하여 TiON화시킴으로써 상기 Ta2O5막에서 Ta 또는 O2가 확산되어 상기 다결정실리콘층과 반응하여 누설전류가 발생하는 것을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the capacitor forming method of the semiconductor device according to the present invention, in a capacitor using a Ta 2 O 5 film as a dielectric film, a polysilicon layer is used as a lower electrode, and a TiN film is formed as a diffusion barrier on the lower electrode. Then, the surface of the TiN film is plasma-treated with N 2 O gas to form TiON, thereby preventing Ta or O 2 from diffusing in the Ta 2 O 5 film and reacting with the polycrystalline silicon layer to prevent leakage current. There is an advantage of improving the characteristics and reliability of the semiconductor device.

Claims (11)

소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택홀이 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a storage electrode contact hole on the semiconductor substrate having a predetermined lower structure formed thereon; 상기 층간절연막 상부에 하부전극으로 다결정실리콘층을 형성하는 공정과,Forming a polysilicon layer as a lower electrode on the interlayer insulating film; 상기 다결정실리콘층 상부에 제1TiN막을 형성하는 공정과,Forming a first TiN film on the polycrystalline silicon layer; 상기 제1TiN막 표면을 N2O 또는 O2가스를 사용하여 제1플라즈마처리하는 공정과,Performing a first plasma treatment on the surface of the first TiN film using N 2 O or O 2 gas; 상기 플라즈마처리된 제1TiN막 상부에 유전체막으로 Ta2O5막을 형성하는 공정과,Forming a Ta 2 O 5 film as a dielectric film on the plasma-treated first TiN film; 상기 Ta2O5막을 제2플라즈마처리 및 고온 열처리하는 공정과,A second plasma treatment and a high temperature heat treatment of the Ta 2 O 5 film; 상기 Ta2O5막 상부에 상부전극으로 제2TiN막을 형성하는 공정을 포함하는 반도체소자의 캐패시터 형성방법.And forming a second TiN film as an upper electrode on the Ta 2 O 5 film. 제 1 항에 있어서,The method of claim 1, 상기 제1TiN막은 400 ∼ 750℃ 온도 및 0.1 ∼2torr의 압력하에서 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.And the first TiN film is formed at a temperature of 400 to 750 ° C. and a pressure of 0.1 to 2 torr. 제 1 항에 있어서,The method of claim 1, 상기 제1플라즈마처리 공정은 챔버내의 압력을 9 ∼ 999 torr로, 서브 히터는 300 ∼ 500℃의 온도로 유지하고, R.F. 파워는 100 ∼ 400 watt로 인가하여 실시하는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.In the first plasma treatment process, the pressure in the chamber is maintained at 9 to 999 torr, and the sub heater is maintained at a temperature of 300 to 500 ° C. A method for forming a capacitor of a semiconductor device, characterized in that the power is applied at 100 to 400 watts. 제 1 에 있어서,In the first, 상기 제1플라즈마처리 공정은 N2O 개스의 유량을 20 ∼ 1000 sccm으로 하고 1 ∼ 10분간 실시하는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The method of forming a capacitor of a semiconductor device according to claim 1, wherein the first plasma treatment step is performed at a flow rate of N 2 O gas of 20 to 1000 sccm for 1 to 10 minutes. 제 1 에 있어서,In the first, 상기 Ta2O5막은 PECVD 또는 LPCVD 방법으로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The Ta 2 O 5 film is a capacitor formation method of a semiconductor device, characterized in that formed by PECVD or LPCVD method. 제 5 에 있어서,According to claim 5, 상기 Ta2O5막을 PECVD방법으로 형성할 때 R.F. 파워를 50 ∼ 300watt로 인가하는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.When the Ta 2 O 5 film is formed by PECVD, RF power is applied in a range of 50 to 300 watts. 제 1 에 있어서,In the first, 상기 Ta2O5막은 웨이퍼의 온도를 300 ∼ 500℃로 유지하고, 챔버의 압력은 0.1 ∼ 2 torr으로 유지한 다음, 10 ∼ 500sccm의 O2가스와 0.005 ∼ 2cc의 Ta(OC2H5)5를 원료로 사용하여 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The Ta 2 O 5 film maintains the wafer temperature at 300 to 500 ° C., maintains the chamber pressure at 0.1 to 2 torr, and then 10 to 500 sccm of O 2 gas and 0.005 to 2 cc of Ta (OC 2 H 5 ). A method of forming a capacitor of a semiconductor device, characterized in that formed using 5 as a raw material. 제 1 에 있어서,In the first, 상기 제2플라즈마처리 공정은 300 ∼ 500℃에서 N2O 플라즈마를 사용하여 실시하는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The second plasma treatment step is a capacitor forming method of a semiconductor device, characterized in that carried out using N 2 O plasma at 300 ~ 500 ℃. 제 1 에 있어서,In the first, 상기 열처리공정은 급속열산화공정으로 750 ∼ 900 ℃ 로 실시하는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The heat treatment process is a rapid thermal oxidation process capacitor formation method of a semiconductor device, characterized in that carried out at 750 ~ 900 ℃. 제 1 에 있어서,In the first, 상기 제2TiN막은 400 ∼ 750℃ 및 0.1 ∼ 2 torr압력하에서 10 ∼ 5000sccm의 TiCl4가스를 사용하여 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The second TiN film is formed using a TiCl 4 gas of 10 to 5000 sccm at 400 to 750 ℃ and 0.1 to 2 torr pressure. 제 1 에 있어서,In the first, 상기 제1플라즈마처리공정과 Ta2O5막의 형성공정은 인시튜방법으로 실시하는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.And forming the Ta 2 O 5 film by an in-situ method.
KR1019980058652A 1998-12-24 1998-12-24 Method for forming capacitor of semiconductor device KR20000042485A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801314B1 (en) * 2002-06-29 2008-02-05 주식회사 하이닉스반도체 Method for fabricating capacitor in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801314B1 (en) * 2002-06-29 2008-02-05 주식회사 하이닉스반도체 Method for fabricating capacitor in semiconductor device

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