KR20000042390A - Cmos transistor manufacturing method - Google Patents
Cmos transistor manufacturing method Download PDFInfo
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- KR20000042390A KR20000042390A KR1019980058555A KR19980058555A KR20000042390A KR 20000042390 A KR20000042390 A KR 20000042390A KR 1019980058555 A KR1019980058555 A KR 1019980058555A KR 19980058555 A KR19980058555 A KR 19980058555A KR 20000042390 A KR20000042390 A KR 20000042390A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000001268 conjugating effect Effects 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 14
- 150000004767 nitrides Chemical class 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 분야에 관한 것으로, 특히 이중 폴리 게이트(dual poly gate) 구조를 갖는 CMOS 트랜지스터의 게이트 전극 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method of forming a gate electrode of a CMOS transistor having a dual poly gate structure.
반도체 소자에서 NMOS 트랜지스터와 PMOS 트랜지스터를 형성 할 때 게이트 전극에 도핑된 불순물의 전도형에 따라 트랜지스터의 특성이 큰 차이를 보이게 된다. NMOS, PMOS 모두 N+게이트 전극을 사용할 경우 NMOS는 게이트 전극 바로 밑에 채널(channel) 즉 표면 채널(surface channel)이 형성되는데, 비해 PMOS는 게이트 전극에서 조금 떨어진 곳에 매몰 채널(buried channel)이 형성되어 게이트 전극에 의한 채널의 조절 능력이 떨어지게 된다. 따라서, 매몰 채널이 형성된 PMOS에서는 누설전류가 커지는 문제가 있고 이를 위해서는 NMOS에 비해 PMOS의 게이트 전극을 길게 형성하여야 한다. NMOS, PMOS의 채널을 모두 표면(surface)에 형성하기 위해서는 NMOS 게이트 전극은 N+전도형으로, PMOS 게이트 전극은 P+전도형으로 형성하여야 한다. 이럴 때, PMOS도 NMOS와 마찬가지로 표면에 채널이 형성되어 게이트 전극의 길이를 증가시키지 않을 수 있어 작은 크기의 소자를 형성할 수 있다.When the NMOS transistor and the PMOS transistor are formed in a semiconductor device, the characteristics of the transistor show a big difference according to the conduction type of impurities doped in the gate electrode. When N + gate electrode is used for both NMOS and PMOS, NMOS channel (surface channel) is formed just under the gate electrode, whereas PMOS buried channel is formed at some distance from the gate electrode. The control ability of the channel by the gate electrode is reduced. Therefore, in the PMOS in which the buried channel is formed, there is a problem in that the leakage current increases, and for this purpose, the gate electrode of the PMOS should be formed longer than that of the NMOS. In order to form both NMOS and PMOS channels on the surface, the NMOS gate electrode should be formed of N + conduction type and the PMOS gate electrode should be formed of P + conduction type. In this case, like the NMOS, the PMOS may have a channel formed on the surface thereof, thereby not increasing the length of the gate electrode, thereby forming a small size device.
한편, 도1에 도시한 바와 같이 NMOS와 PMOS의 게이트 전극을 각각 서로 다른 도전형으로 형성하였을 때 발생하는 문제로는 p+게이트 전극(15A)과 n+게이트 전극(15B) 사이에 생기는 PN 접합(junction)이 있다. 이는 p+에서 n+로 전하가 이동할 때 전압 강하를 일으켜 소자의 동작에 바람직하지 못한 결과를 가져온다.On the other hand, as shown in FIG. 1, a problem that occurs when the gate electrodes of the NMOS and the PMOS are formed in different conductivity types is a PN junction generated between the p + gate electrodes 15A and the n + gate electrodes 15B. There is a junction. This causes a voltage drop as the charge moves from p + to n + , which is undesirable for the device's operation.
이 경우, 도2에 도시한 바와 같이 폴리실리콘막으로 형성된 NMOS 및 PMOS 트랜지스터의 게이트 전극 상에 WSi2등과 같은 실리사이드층(silicide layer)(16)을 형성하면 PN 접합을 통하지 않고 실리사이드층(16)을 통해 전류가 흐름에 따라 PN 접합 문제를 해결할 수 있다.In this case, as shown in FIG. 2, when the silicide layer 16 such as WSi 2 is formed on the gate electrodes of the NMOS and PMOS transistors formed of the polysilicon film, the silicide layer 16 does not pass through the PN junction. This solves the PN junction problem as the current flows.
그러나, 전술한 바와 같이 실리사이드층을 사용할 때는 p+게이트 전극(15A) 내에 주입된 붕소(B)이온이 후속 열처리(thermal process)에 의해 n+게이트 전극(15B)에까지 확산되어 n+게이트 전극(15B)의 특성을 변화시키고 결국은 NMOS 트랜지스터의 특성변화를 유발하는 것이다.However, the implanted boron (B) ions are spread far n + gate electrode (15B) by the subsequent heat treatment (thermal process) n + gate electrode in the p + gate electrode (15A) when using the silicide layer as described above ( The characteristics of 15B) are changed and eventually the characteristics of the NMOS transistors are induced.
또한, 텅스텐 실리사이드층을 형성할 경우에는 다음의 반응식1과 같은 과정에서 발생한 불소(F) 이온이 게이트 산화막(14)까지 확산되어 트랜지스터의 특성을 변화시킨다.In addition, in the case of forming the tungsten silicide layer, fluorine (F) ions generated in the process as in the following Reaction 1 are diffused to the gate oxide film 14 to change the characteristics of the transistor.
도1 및 도2에서 미설명 도면부호 '10'은 반도체 기판, '11'은 n-웰, '12'는 p-웰, '13'은 소자분리막을 각각 나타낸다.1 and 2, reference numeral '10' denotes a semiconductor substrate, '11' denotes an n-well, '12' denotes a p-well, and '13' denotes an isolation layer.
[반응식][Scheme]
WF6+ 2SiH4→ WSi2+ 6HF + H2 WF 6 + 2 SiH 4 → WSi 2 + 6 HF + H 2
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 서로 다른 전도형의 게이트 전극을 갖으며 두 게이트 전극이 접하는 PMOS 및 NMOS 트랜지스터로 이루어지는 CMOS 트랜지스터에서, 두 게이트 전극의 접함으로 인하여 발생하는 PN 접합 문제와 게이트 전극 내에 도핑된 불순물의 확산을 효과적으로 방지할 수 있는 CMOS 트랜지스터 제조 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is a PN junction problem caused by the contact of two gate electrodes in a CMOS transistor having a PMOS and an NMOS transistor having a gate electrode of a different conductivity type and the two gate electrodes contact. And to provide a CMOS transistor manufacturing method that can effectively prevent the diffusion of the doped impurities in the gate electrode.
도1 및 도2는 종래 기술에 따라 형성된 CMOS 트랜지스터의 단면도,1 and 2 are cross-sectional views of a CMOS transistor formed according to the prior art,
도3a 내지 도3j는 본 발명의 일실시예에 따른 CMOS 트랜지스터 제조 공정 단면도.3A to 3J are cross-sectional views of a CMOS transistor manufacturing process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings
24: 게이트 산화막 25: 폴리실리콘막24: gate oxide film 25: polysilicon film
25A: n+게이트 전극 25B: p+게이트 전극25A: n + gate electrode 25B: p + gate electrode
26: 질화막 스페이서 27: 질화막26 nitride film spacer 27 nitride film
28: 산화막 29: 금속막28: oxide film 29: metal film
29A: 금속배선 29B: 금속콘택29A: Metal Wiring 29B: Metal Contact
상기와 같은 목적을 달성하기 위한 본 발명은 웰(well) 형성 공정 및 소자분리막 형성 공정이 완료된 반도체 기판 상에 게이트 산화막 및 폴리실리콘막을 차례로 형성하는 제1 단계; 제1 도전형 모스 트랜지스터(MOS transistor)의 제1 도전형 게이트 전극을 형성하기 위하여, 제1 도전형 모스 트랜지스터 영역의 상기 폴리실리콘막 내에 제1 도전형 불순물을 이온주입하는 제2 단계; 제2 도전형 모스 트랜지스터의 제2 도전형 게이트 전극을 형성하기 위하여 제2 도전형 모스 트랜지스터 영역의 상기 폴리실리콘막 내에 제2 도전형 불순물을 이온주입하는 제3 단계; 상기 폴리실리콘막을 선택적으로 식각하여 상기 제1 도전형 게이트 전극과 상기 제2 도전형 게이트 전극을 분리시키는 제4 단계; 이온주입을 실시하여 제1 도전형 모스 트랜지스터 및 제2 도전형 모스 트랜지스터 각각의 소오스 및 드레인을 형성하는 제5 단계; 상기 제5 단계가 완료된 전체 구조 상에 절연막을 형성하는 제6 단계; 상기 제1 도전형 게이트 전극과 상기 제2 도전형 게이트 전극 사이에 형성된 절연막을 선택적으로 식각하여 이웃하는 상기 제1 도전형 게이트 전극과 상기 제2 도전형 게이트 전극 각각의 측벽을 노출시키는 제7 단계; 및 상기 제1 도전형 게이트 전극과 상기 제2 도전형 게이트 전극을 연결하는 전도막 콘택(contact)을 형성하는 제8 단계를 포함하는 CMOS 트랜지스터 제조 방법을 제공한다.The present invention for achieving the above object is a first step of sequentially forming a gate oxide film and a polysilicon film on a semiconductor substrate in which a well forming process and the device isolation film forming process is completed; A second step of ion implanting a first conductivity type impurity into the polysilicon film in a first conductivity type MOS transistor to form a first conductivity type gate electrode of a first conductivity type MOS transistor; A third step of ion implanting a second conductivity type impurity into the polysilicon film in a second conductivity type MOS transistor region to form a second conductivity type gate electrode of a second conductivity type MOS transistor; Selectively etching the polysilicon layer to separate the first conductive gate electrode from the second conductive gate electrode; Performing a ion implantation to form a source and a drain of each of the first conductive MOS transistor and the second conductive MOS transistor; A sixth step of forming an insulating film on the entire structure in which the fifth step is completed; A seventh step of selectively etching an insulating layer formed between the first conductive gate electrode and the second conductive gate electrode to expose sidewalls of each of the neighboring first conductive gate electrode and the second conductive gate electrode; ; And an eighth step of forming a conductive film contact connecting the first conductive gate electrode and the second conductive gate electrode.
본 발명은 NMOS의 n+게이트 전극과 PMOS의 p+게이트 전극의 패턴 형성시 두 게이트 전극을 완전히 분리시킨 후 열처리 공정을 진행하고, 이후 금속 콘택 형성시 콘택을 통해 n+게이트 전극과 p+게이트 전극을 연결하는데 그 특징이 있다.In the present invention, the two gate electrodes are completely separated during the pattern formation of the n + gate electrode of the NMOS and the p + gate electrode of the PMOS, followed by a heat treatment process, and then the n + gate electrode and the p + gate are formed through a contact when forming a metal contact. It is characterized by connecting the electrodes.
n+게이트 전극과 p+게이트 전극이 완전히 분리된 상태에서 열처리 공정을 실시하므로 도펀트(dopant)가 반대 도전형의 게이트 전극으로 확산되는 것을 효과적으로 방지할 수 있을 뿐만 아니라 금속 콘택을 이용하여 n+게이트 전극과 p+게이트 전극을 연결하므로 PN 접합에 따른 문제를 근본적으로 해결할 수 있다.The heat treatment process is performed when the n + gate electrode and the p + gate electrode are completely separated, thereby effectively preventing the dopant from diffusing to the gate electrode of the opposite conductivity type, and using the metal contact to form the n + gate. Connecting the electrode and the p + gate electrode can fundamentally solve the problem of PN junction.
이하, 첨부된 도면 도3a 내지 도3j를 참조하여 본 발명의 일실시예에 따른 CMOS 트랜지스터 제조 방법을 상세히 설명한다.Hereinafter, a method of manufacturing a CMOS transistor according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3J.
먼저, 도3a에 도시한 바와 같이 n-웰(21) 및 p-웰(22) 그리고, 소자분리막(23) 형성 공정이 완료된 실리콘 기판(20) 상에 게이트 산화막(24) 및 폴리실리콘막(25)을 형성한다.First, as shown in FIG. 3A, the gate oxide film 24 and the polysilicon film (on the n-well 21 and p-well 22 and the silicon substrate 20 on which the device isolation film 23 is formed) are completed. 25).
다음으로, 도3b에 도시한 바와 같이 PMOS 트랜지스터 영역 상에 제1 이온주입마스크(PR1)를 형성하고 n+이온주입공정을 실시한 다음, 도3c에 도시한 바와 같이 제1 이온주입마스크(PR1)를 제거하고, NMOS 트랜지스터 영역 상에 제2 이온주입마스크(PR2)를 형성하고 p+이온주입공정을 실시한다.Next, as shown in FIG. 3B, a first ion implantation mask PR1 is formed on the PMOS transistor region and n + ion implantation process is performed. Then, as shown in FIG. 3C, the first ion implantation mask PR1 is formed. Next, the second ion implantation mask PR2 is formed on the NMOS transistor region and the p + ion implantation process is performed.
다음으로, 도3d에 도시한 바와 같이 제2 이온주입마스크(PR1)를 제거하고, 폴리실리콘막(25)을 선택적으로 식각하여NMOS 트랜지스터의 n+게이트 전극(25A)과 PMOS 트랜지스터의 p+게이트 전극(25B)을 분리시킨다.Next, as illustrated in FIG. 3D, the second ion implantation mask PR1 is removed, and the polysilicon film 25 is selectively etched to n + gate electrodes 25A of the NMOS transistor and p + gate of the PMOS transistor. The electrode 25B is separated.
다음으로, 도3e에 도시한 바와 같이 전체 구조 상에 질화막을 형성하고 전면식각하여 n+게이트 전극(25A)과 p+게이트 전극(25B) 측벽에 질화막 스페이서(26)를 형성한 후, 이온주입을 실시하여 n+소오스/드레인(도시하지 않음) 및 p+소오스/드레인(도시하지 않음)을 형성한다.Next, as shown in FIG. 3E, a nitride film is formed over the entire structure, and the surface is etched to form a nitride film spacer 26 on the sidewalls of the n + gate electrode 25A and the p + gate electrode 25B. N + source / drain (not shown) and p + source / drain (not shown) are formed.
다음으로, 도3f에 도시한 바와 같이 식각정지막인 질화막(27) 및 층간절연을 위한 산화막(28)을 차례로 형성한다.Next, as shown in Fig. 3F, a nitride film 27, which is an etch stop film, and an oxide film 28 for interlayer insulation are sequentially formed.
다음으로, 도3g에 도시한 바와 같이 산화막(28)을 선택적으로 식각하여 n+게이트 전극(25A)과 p+게이트 전극(25B) 사이의 질화막(27)을 노출시킨다.Next, as illustrated in FIG. 3G, the oxide film 28 is selectively etched to expose the nitride film 27 between the n + gate electrode 25A and the p + gate electrode 25B.
다음으로, 도3h에 도시한 바와 같이 n+게이트 전극(25A)과 p+게이트 전극(25B) 사이의 질화막(27) 및 질화막 스페이서(26)를 제거한다. 이때, 질화막(27) 및 질화막 스페이서(26)가 산화막으로 형성된 경우에는 식각시 소자분리막(23)이 손상되기 때문에 질화막(27) 또는 질화막 스페이서(26)는 식각정지를 위하여 질화막으로 형성되었다.Next, as shown in FIG. 3H, the nitride film 27 and the nitride film spacer 26 between the n + gate electrode 25A and the p + gate electrode 25B are removed. In this case, when the nitride layer 27 and the nitride layer spacer 26 are formed of an oxide layer, the device isolation layer 23 is damaged during etching, and thus the nitride layer 27 or the nitride layer spacer 26 is formed of a nitride layer for etching stop.
다음으로, 도3i에 도시한 바와 같이 전체 구조 상에 금속막(29)을 형성한다.Next, as shown in Fig. 3I, a metal film 29 is formed over the entire structure.
다음으로, 도3j에 도시한 바와 같이 금속막(29)을 패터닝하여 금속배선(29A)을 형성하는 과정에서 n+게이트 전극(25A)과 p+게이트 전극(25B)을 연결하는 금속콘택(29B)을 함께 형성한다. 이때, n+게이트 전극(25A)과 p+게이트 전극(25B)을 연결하는 금속콘택(29B)은 두 게이트 전극 사이의 공간에 금속막이 매립되는 형태로 형성되므로, 금속콘택(29B)을 정의하는 별도의 마스크 패턴은 필요하지 않다.Next, as shown in FIG. 3J, the metal contact 29B connecting the n + gate electrodes 25A and the p + gate electrodes 25B in the process of forming the metal wiring 29A by patterning the metal film 29. ) Together. In this case, the metal contact 29B connecting the n + gate electrode 25A and the p + gate electrode 25B is formed in a shape in which a metal film is buried in a space between the two gate electrodes, thereby defining the metal contact 29B. No separate mask pattern is needed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 이중 폴리게이트(dual poly gate)로 구성된 CMOS 트랜지스터에서 문제가 되는 PN 접합 문제를 금속콘택으로 제거할 수 있으며, 도펀트(dopant)의 확산에 의한 문제는 게이트를 분리시킴으로써 해결할 수 있다. 따라서, NMOS, PMOS 모두 표면 채널 트랜지스터로 만들 수 있어서 트랜지스터 크기를 줄일 수 있으며 열처리 공정에 의한 트랜지스터의 특성열화를 방지할 수 있다.According to the present invention, the PN junction problem, which is a problem in a CMOS transistor composed of a dual poly gate, can be eliminated by a metal contact, and the problem of diffusion of dopants is solved by separating the gate. Can be. Therefore, both NMOS and PMOS can be made into surface channel transistors, thereby reducing transistor size and preventing deterioration of transistor characteristics due to a heat treatment process.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020094588A (en) * | 2001-06-12 | 2002-12-18 | 주식회사 하이닉스반도체 | Semiconductor devicd and method for manufacturing the same |
| KR101876305B1 (en) * | 2013-01-04 | 2018-07-11 | 삼성전자주식회사 | Semiconductor device and forming the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020094588A (en) * | 2001-06-12 | 2002-12-18 | 주식회사 하이닉스반도체 | Semiconductor devicd and method for manufacturing the same |
| KR101876305B1 (en) * | 2013-01-04 | 2018-07-11 | 삼성전자주식회사 | Semiconductor device and forming the same |
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