KR19990037892A - Multi-Etchant method for Ti/Al and Ti/Al-Nd metal membrane layer patterning of the TFT-LCD making method - Google Patents

Multi-Etchant method for Ti/Al and Ti/Al-Nd metal membrane layer patterning of the TFT-LCD making method Download PDF

Info

Publication number
KR19990037892A
KR19990037892A KR1019990005010A KR19990005010A KR19990037892A KR 19990037892 A KR19990037892 A KR 19990037892A KR 1019990005010 A KR1019990005010 A KR 1019990005010A KR 19990005010 A KR19990005010 A KR 19990005010A KR 19990037892 A KR19990037892 A KR 19990037892A
Authority
KR
South Korea
Prior art keywords
layer
tft
metal layer
etchant
metal
Prior art date
Application number
KR1019990005010A
Other languages
Korean (ko)
Other versions
KR100318858B1 (en
Inventor
정지완
Original Assignee
정지완
케이와이휴텍 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정지완, 케이와이휴텍 주식회사 filed Critical 정지완
Priority to KR1019990005010A priority Critical patent/KR100318858B1/en
Publication of KR19990037892A publication Critical patent/KR19990037892A/en
Application granted granted Critical
Publication of KR100318858B1 publication Critical patent/KR100318858B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66765Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

본 발명은 TFT-LCD(박막 트렌지스터-액정 디스플레이)의 제조공정 중에서 크레드층인 Ti와 금속층인 Al의 금속막층의 패턴과 동시에 에칭이 가능하도록 하는 것이다The present invention enables etching simultaneously with the pattern of the metal film layer of Ti, which is a cladding layer, and Al, which is a metal layer, during the manufacturing process of a TFT-LCD (thin film transistor-liquid crystal display).

종래 TFT-LCD의 제조공정중 크레드층(Mo)과 메탈층(Al)의 구성 원소의 전기화학적 특성상 동일 에천트에 의해 원하는 패턴의 동시 에칭이 되지않아 별도의 에천트를 사용 하므로 상대적 공정수가 증가하여 제조원가의 상승 및 생산성저하 요인이 되었다.Due to the electrochemical characteristics of the constituent elements of the cladding layer (Mo) and the metal layer (Al) during the manufacturing process of the conventional TFT-LCD, since the same etchant does not simultaneously etch a desired pattern, a separate etchant is used, so the relative process number increases. As a result, manufacturing costs have increased and productivity has decreased.

따라서 본 발명은 종래의 크레드층(Mo)과 메탈층(Al)의 구성원소 대신에 크레드층을 Ti, 메탈층을 Al 또는 Al + Nd(1∼10wt%)의 Al합금을 사용하여 원하는 패턴인 45°의 에칭 프로파일을 얻음과 동시에 크레드층과 메탈층이 동시에 에칭이 가능한 동시 에천트를 제공함을 특징으로 하여 기존대비 공정단축에 의해 제조원가를 절감하고 생산성 제고를 통한 가격경쟁력을 제공하는 것이다.Therefore, in the present invention, instead of the conventional elements of the cladding layer (Mo) and the metal layer (Al), the cradle layer is Ti, the metal layer is Al or Al + Nd (1-10wt%) Al alloy of the desired pattern In addition to obtaining an etching profile of 45 °, the etch and creed layers can be simultaneously etched to allow simultaneous etching of the metal layer, thereby reducing manufacturing costs and providing cost competitiveness through improved productivity.

Description

티에프티-엘시디 제조공정중 티아이/에이엘과 티아이/에이엘-엔디 금속막층의 패턴닝을 위한 멀티 에천트 제조방법{Multi-Etchant method for Ti/Al and Ti/Al-Nd metal membrane layer patterning of the TFT-LCD making method}Multi-Etchant method for Ti / Al and Ti / Al and Ti / Al-Nd metal membrane layer patterning of the TFT -LCD making method}

본 발명은 TFT-LCD(박막 트렌지스터-액정 디스플레이)의 제조공정 중에서 크레드층인 Ti와 금속층인 Al 또는 Al-Nd합금의 금속막층의 패턴닝을 위해 동시에 에칭이 가능하도록 하는 것이다.The present invention enables etching simultaneously for patterning of a metal layer of Ti or a metal layer of Al or Al-Nd alloy, which is a creed layer and a metal layer, in a manufacturing process of a TFT-LCD (thin film transistor-liquid crystal display).

TFT(Thin Film Transistor)-LCD의 구성 요소 중에서 게이트(Gate)전극, 소스(Source)전극 및 드레인(Drain)전극은 금속막층으로 되어 있으며, 이 금속막은 Al, Cu 와 같은 전기저항이 낮은 금속이 적용되어지고 있다.Among the components of thin film transistor (TFT) -LCD, the gate electrode, the source electrode, and the drain electrode are made of a metal film layer, and the metal film is made of metal having low electrical resistance such as Al and Cu. Is being applied.

그런데, 이 금속막은 EM(Electro - Migration)현상 때문에 Al, Cu 단독으로 사용이 어려운 상태이므로 현재는 EM현상 방지를 위해 메탈 금속막의 상부에 크레드 (Clad) 막을 도포 하는 크레드/메탈(Metal) 형태의 금속막층으로 구성되어있다.However, since the metal film is difficult to use Al and Cu alone due to EM (Electro-migration) phenomenon, it is currently in the form of a cradle / metal type to apply a clad film on top of the metal metal film to prevent EM phenomenon. It consists of a metal film layer.

그리고 후공정인 패턴의 형성을 위한 습식식각공정 에서는 에천트(Etchant)를 사용하여 45°를 유지하는 사다리꼴의 에칭 프로파일(Etch Profile)을 가지도록 패턴 식각을 하여야 한다.In the wet etching process for the formation of the pattern, which is a post-process, the pattern is etched to have a trapezoidal etching profile that maintains 45 ° using an etchant.

그러나 기존의 습식식각공정 에서는 크레드층과 메탈층의 구성 원소의 전기화학적 특성상 동일 에천트에 의해 원하는 패턴의 동시 에칭이 되지 않아 별도의 에천트를 사용하여 크레드층(Mo)식각과 메탈층(Al)식각을 별도로 실시하므로서 상대적으로 공정수가 증가하게 된다.However, in the conventional wet etching process, since the desired pattern is not etched simultaneously by the same etchant due to the electrochemical properties of the constituent elements of the clad layer and the metal layer, a separate etchant is used to etch the crad layer (Mo) and the metal layer (Al). As the etching is performed separately, the number of processes increases relatively.

따라서 패턴과 에칭이 동시에 이루어지지 않는 관계로 공정수가 자연히 증가하여 제조원가를 상승시키는 요인이 되며, 이로 인하여 생산성이 저하되는 원인이 되는 것이다.Therefore, since the number of processes is naturally increased because the pattern and the etching are not performed at the same time, the manufacturing cost is increased, which causes a decrease in productivity.

즉, 기존의 TFT-LCD용 금속막층은 크레드층이 Mo, 메탈층이 Al으로 구성되어 있어서 Mo과 Al은 wjs극 전위차가 크기 때문에 패턴닝(Patterning) 공정인 습식식각 과정에서 갈바닉 전지(Galvanic Cell)를 형성하여 전기화학적 에칭현상이 일어나 Mo은 음극, Al은 양극 역할을 하여 메탈층인 Al의 에칭속도가 크레드층인 Mo에 비해 매우 빠르기 때문에 원하는 패턴의 형성을 위한 동시 에칭이 불가능한 실정 이다.That is, in the conventional TFT-LCD metal film layer, since the cladding layer is made of Mo and the metal layer is made of Al, Mo and Al have a large wjs pole potential difference, so a galvanic cell is used in the wet etching process, which is a patterning process. ), And the electrochemical etching phenomenon occurs, Mo acts as a cathode, Al acts as an anode, so the etching rate of Al, which is a metal layer, is much faster than Mo, which is a crad layer.

본 발명은 크레드층과 메탈층을 한번에 동시에 에칭시켜 원하는 패턴을 구성시킴으로서 TFT-LCD의 제조공정 단축에 따른 제조원가를 절감하도록 하는 멀티-에천트(Multi-Etchant)제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention provides a multi-etch manufacturing method that reduces the manufacturing cost by shortening the manufacturing process of a TFT-LCD by forming a desired pattern by simultaneously etching a cradle layer and a metal layer at a time.

본 발명은 크레드층을 Ti, 메탈층을 Al 또는 Al + Nd(1 ∼ 10wt%)의 Al합금을 사용하여 원하는 패턴인 45°의 에칭 프로파일을 얻을 수 있는 것과 동시에 크레드층과 메탈층이 동시에 에칭이 가능하도록 함을 특징으로 하는 것이다.According to the present invention, an etch profile of 45 °, which is a desired pattern, can be obtained by using a Ti alloy for the Ti layer and an Al alloy of Al or Al + Nd (1 to 10 wt%), and simultaneously the etch layer and the metal layer are simultaneously etched. It is characterized by enabling this.

도 1 은 스텐다드 패턴의 TFT-LCD 도.1 is a TFT-LCD diagram of a standard pattern.

1 : 크레드층2 : 메탈층1: Creed layer 2: Metal layer

본 발명은 Al과 전극전위차를 최소화할 수 있는 Ti를 Mo대신 크레드층(1)으로 사용하여 원하는 패턴의 동시 에칭이 가능하도록 하는 것이다.The present invention is to enable the simultaneous etching of the desired pattern using Al and Ti, which can minimize the electrode potential difference, as the crad layer 1 instead of Mo.

그리고 크레드층(Ti)/메탈층(Al)의 금속막층 형태 외에도 기존 메탈층(Al)보다 에칭속도를 약간 감소시켜 원하는 패턴인 45°의 에칭 프로파일을 얻을 수 있도록 Al에 Nd를 1 ∼ 10wt% 첨가시킨 Al + Nd합금을 메탈층(2)으로 사용한 크레드층(Ti)/메탈층(Al+Nd합금)을 적용하는 것이다.In addition to the metal film layer form of the creed layer (Ti) / metal layer (Al), the etching rate is slightly reduced than that of the existing metal layer (Al), so that an etching profile of 45 °, which is a desired pattern, can be obtained. The cradle layer (Ti) / metal layer (Al + Nd alloy) using the added Al + Nd alloy as the metal layer 2 is applied.

상기의 금속막층을 동시에 에칭시킬 수 있는 멀티-에천트의 분자식(Formula)은 HF + HIO4+ HN03로 구성되어 있으며, 이때 HF는 0.1 ∼ 7.0wt%, HIO4는 0.01 ∼ 5.0wt%, HN03는 1.0 ∼ 65.0wt% 이다.The molecular formula of the multi-etchant which can simultaneously etch the metal layer is composed of HF + HIO 4 + HN0 3 , wherein HF is 0.1 to 7.0 wt%, HIO 4 is 0.01 to 5.0 wt%, HN0 3 is 1.0 to 65.0 wt%.

본 발명은 멀티 에천트의 적용시 Al과 전극전위차를 최소화할 수 있도록 하여 원하는 패턴의 동시 에칭이 가능하도록 하는 것이다.The present invention is to minimize the Al and the electrode potential difference when applying the multi-etchant to enable simultaneous etching of the desired pattern.

본 발명은 패턴의 동시 에칭이 가능하므로서 공정의 단축이 가능하여 제조원가를 절감하고 생산성 제고 등을 통한 TFT-LCD의 가격경쟁력 제고를 가져올 수 있는 것이다.In the present invention, since the pattern can be simultaneously etched, the process can be shortened, thereby reducing the manufacturing cost and increasing the price competitiveness of the TFT-LCD through productivity.

Claims (3)

상측인 크레드층(1)을 Ti, 하층인 메탈층(2)을 Al 또는 Al + Nd(1 ∼ 10wt%)합금으로한 금속막 층에서 패턴닝을 할때 45°의 각도를 유지하면서 동시에 동시 에칭이 가능하도록 함을 특징으로 하는 TFT-LCD제조공정중 Ti/Al과 Ti/Al-Nd 금속막층의 패턴닝을 위한 멀티 에천트 제조방법When patterning on a metal film layer in which the upper cradle layer 1 is made of Ti and the lower metal layer 2 is made of Al or Al + Nd (1-10 wt%) alloy, at the same time maintaining the angle of 45 ° A method of manufacturing a multi etchant for patterning Ti / Al and Ti / Al-Nd metal film layers during a TFT-LCD manufacturing process characterized by enabling etching 제 1 항에 있어서, 크레드층(1)과 메탈층(2)을 동시에 에칭하는 멀티 에천트는 혼산으로서 그 분자식은 HF + HIO4+ HN03임을 특징으로 하는 TFT-LCD제조공정중 Ti/Al과 Ti/Al-Nd 금속막층의 패턴닝을 위한 멀티 에천트 제조방법.The method of claim 1, wherein the multi etchant for simultaneously etching the cradle layer (1) and the metal layer (2) is mixed acid, the molecular formula of HF + HIO 4 + HN0 3 Ti and Al during the TFT-LCD manufacturing process A method for producing a multi etchant for patterning a Ti / Al-Nd metal film layer. 제 2 항에 있어서, HF + HIO4+ HN03중 HF는 0.1 ∼ 7.0wt%, HIO4는 0.01 ∼ 5.0wt%, HN03는 1.0 ∼ 65.0wt% 임을 특징으로 하는 TFT-LCD제조공정중 Ti/Al과 Ti/Al-Nd 금속막층의 패턴닝을 위한 멀티 에천트 제조방법.The method of claim 2 wherein the HF + HIO 4 + HN0 3 HF is 0.1 to 7.0wt%, HIO 4 is 0.01 to 5.0wt%, HN0 3 is 1.0 to 65.0wt% Ti during TFT-LCD manufacturing process A method for producing a multi etchant for the patterning of / Al and Ti / Al-Nd metal layers.
KR1019990005010A 1999-02-12 1999-02-12 Multi-Etchantd and metal membrane layer patterning of the TFT-LCD making method KR100318858B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990005010A KR100318858B1 (en) 1999-02-12 1999-02-12 Multi-Etchantd and metal membrane layer patterning of the TFT-LCD making method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990005010A KR100318858B1 (en) 1999-02-12 1999-02-12 Multi-Etchantd and metal membrane layer patterning of the TFT-LCD making method

Publications (2)

Publication Number Publication Date
KR19990037892A true KR19990037892A (en) 1999-05-25
KR100318858B1 KR100318858B1 (en) 2002-01-04

Family

ID=54780779

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990005010A KR100318858B1 (en) 1999-02-12 1999-02-12 Multi-Etchantd and metal membrane layer patterning of the TFT-LCD making method

Country Status (1)

Country Link
KR (1) KR100318858B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100980702B1 (en) * 2005-02-24 2010-09-07 간또 가가꾸 가부시끼가이샤 Etchant compositions for metal laminated films having titanium and aluminum layer
KR101317473B1 (en) * 2006-08-23 2013-10-18 간또 가가꾸 가부시끼가이샤 Etchant compositions for metal laminated films having titanium and aluminum layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100980702B1 (en) * 2005-02-24 2010-09-07 간또 가가꾸 가부시끼가이샤 Etchant compositions for metal laminated films having titanium and aluminum layer
KR101149003B1 (en) * 2005-02-24 2012-05-23 간또 가가꾸 가부시끼가이샤 Etchant compositions for metal laminated films having titanium and aluminum layer
KR101317473B1 (en) * 2006-08-23 2013-10-18 간또 가가꾸 가부시끼가이샤 Etchant compositions for metal laminated films having titanium and aluminum layer

Also Published As

Publication number Publication date
KR100318858B1 (en) 2002-01-04

Similar Documents

Publication Publication Date Title
US8148182B2 (en) Manufacturing method of electro line for liquid crystal display device
CN102983101B (en) Manufacturing method of array substrate for liquid crystal display
US6337520B1 (en) Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and manufacturing method thereof
KR102048022B1 (en) Composition for etching metal layer and method for etching using the same
US20040140566A1 (en) Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
JP2006339635A (en) Etching composition
CN102576170A (en) Method of fabricating array substrate for liquid crystal display
KR102400343B1 (en) Metal film etchant composition and manufacturing method of an array substrate for display device
KR100685953B1 (en) Method for Forming Metal Lines in Liquid Crystal Display Device
CN113667979A (en) Copper-molybdenum metal etching solution and application thereof
KR20010091799A (en) Electrode etching liquid in LCD display system
KR100318858B1 (en) Multi-Etchantd and metal membrane layer patterning of the TFT-LCD making method
KR101560000B1 (en) Manufacturing method of an array substrate for liquid crystal display
KR100456657B1 (en) Etchant for making metal electrodes of TFT in FPD
KR102505196B1 (en) Etchant composition for copper-containing metal layer and preparing method of an array substrate for liquid crystal display using same
CN103026293A (en) Method for producing an array substrate for a liquid crystal display device
KR100415700B1 (en) Etchant for manufacturing source and drain electrode in TFT-LCD
KR20030078208A (en) Etchant for making metal electrodes of TFT in FPD
CN107227461B (en) Indium oxidation film and molybdenum film etch combination
KR102459681B1 (en) Etchant for cupper-based metat layer, manufacturing method of an array substrate for liquid crystal display using the same and an array substrate for liquid crystal display
CN111755461B (en) Method for manufacturing array substrate for liquid crystal display device and copper-based metal film etching liquid composition for same
KR102384594B1 (en) Manufacturing method of an array substrate for display device
TW201207951A (en) Method of fabricating an array substrate for a liquid crystal display
KR102368356B1 (en) Etchant composition and manufacturing method of an array for liquid crystal display
KR102368028B1 (en) Etchant composition for etching multi-layered structure of different metals and method of forming wiring using the same

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20071019

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee