KR19990025316A - Capacitor Formation Method on Substrate - Google Patents
Capacitor Formation Method on Substrate Download PDFInfo
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- KR19990025316A KR19990025316A KR1019970046888A KR19970046888A KR19990025316A KR 19990025316 A KR19990025316 A KR 19990025316A KR 1019970046888 A KR1019970046888 A KR 1019970046888A KR 19970046888 A KR19970046888 A KR 19970046888A KR 19990025316 A KR19990025316 A KR 19990025316A
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Abstract
본 발명은 반도체 기판상에서 커패서터의 면적을 줄일 수 있도록 하기 위한 는 방법으로 양면을 형성하는 전도체 사이에 SIPOS를 유전체로 사용하여 커패서터를 형성한다.The present invention forms a capacitor using a SIPOS as a dielectric between conductors forming both sides in a method for reducing the area of the capacitor on the semiconductor substrate.
Description
본 발명은 기판상의 커패서터 형성 방법에 관한 것으로, 좀 더 구체적으로는 반도체 디바이스에서 기판상에 커패서터를 형성하기 위한 기판상의 커패서터 형성 방법에 관한 것이다.The present invention relates to a method of forming a capacitor on a substrate, and more particularly, to a method of forming a capacitor on a substrate for forming a capacitor on a substrate in a semiconductor device.
반도체 제조 공정에서 가장 문제점 중의 하나는 선폭의 미세화와 고집적화 그리고 다층화 등이다. 그리고, 상기 고집적화에서 가장 많은 문제를 유발시키는 것이 커패서터(capacitor)의 영역이다. 따라서, 이와 같은 커패서터의 면적을 줄이기 위해서는 동일한 효과를 얻을 수 있는 유전율이 높은 물질을 사용하거나 유전체의 두께를 낮춘다. 그러나, 유전체의 두께를 낮추는 것은 관리상 어려움이 많으므로 유전율이 높은 유전체를 이용하고 있으나, 주로 사용되고 있는 질화물(nitride) 등 유전체의 유전율는 7.5 정도이다.One of the biggest problems in the semiconductor manufacturing process is miniaturization, high integration, and multilayering of line widths. In addition, it is the area of the capacitor that causes the most problems in the high integration. Therefore, in order to reduce the area of such a capacitor, a material having a high dielectric constant capable of obtaining the same effect or reducing the thickness of the dielectric. However, lowering the thickness of the dielectric has many management difficulties, so a dielectric having a high dielectric constant is used. However, the dielectric constant of a dielectric such as nitride is generally about 7.5.
본 발명은 이와 같은 종래의 문제점을 해결하기 위한 것으로, 그 목적은 반도체 기판상에서 커패서터의 면적을 줄일 수 있는 새로운 형태의 기판상의 커패서터 형성 방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and an object thereof is to provide a method of forming a capacitor on a substrate of a new type which can reduce the area of the capacitor on the semiconductor substrate.
도 1은 본 발명의 실시예에 따른 기판상의 커패서터 형성 방법이 적용된 기판의 구조를 도시한 단면도이다.1 is a cross-sectional view illustrating a structure of a substrate to which a method of forming a capacitor on the substrate according to an embodiment of the present invention is applied.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : SIPOS 12 : 전도체10: SIPOS 12: Conductor
상술한 목적을 달성하기 위한 본 발명의 특징에 의하면, 기판상의 커패서터 형성 방법은 양면을 형성하는 전도체 사이에 SIPOS를 유전체로 사용하여 커패서터를 형성한다.According to a feature of the present invention for achieving the above object, a method of forming a capacitor on a substrate forms a capacitor using SIPOS as a dielectric between conductors forming both sides.
이와 같은 본 발명에서 상기 전도체 사이에 소정 재질의 유전체를 부가한다.In the present invention, a dielectric of a predetermined material is added between the conductors.
본 발명은 반도체 기판상에서 커패서터의 면적을 줄일 수 있도록 하는 방법을 제공하고자 하는 것이다.It is an object of the present invention to provide a method for reducing the area of a capacitor on a semiconductor substrate.
이때, 커패서터의 면적을 줄이기 위해서는 동일한 효과를 얻을 수 있는 유전율이 높은 물질을 사용하거나 유전체의 두께를 낮추는 방법이 있다. 그러나, 유전체의 두께를 낮추는 것은 관리상 어려움이 많으므로 유전율이 높은 유전체를 사용할 필요가 있다.At this time, in order to reduce the area of the capacitor, there is a method of using a material having a high dielectric constant or lowering the thickness of the dielectric. However, it is necessary to use a dielectric having a high dielectric constant because reducing the thickness of the dielectric has many management difficulties.
따라서, 본 발명은 커패서터를 구성하는 유전체로 SIPOS(semi insulated polycrystalized silicide)를 사용한다. 상기 SIPOS를 이용하면 유전율이 5.0에서 9.0까지의 막을 구성할 수 있다.Therefore, the present invention uses a semi insulated polycrystalized silicide (SIPOS) as the dielectric constituting the capacitor. Using the SIPOS it is possible to configure a film having a dielectric constant of 5.0 to 9.0.
도 1은 본 발명의 실시예에 따른 기판상의 커패서터 형성 방법이 적용된 기판의 구조를 도시한 단면도이다.1 is a cross-sectional view illustrating a structure of a substrate to which a method of forming a capacitor on the substrate according to an embodiment of the present invention is applied.
도 1에서 도시한 바와 같이 본 발명의 실시예에 따른 기판상의 커패서터 형성 방법은 양면을 형성하는 전도체(12) 사이에 SIPOS(10)를 유전체로 사용하여 커패서터를 형성한다.As shown in FIG. 1, in a method of forming a capacitor on a substrate according to an embodiment of the present invention, a capacitor is formed using a SIPOS 10 as a dielectric between conductors 12 forming both sides.
이때, 상기 전도체(12) 사이에 상기 SIPOS(10)와 다른 소정 재질의 유전체를 부가하여 사용할 수 있다.In this case, a dielectric of a predetermined material different from the SIPOS 10 may be added between the conductors 12.
이와 같이 본 발명의 실시예에 따른 SIPOS가 적용된 커패서터는 기판상에서 면적을 줄일 수 있으므로, 기판의 면적비가 증가하여 원가의 감소가 가능하다.As described above, since the SIPOS-enabled capacitor according to the embodiment of the present invention can reduce the area on the substrate, the area ratio of the substrate is increased, thereby reducing the cost.
이와 같은 본 발명을 적용하면 SIPOS를 이용하여 유전체의 막을 용이하게 조절할 수 있으므로 반도체 기판상에서 커패서터의 면적을 줄일 수 있다. 따라서, 커패서터의 면적의 감소에 따른 기판의 면적비가 증가하게 되므로 원가의 감소가 가능하다.Applying the present invention as described above it is possible to easily control the dielectric film by using the SIPOS it is possible to reduce the area of the capacitor on the semiconductor substrate. Therefore, the area ratio of the substrate is increased according to the reduction of the area of the capacitor, thereby reducing the cost.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970046888A KR19990025316A (en) | 1997-09-11 | 1997-09-11 | Capacitor Formation Method on Substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970046888A KR19990025316A (en) | 1997-09-11 | 1997-09-11 | Capacitor Formation Method on Substrate |
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| Publication Number | Publication Date |
|---|---|
| KR19990025316A true KR19990025316A (en) | 1999-04-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019970046888A KR19990025316A (en) | 1997-09-11 | 1997-09-11 | Capacitor Formation Method on Substrate |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4432035A (en) * | 1982-06-11 | 1984-02-14 | International Business Machines Corp. | Method of making high dielectric constant insulators and capacitors using same |
| JPS6411362A (en) * | 1987-07-03 | 1989-01-13 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH01164016A (en) * | 1987-12-21 | 1989-06-28 | Matsushita Electric Ind Co Ltd | Dielectric ceramic and its manufacture |
| JPH06140570A (en) * | 1992-10-26 | 1994-05-20 | Fujitsu Ltd | Electronic component having dielectric thin film of high dielectric constant and manufacture thereof |
-
1997
- 1997-09-11 KR KR1019970046888A patent/KR19990025316A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4432035A (en) * | 1982-06-11 | 1984-02-14 | International Business Machines Corp. | Method of making high dielectric constant insulators and capacitors using same |
| JPS6411362A (en) * | 1987-07-03 | 1989-01-13 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH01164016A (en) * | 1987-12-21 | 1989-06-28 | Matsushita Electric Ind Co Ltd | Dielectric ceramic and its manufacture |
| JPH06140570A (en) * | 1992-10-26 | 1994-05-20 | Fujitsu Ltd | Electronic component having dielectric thin film of high dielectric constant and manufacture thereof |
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