KR100278273B1 - A method for forming contact holes in semiconductor device - Google Patents

A method for forming contact holes in semiconductor device Download PDF

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KR100278273B1
KR100278273B1 KR1019970078022A KR19970078022A KR100278273B1 KR 100278273 B1 KR100278273 B1 KR 100278273B1 KR 1019970078022 A KR1019970078022 A KR 1019970078022A KR 19970078022 A KR19970078022 A KR 19970078022A KR 100278273 B1 KR100278273 B1 KR 100278273B1
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junction region
contact hole
gate electrode
forming
contact
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KR1019970078022A
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Korean (ko)
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KR19990057943A (en
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박재범
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 장치를 구성하는 층간의 수직 배선을 위한 콘택홀 형성 공정에 관한 것이며, 접합 영역의 손상 없이 접합 영역 및 게이트 전극에의 콘택을 위한 두 종류의 콘택홀을 동시에 형성할 수 있는 반도체 장치의 콘택홀 형성방법을 제공하는데 그 목적이 있다. 본 발명은 게이트 전극 상부의 마스크 절연막으로 산화막을 적용하고, 역시 산화막계인 층간절연막과 높은 식각 선택비를 갖는 질화막을 베리어층으로 접합 영역 상의 콘택 부분에 선택적으로 형성한 상태에서 층간절연막 증착 및 콘택홀 식각 공정을 진행함으로써 접합 영역의 손상을 유발하지 않으면서 접합 영역에 자기정렬 콘택홀을 형성함과 동시에 게이트 전극에도 콘택홀을 형성할 수 있다. 즉, 접합 영역의 손상 없이 두 종류의 콘택홀을 한 번의 마스크 공정 및 식각 공정을 통해 형성할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a process for forming a contact hole for vertical interconnection between layers constituting a semiconductor device. The present invention relates to two types of contact holes for contacting a junction region and a gate electrode without damaging the junction region. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of forming the same simultaneously. In the present invention, an oxide film is applied as a mask insulating film on the gate electrode, and an interlayer insulating film is deposited and a contact hole in a state in which an interlayer insulating film, which is also an oxide film, and a nitride film having a high etching selectivity are selectively formed in a contact portion on the junction region as a barrier layer. By performing the etching process, the self-aligned contact hole may be formed in the junction region without causing damage to the junction region, and at the same time, the contact hole may also be formed in the gate electrode. That is, two types of contact holes may be formed through one mask process and an etching process without damaging the junction region.

Description

반도체 장치의 콘택홀 형성방법{A method for forming contact holes in semiconductor device}A method for forming contact holes in semiconductor device

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 장치를 구성하는 전도층간의 수직 배선을 위한 콘택홀 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a contact hole forming process for vertical wiring between conductive layers constituting a semiconductor device.

반도체 장치가 고집적화에 따라 패턴의 선폭 및 패턴간의 거리가 좁아지고 있으며, 이에 따라 반도체 장치를 구성하는 도전층간의 수직 배선을 위한 콘택홀 형성시의 공정 마진이 줄어들고 있다. 이러한 콘택 공정의 마진을 확보하기 위하여 서로 다른 절연막간의 식각 선택비를 이용한 자기정렬 방식의 콘택홀 형성 공정이 일반화되고 있다.As the semiconductor devices are highly integrated, the line widths of the patterns and the distances between the patterns are narrowed. As a result, the process margin at the time of forming contact holes for the vertical wiring between the conductive layers constituting the semiconductor devices is reduced. In order to secure a margin of such a contact process, a self-aligning contact hole forming process using etching selectivity between different insulating layers is becoming common.

이하, 첨부된 도 1a 내지 도 1c를 참조하여 종래기술에 따른 콘택홀 형성 공정 및 그 문제점을 살펴본다.Hereinafter, a process of forming a contact hole and a problem thereof according to the prior art will be described with reference to FIGS. 1A to 1C.

먼저, 도 1a에 도시된 바와 같이 실리콘 기판(11) 상에 소자 분리막(12)을 형성하고, 전체구조 상부에 게이트 산화막(13)을 성장시킨 다음, 그 상부에 게이트 전극(14)을 형성한다. 이때, 게이트 전극(14)은 후속 자기정렬 콘택 공정을 위하여 그 상부의 마스크 질화막(15)과 그 측벽 부분의 스페이서 질화막(17)으로 덮여 있다. 이어서, 전체구조 상부에 평탄화된 층간절연막(18)을 형성한다. 여기서, 도면 부호 '16'은 접합 영역을 나타낸 것이다.First, as shown in FIG. 1A, the device isolation layer 12 is formed on the silicon substrate 11, the gate oxide layer 13 is grown on the entire structure, and then the gate electrode 14 is formed thereon. . At this time, the gate electrode 14 is covered with a mask nitride film 15 thereon and a spacer nitride film 17 at its sidewall portion for the subsequent self-aligned contact process. Next, a planarized interlayer insulating film 18 is formed over the entire structure. Here, reference numeral 16 denotes a junction region.

계속하여, 도 1b에 도시된 바와 같이 마스크 공정 및 식각 공정을 진행하여 층간절연막(18)을 선택 식각함으로써 접합 영역(16)을 노출시키는 자기정렬 콘택홀을 형성한다.Subsequently, as shown in FIG. 1B, a mask process and an etching process are performed to selectively etch the interlayer insulating layer 18, thereby forming a self-aligned contact hole exposing the junction region 16.

다음으로, 도 1c에 도시된 바와 같이 게이트 전극(14)에의 콘택을 이루기 위하여 다시 마스크 공정 및 식각 공정을 진행하여 층간절연막(18)을 선택 식각함으로써 게이트 전극(14)을 노출시키는 콘택홀을 형성한다.Next, as shown in FIG. 1C, in order to make contact with the gate electrode 14, a mask hole and an etching process are performed again to selectively etch the interlayer insulating layer 18 to form a contact hole exposing the gate electrode 14. do.

상술한 바와 같이 진행되는 종래의 콘택홀 형성 공정은 접합 영역 및 게이트 전극에의 콘택을 위하여 각각의 콘택홀 형성을 위한 2회의 마스크 공정 및 식각 공정을 수행해야 하므로 공정이 복잡해지는 문제점이 있다. 이처럼 접합 영역 및 게이트 전극에의 콘택을 위하여 각각의 콘택홀 형성을 위한 2회의 마스크 공정 및 식각 공정을 수행하는 이유는 층간절연막에 비해 식각 속도가 훨씬 느린 질화막(마스크 질화막)이 게이트 전극 상부를 덮고 있어 서로 식각 타겟이 다른 두 종류의 콘택홀을 동시에 식각할 경우 접합 영역의 손상이 유발되기 때문이다.The conventional contact hole forming process, which is performed as described above, has a problem in that the process is complicated because two mask processes and an etching process for forming each contact hole must be performed to contact the junction region and the gate electrode. The reason for performing the two mask processes and the etching process for forming each contact hole for contacting the junction region and the gate electrode is that the nitride film (mask nitride film), which is much slower than the interlayer insulating film, covers the gate electrode. This is because when two types of contact holes having different etching targets are etched at the same time, damage to the junction region is caused.

본 발명은 접합 영역의 손상 없이 접합 영역 및 게이트 전극에의 콘택 각각을 위한 콘택홀을 한 번의 마스크 공정 및 식각 공정을 통해 형성할 수 있는 반도체 장치의 콘택홀 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of forming a contact hole for each of a contact to a junction region and a gate electrode through a single mask process and an etching process without damaging the junction region.

도 1a 내지 도 1c는 종래기술에 따른 콘택홀 형성 공정도.1a to 1c is a contact hole forming process according to the prior art.

도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 콘택홀 형성 공정도.2a to 2d is a contact hole forming process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 실리콘 기판 22 : 소자 분리막21 silicon substrate 22 device isolation film

23 : 게이트 산화막 24 : 폴리실리콘막23 gate oxide film 24 polysilicon film

25 : 마스크 산화막 26 : 접합 영역25 mask oxide film 26 junction region

27 : 스페이서 산화막 28 : 질화막27 spacer oxide film 28 nitride film

29 : 층간절연막29: interlayer insulating film

상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 반도체 장치의 콘택홀 형성방법은, 게이트 절연막이 형성된 반도체 기판에 마스크 산화막 및 측벽 스페이서 절연막을 구비한 게이트 전극과 접합 영역을 형성하는 제1 단계; 상기 제1 단계를 마친 전체구조 상부에 베리어 질화막을 형성하는 제2 단계; 적어도 상기 게이트 전극 콘택 영역의 상기 베리어 질화막을 선택 식각하는 제3 단계; 상기 제3 단계를 마친 전체구조 상부에 산화막계의 층간절연막을 형성하는 제4 단계; 및 접합 영역 콘택 영역의 상기 층간절연막 및 베리어 질화막을 차례로 선택 식각하여 접합 영역을 노출시키는 제1 콘택홀을 형성하고, 동시에 상기 게이트 전극 콘택 영역의 상기 층간절연막을 선택 식각하여 상기 게이트 전극을 노출시키는 제2 콘택홀을 형성하는 제5 단계를 포함하여 이루어진다.According to another aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, comprising: forming a junction region and a gate electrode including a mask oxide layer and a sidewall spacer insulating layer on a semiconductor substrate on which a gate insulating layer is formed; A second step of forming a barrier nitride film on the entire structure of the first step; A third step of selectively etching the barrier nitride layer in at least the gate electrode contact region; A fourth step of forming an interlayer insulating film of an oxide film layer on the entire structure having finished the third step; And selectively etching the interlayer insulating layer and the barrier nitride layer in the junction region contact region to form a first contact hole exposing the junction region, and simultaneously etching the interlayer insulating layer in the gate electrode contact region to expose the gate electrode. And a fifth step of forming the second contact hole.

즉, 본 발명은 게이트 전극 상부의 마스크 절연막으로 산화막을 적용하고, 역시 산화막계인 층간절연막과 높은 식각 선택비를 갖는 질화막을 베리어층으로 접합 영역 상의 콘택 부분에 선택적으로 형성한 상태에서 층간절연막 증착 및 콘택홀 식각 공정을 진행함으로써 접합 영역의 손상을 유발하지 않으면서 접합 영역에 자기정렬 콘택홀을 형성함과 동시에 게이트 전극에도 콘택홀을 형성할 수 있다. 즉, 접합 영역의 손상 없이 두 종류의 콘택홀을 한 번의 마스크 공정 및 식각 공정을 통해 형성할 수 있다.That is, the present invention applies an oxide film as a mask insulating film on the gate electrode, and deposits an interlayer insulating film in a state in which an interlayer insulating film, which is also an oxide film, and a nitride film having a high etching selectivity, are selectively formed in a contact portion on the junction region as a barrier layer. By performing the contact hole etching process, a self-aligned contact hole may be formed in the junction region without causing damage to the junction region, and at the same time, a contact hole may also be formed in the gate electrode. That is, two types of contact holes may be formed through one mask process and an etching process without damaging the junction region.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 콘택홀 형성 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 설명한다.2A to 2D illustrate a process of forming a contact hole according to an embodiment of the present invention, and the process will be described below with reference to the drawings.

우선, 도 2a에 도시된 바와 같이 실리콘 기판(21) 상에 소자 분리막(22)을 형성한 다음, 전체구조 상부에 게이트 산화막(23), 폴리실리콘막(24) 및 마스크 산화막(25)을 차례로 형성하고, 게이트 전극 형성을 위한 식각 마스크를 사용하여 마스크 산화막(25) 및 폴리실리콘막(24)을 차례로 선택 식각하여 게이트 전극을 형성한다. 이어서, LDD(Lightly Doped Drain) 구조 형성을 위한 저농도의 도전형 불순물 이온주입을 실시하고, 게이트 전극 측벽 부분에 스페이서 산화막(27)을 형성한 다음, 고농도의 도전형 불순물 이온주입을 실시하여 접합 영역(26)을 형성한다.First, as shown in FIG. 2A, the device isolation film 22 is formed on the silicon substrate 21, and then the gate oxide film 23, the polysilicon film 24, and the mask oxide film 25 are sequentially formed on the entire structure. The mask oxide layer 25 and the polysilicon layer 24 are sequentially etched sequentially using an etching mask for forming a gate electrode to form a gate electrode. Subsequently, a low concentration of conductive impurity ions are implanted to form a lightly doped drain (LDD) structure, a spacer oxide layer 27 is formed on the sidewall portion of the gate electrode, and a high concentration of conductive impurity ions is implanted to form a junction region. (26) is formed.

계속하여, 도 2b에 도시된 바와 같이 후속 층간절연막 식각시 높은 선택비를 갖는 베리어층으로써 질화막(28)을 전체구조 상부에 증착한다.Subsequently, as illustrated in FIG. 2B, a nitride layer 28 is deposited on the entire structure as a barrier layer having a high selectivity during subsequent interlayer insulating layer etching.

다음으로. 도 2c에 도시된 바와 같이 질화막(28)을 선택 식각하여 후속 게이트 전극에의 콘택을 위한 콘택홀이 형성될 부분의 질화막(28)을 선택적으로 제거한다.to the next. As illustrated in FIG. 2C, the nitride film 28 is selectively etched to selectively remove the nitride film 28 in a portion where a contact hole for a subsequent contact to the gate electrode is to be formed.

계속하여, 도 2d에 도시된 바와 같이 전체구조 상부에 산화막계 층간절연막(29)을 증착하고, 층간절연막(29) 및 질화막(28)을 선택 식각하여 접합 영역(26) 및 게이트 전극(폴리실리콘막)을 노출시키는 콘택홀을 형성한다. 이때, 접합 영역(26)을 노출시키는 콘택홀은 자기정렬 방식으로 형성되고, 게이트 전극 콘택 영역에서는 콘택홀 식각 과정에서 마스크 산화막(25)이 선택 식각되며, 따라서 접합 영역(26)의 손상을 방지할 수 있다.Subsequently, as shown in FIG. 2D, an oxide-based interlayer insulating film 29 is deposited on the entire structure, and the interlayer insulating film 29 and the nitride film 28 are selectively etched to bond the junction region 26 and the gate electrode (polysilicon). A contact hole exposing the film). In this case, the contact hole exposing the junction region 26 is formed in a self-aligned manner, and the mask oxide layer 25 is selectively etched during the contact hole etching process in the gate electrode contact region, thereby preventing damage to the junction region 26. can do.

상기와 같은 공정을 실시하는 경우, 접합 영역 콘택 영역에는 층간절연막과 높은 식각 선택비를 갖는 베리어 질화막이 존재하기 때문에 접합 영역의 손상 없이 두 종류의 콘택홀(접합 영역 및 게이트 전극)을 한 번의 마스크 공정 및 식각 공정을 통해 형성할 수 있다.In the above process, since there is an interlayer insulating film and a barrier nitride film having a high etching selectivity in the junction region contact region, two types of contact holes (junction region and gate electrode) are masked once without damaging the junction region. It can be formed through a process and an etching process.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

예컨대, 전술한 실시예에서는 스페이서 절연막으로 산화막을 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 스페이서 절연막으로 질화막을 사용하는 경우에도 적용된다.For example, in the above-described embodiment, the case where the oxide film is used as the spacer insulating film has been described as an example, but the present invention is also applied to the case where the nitride film is used as the spacer insulating film.

이상에서와 같이 본 발명은 접합 영역의 손상 없이 접합 영역에 자기정렬 방식으로 콘택홀을 형성함과 동시에 게이트 전극에도 콘택홀을 형성함으로써 반도체 장치 제조 공정을 단순화하는 효과가 있다.As described above, the present invention has the effect of simplifying a semiconductor device manufacturing process by forming contact holes in the junction region in a self-aligned manner without damaging the junction region, and also forming contact holes in the gate electrode.

Claims (1)

게이트 절연막이 형성된 반도체 기판에 마스크 산화막 및 측벽 스페이서 절연막을 구비한 게이트 전극과 접합 영역을 형성하는 제1 단계;Forming a junction region and a gate electrode including a mask oxide film and a sidewall spacer insulating film on a semiconductor substrate on which the gate insulating film is formed; 상기 제1 단계를 마친 전체구조 상부에 베리어 질화막을 형성하는 제2 단계;A second step of forming a barrier nitride film on the entire structure of the first step; 적어도 상기 게이트 전극 콘택 영역의 상기 베리어 질화막을 선택 식각하는 제3 단계;A third step of selectively etching the barrier nitride layer in at least the gate electrode contact region; 상기 제3 단계를 마친 전체구조 상부에 산화막계의 층간절연막을 형성하는 제4 단계; 및A fourth step of forming an interlayer insulating film of an oxide film layer on the entire structure having finished the third step; And 접합 영역 콘택 영역의 상기 층간절연막 및 베리어 질화막을 차례로 선택 식각하여 접합 영역을 노출시키는 제1 콘택홀을 형성하고, 동시에 상기 게이트 전극 콘택 영역의 상기 층간절연막을 선택 식각하여 상기 게이트 전극을 노출시키는 제2 콘택홀을 형성하는 제5 단계Selectively etching the interlayer insulating layer and the barrier nitride layer in the junction region contact region to form a first contact hole for exposing the junction region, and simultaneously etching the interlayer insulating layer in the gate electrode contact region to expose the gate electrode. 5th step of forming a contact hole 를 포함하여 이루어진 반도체 장치의 콘택홀 형성방법.Contact hole forming method of a semiconductor device comprising a.
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