KR19980072232A - Manufacturing method of liquid crystal display device for IPS mode thin film transistor - Google Patents
Manufacturing method of liquid crystal display device for IPS mode thin film transistor Download PDFInfo
- Publication number
- KR19980072232A KR19980072232A KR1019970006888A KR19970006888A KR19980072232A KR 19980072232 A KR19980072232 A KR 19980072232A KR 1019970006888 A KR1019970006888 A KR 1019970006888A KR 19970006888 A KR19970006888 A KR 19970006888A KR 19980072232 A KR19980072232 A KR 19980072232A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- gate
- gate insulating
- insulating layer
- amorphous silicon
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 10
- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 85
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000011241 protective layer Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 239000011159 matrix material Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 1
- 229910004205 SiNX Inorganic materials 0.000 description 4
- 239000011521 glass Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
Landscapes
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명에 의한 IPS(In-Plane Switching) 모드 박막트랜지스터용 액정표시소자(TFT-LCD) 제조방법은, 게이트 전극과 게이트 패드부 및 공통 전극이 구비되어 있는 하부기판 상에 게이트 절연층, 반도체층, n+ 비정질실리콘층을 증착하는 공정과, 상기 게이트 패드부 및 공통 전극 상의 게이트 절연층이 소정 부분 노출되도록, 상기 n+ 비정질실리콘층 및 반도체층을 식각하여 액티브 패턴을 형성하는 공정과, 상기 액티브 패턴을 포함한 게이트 절연층 상에 금속배선층을 형성하는 공정과, 상기 금속배선층을 선택식각하여 소오스/드레인 전극을 형성하는 공정과, 상기 소오스/드레인 전극을 마스크로 상기 n+ 비정질실리콘층을 식각하여 채널을 형성하는 공정과, 상기 소오스/드레인 전극을 포함한 게이트 절연층과 반도체층 상에 보호층을 형성하는 공정과, 칼라필터와 블랙매트릭스가 구비된 상부기판을 게이트 패드부 상의 보호층이 오픈되도록 상기 하부기판과 조립하고 그 사이에 액정을 주입하는 공정 및, 상기 게이트 패드부 상의 보호층과 게이트 절연층을 건식식각법으로 제거하는 공정으로 이루어져, 박막트랜지스터 제조시 마스크 1매를 줄일 수 있게 되므로 공정 단순화와 비용 절감 및 수율 향상을 기할 수 있게 된다.In a method of manufacturing an In-Plane Switching (IPS) mode thin film transistor (TFT-LCD) according to the present invention, a gate insulating layer and a semiconductor layer are provided on a lower substrate including a gate electrode, a gate pad part, and a common electrode. depositing an n + amorphous silicon layer, etching the n + amorphous silicon layer and the semiconductor layer to form an active pattern so that a predetermined portion of the gate insulating layer on the gate pad part and the common electrode is exposed, and forming the active pattern; Forming a metal wiring layer on the gate insulation layer including the gate insulating layer, selectively etching the metal wiring layer to form a source / drain electrode, and etching the n + amorphous silicon layer using the source / drain electrode as a mask Forming a protective layer on the gate insulating layer and the semiconductor layer including the source / drain electrodes; And assembling the upper substrate provided with the black matrix with the lower substrate such that the protective layer on the gate pad portion is opened, and injecting liquid crystal therebetween, and dry etching the protective layer and the gate insulating layer on the gate pad portion. It is made of a removing process, so that one mask can be reduced when manufacturing a thin film transistor, thereby simplifying a process, reducing costs, and improving yield.
Description
본 발명은 박막트랜지스터용 액정표시소자(thin film transistor liquid crystal display device:이하, TFT-LCD라 한다) 제조방법에 관한 것으로, 보다 상세하게는 공정 진행시 마스크 수를 1매 감소시켜 공정 단순화 및 수율 향상을 기할 수 있도록 한 IPS 모드(In-Plane Switching mode) TFT-LCD 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device (hereinafter referred to as TFT-LCD) for thin film transistor, and more particularly, to simplify the process and yield by reducing the number of masks by one sheet during the process. The present invention relates to an IPS mode (In-Plane Switching mode) TFT-LCD manufacturing method.
근래에 고품위 TV(high definition TV:이하, HDTV라 한다) 등의 새로운 첨단 영상기기가 개발됨에 따라 평판표시기에 대한 요구가 대두되고 있다. LCD는 평판표시기의 대표적인 기술로써 ELD(electro luminescence display), VFD(vacuum fluorescence display), PDP(plasma display panel) 등이 해결하지 못한 칼라화, 저전력, 그리고 고속화등의 문제를 가지고 있지 않다. 이 LCD는 크게 수동형과 능동형의 두가지 형태로 나누어지는데, 능동형 LCD는 각 화소 하나 하나를 TFT와 같은 능동소자가 제어하도록 되어 있어 속도, 시야각, 그리고 대조비(contrast)에 있어서, 수동형 LCD보다 훨씬 뛰어나 100만 화소 이상의 해상도를 필요로 하는 HDTV에 가장 적합한 표시기로 사용되고 있다. 이에 따라, TFT의 중요성이 부각되면서 이에 대한 연구개발이 심화되고 있다.Recently, with the development of new high-tech video devices such as high definition TVs (hereinafter referred to as HDTVs), there is a demand for flat panel displays. LCD is a representative technology of flat panel display, and it does not have problems such as colorization, low power, and high speed that ELD (electro luminescence display), VFD (vacuum fluorescence display), PDP (plasma display panel) cannot solve. The LCD is divided into two types, passive and active. The active LCD is controlled by an active element such as TFT to control each pixel one by one, which is far superior to the passive LCD in terms of speed, viewing angle, and contrast. It is used as the most suitable indicator for HDTV that requires more than 10,000 pixels of resolution. Accordingly, as the importance of TFTs is highlighted, R & D on them is intensifying.
특히, IPS 모드의 TFT-LCD는 TN(twist nematic) 액정에 의해 동작되는 TFT-LCD와는 달리 TFT 기판 위에 공통 전극(common electrode)을 게이트 금속을 이용하여 형성시켜 주므로, 칼라필터 기판에 ITO 전극을 따로 증착해 줄 필요가 없을 뿐 아니라 픽셀 ITO 전극이 필요없어, 보통 4매의 마스크를 가지고 TFT 제조가 이루어지고 있다. 이를 4단계로 구분하여 간략하게 살펴보면 다음과 같다.In particular, unlike the TFT-LCD which is operated by TN (twist nematic) liquid crystal, the TFT-LCD in the IPS mode forms a common electrode on the TFT substrate using a gate metal, so that an ITO electrode is formed on the color filter substrate. Not only does it need to be deposited separately, but no pixel ITO electrode is required, and TFT manufacturing is usually performed with four masks. This is briefly divided into four steps as follows.
제 1 단계로서, 유리 재질의 하부기판 상에 게이트 금속을 증착한 후, 제 1 마스크를 이용한 광식각 공정으로 상기 게이트 금속의 소정 부분을 선택식각하여 게이트 전극과 게이트 패드 및 공통 전극을 형성한다.In a first step, a gate metal is deposited on a lower substrate made of glass, and then a predetermined portion of the gate metal is selectively etched by a photoetch process using a first mask to form a gate electrode, a gate pad, and a common electrode.
제 2 단계로서, 상기 게이트 전극과 게이트 패드 및 공통 전극을 포함한 하부기판 전면에 액티브층으로서, 게이트 절연층(예컨대, SiNx층), 반도체층(예컨대, a-Si:H), n+ 비정질실리콘층(예컨대, n+ a-Si층)을 순차적으로 증착하고, 상기 게이트 패드와 그 주변부(이하, 게이트 패드부라 칭한다) 및 상기 공통전극과 그 주변부 상의 게이트 절연층 표면이 노출되도록, 제 2 마스크를 이용한 광식각 공정으로 상기 n+ 비정질실리콘층과 반도체층을 선택식각한다. 그 결과, 상기 게이트 전극 상에는 게이트 절연층, 반도체층, n+ 비정질실리콘층이 연속적으로 증착된 구조의 액티브 패턴이 형성된다.As a second step, a gate insulating layer (eg, SiNx layer), semiconductor layer (eg, a-Si: H), n + amorphous silicon layer as an active layer on the entire lower substrate including the gate electrode, the gate pad, and the common electrode. (E.g., an n + a-Si layer) are sequentially deposited and a second mask is used to expose the gate pad and its periphery (hereinafter referred to as the gate pad portion) and the surface of the gate insulating layer on the common electrode and its periphery. In the photolithography process, the n + amorphous silicon layer and the semiconductor layer are selectively etched. As a result, an active pattern having a structure in which a gate insulating layer, a semiconductor layer, and an n + amorphous silicon layer are continuously deposited is formed on the gate electrode.
제 3 단계로서, 상기 액티브 패턴을 포함한 게이트 절연층 상에 금속배선층을 증착하고, 제 3 마스크를 이용한 광식각 공정으로 상기 금속배선층의 소정 부분을 식각하여 데이터 라인(data line)으로 사용되어질 소오스/드레인 전극을 형성한 다음, 상기 소오스/드레인 전극을 마스크로하여 그 하부의 n+ 비정질실리콘층을 식각하여 반도체층의 표면이 소정 부분 노출되도록 한다.In a third step, a metal wiring layer is deposited on the gate insulating layer including the active pattern, and a portion of the metal wiring layer is etched by a photoetch process using a third mask to be used as a data line. After the drain electrode is formed, the n + amorphous silicon layer is etched using the source / drain electrode as a mask so that the surface of the semiconductor layer is partially exposed.
제 4 단계로서, 상기 소오스/드레인 전극을 포함한 반도체층 및 게이트 절연층 상에 보호층(예컨대, SiNx층)을 증착하고, 상기 게이트 패드부 표면을 오픈시키기 위하여 제 4 마스크를 이용한 광식각 공정으로 상기 보호층을 식각한 후, 이를 마스크로하여 그 하부의 게이트 절연층을 식각한다.In a fourth step, a protective layer (eg, a SiNx layer) is deposited on a semiconductor layer including the source / drain electrodes and a gate insulating layer, and an optical etching process using a fourth mask to open the gate pad part surface is performed. After the protective layer is etched, the gate insulating layer below is etched using the mask as a mask.
이후, 칼라필터 및 블랙매트릭스가 구비된 상부기판과 제 1 내지 제 4 단계를 거쳐 제조된 하부기판을 게이트 패드부가 오픈되도록 조립(assembly)하고, 그 사이에 액정을 주입한 뒤, 밀봉재를 사용하여 상기 상/하부 기판을 밀봉하므로써, 공정 진행을 완료한다.Subsequently, the upper substrate provided with the color filter and the black matrix and the lower substrate manufactured through the first to fourth steps are assembled to open the gate pad portion, the liquid crystal is injected therebetween, and then a sealing material is used. By sealing the upper and lower substrates, the process is completed.
그러나, 상기 공정을 이용하여 박막트랜지스터를 제조할 경우에는 공정 진행중 마스크를 이용한 식각공정이 5회(예컨대, 게이트 전극과 게이트 패드 및 공통전극 형성시, 액티브 패턴 형성시, 소오스/드레인 전극 형성시, 게이트 패드부 노출시) 요구되므로, 4매의 마스크가 필요로되어 제조원가 상승 및 수율 저하 등의 단점이 발생하게 된다.However, when the thin film transistor is manufactured using the above process, the etching process using the mask during the process is performed five times (for example, when the gate electrode, the gate pad and the common electrode are formed, the active pattern is formed, the source / drain electrode is formed, When the gate pad portion is exposed), four masks are required, resulting in disadvantages such as an increase in manufacturing cost and a decrease in yield.
이에 본 발명은 상기와 같은 단점을 개선하기 위하여 창안된 것으로, 박막트랜지스터 제조시 게이트 패드부 상의 보호층과 게이트 절연층을 상/하부 기판 조립후 건식식각법으로 제거해주므로써, 공정단순화 및 비용 절감을 실현할 수 있도록 한 IPS 모드 TFT-LCD 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention was devised to improve the above-mentioned disadvantages, and by removing the protective layer and the gate insulating layer on the gate pad part by dry etching after assembling the upper and lower substrates in manufacturing the thin film transistor, the process is simplified and the cost is reduced. It is an object of the present invention to provide a method for manufacturing an IPS mode TFT-LCD capable of realizing this.
도 1a 내지 도 1d는 본 발명에 의한 IPS 모드 박막트랜지스터용 액정표시소자 제조방법을 도시한 공정수순도.1A to 1D are process flowcharts showing a method for manufacturing a liquid crystal display device for an IPS mode thin film transistor according to the present invention.
상기와 같은 목적을 달성하기 위하여 본 발명에서는, 게이트 전극과 게이트 패드부 및 공통 전극이 구비되어 있는 하부기판 상에 게이트 절연층, 반도체층, n+ 비정질실리콘층을 증착하는 공정과, 상기 게이트 패드부 및 공통 전극 상의 게이트 절연층이 소정 부분 노출되도록, 상기 n+ 비정질실리콘층 및 반도체층을 식각하여 액티브 패턴을 형성하는 공정과, 상기 액티브 패턴을 포함한 게이트 절연층 상에 금속배선층을 형성하는 공정과, 상기 금속배선층을 선택식각하여 소오스/드레인 전극을 형성하는 공정과, 상기 소오스/드레인 전극을 마스크로 상기 n+ 비정질실리콘층을 식각하여 채널을 형성하는 공정과, 상기 소오스/드레인 전극을 포함한 게이트 절연층과 반도체층 상에 보호층을 형성하는 공정과, 칼라필터와 블랙매트릭스가 구비된 상부기판을 게이트 패드부 상의 보호층이 오픈되도록 상기 하부기판과 조립하고 그 사이에 액정을 주입하는 공정 및, 상기 게이트 패드부 상의 보호층과 게이트 절연층을 건식식각법으로 제거하는 공정으로 이루어진 것을 특징으로 하는 TFT-LCD 제조방법이 제공된다.In order to achieve the above object, in the present invention, a process of depositing a gate insulating layer, a semiconductor layer, an n + amorphous silicon layer on a lower substrate provided with a gate electrode, a gate pad portion and a common electrode, and the gate pad portion And etching the n + amorphous silicon layer and the semiconductor layer to form an active pattern so that the gate insulating layer on the common electrode is partially exposed, forming a metal wiring layer on the gate insulating layer including the active pattern; Selectively etching the metallization layer to form a source / drain electrode, etching the n + amorphous silicon layer using the source / drain electrode as a mask to form a channel, and a gate insulating layer including the source / drain electrode And forming a protective layer on the semiconductor layer, and an upper substrate provided with a color filter and a black matrix And assembling the lower substrate so that the protective layer on the gate pad part is opened and injecting liquid crystal therebetween, and removing the protective layer and the gate insulating layer on the gate pad part by dry etching. TFT-LCD manufacturing method is provided.
상기 공정 결과, 마스크 없이도 게이트 패드부 상의 보호층과 게이트 절연층을 제거할 수 있게 된다.As a result of this process, the protective layer and the gate insulating layer on the gate pad portion can be removed without a mask.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
본 발명은 IPS 모드 TFT-LCD 제조시, 게이트 패드부 상의 보호층과 게이트 절연층을 스위칭 소자 형성시 제거하지 않고, 상/하부기판 조립 후 밀봉 공정까지 완료된 상태에서 건식식각법을 이용하여 제거해주므로써, 공정 진행시 요구되던 마스크 1매를 줄일 수 있도록 하여 공정단순화 및 비용 절감을 실현할 수 있도록 하는데 주안점을 두 기술로서, 이를 도 1a 내지 도 1d에 제시된 공정수순도를 참조하여 구체적으로 살펴보면 다음과 같다.The present invention does not remove the protective layer on the gate pad portion and the gate insulating layer during the formation of the switching element in manufacturing the IPS mode TFT-LCD, but removes them by dry etching in the state of completing the sealing process after assembling the upper and lower substrates. Therefore, the main focus of the present invention is to reduce the amount of masks required in the process, thereby realizing process simplicity and cost reduction, and the two main techniques will be described in detail with reference to the process flow chart shown in FIGS. 1A to 1D. same.
제 1 단계로서, 도 1a에 도시된 바와 같이 유리 재질의 하부기판(10) 상에 게이트 금속을 증착한 후, 제 1 마스크를 이용한 광식각 공정으로 상기 게이트 금속을 선택식각하여 게이트 전극(12)과 게이트 패드(14) 및 공통 전극(16)을 동시에 형성한다.As a first step, as shown in FIG. 1A, the gate metal is deposited on the lower substrate 10 made of glass, and then the gate metal is selectively etched by a photoetch process using a first mask. And the gate pad 14 and the common electrode 16 are formed at the same time.
제 2 단계로서, 도 1b에 도시된 바와 같이 상기 게이트 전극(12)과 게이트 패드(14) 및 공통 전극(16)을 포함한 기판(10) 전면에 PECVD(plasma enhanced chemical vapour deposition)을 이용하여 액티브층으로서, 게이트 절연층(예컨대, SiNx층)(18), 반도체층(예컨대, a-Si:H)(20), n+ 비정질실리콘층(예컨대, n+ a-Si층)(22)을 순차적으로 증착한다. 이어, 상기 게이트 패드(14)와 그 주변부 및 상기 공통 전극(16)과 그 주변부 상의 게이트 절연층(18) 표면이 노출되도록, 제 2 마스크를 이용한 광식각 공정으로 상기 n+ 비정질실리콘층 및 반도체층을 선택식각한다. 그 결과, 상기 게이트 전극(12) 상에는 게이트 절연층(18), 반도체층(20), n+ 비정질실리콘층(22)이 연속적으로 증착된 구조의 액티브 패턴이 형성된다.As a second step, as shown in FIG. 1B, the substrate is active using plasma enhanced chemical vapor deposition (PECVD) on the entire surface of the substrate 10 including the gate electrode 12, the gate pad 14, and the common electrode 16. As the layer, a gate insulating layer (eg, SiNx layer) 18, a semiconductor layer (eg, a-Si: H) 20, and an n + amorphous silicon layer (eg, an n + a-Si layer) 22 are sequentially Deposit. Subsequently, the n + amorphous silicon layer and the semiconductor layer are subjected to a photoetch process using a second mask so that the gate pad 14, the peripheral portion thereof, and the surface of the common electrode 16 and the gate insulating layer 18 on the peripheral portion thereof are exposed. Select Etch. As a result, an active pattern having a structure in which the gate insulating layer 18, the semiconductor layer 20, and the n + amorphous silicon layer 22 are continuously deposited is formed on the gate electrode 12.
제 3 단계로서, 도 1c에 도시된 바와 같이 상기 액티브 패턴을 포함한 게이트 절연층(18) 상에 스퍼터링법으로 금속배선층을 증착하고, 제 3 마스크를 이용한 광식각 공정으로 상기 금속배선층의 소정 부분을 식각하여 데이터 라인(data line)으로 사용되어질 소오스/드레인 전극(24)을 형성한 다음, 상기 소오스/드레인 전극(24)을 마스크로하여 그 하부의 n+ 비정질실리콘층(22)을 식각하여 반도체층(20)의 표면이 소정 부분 노출되도록 한다.As a third step, as shown in FIG. 1C, a metal wiring layer is deposited on the gate insulating layer 18 including the active pattern by sputtering, and a predetermined portion of the metal wiring layer is removed by a photoetch process using a third mask. After etching, the source / drain electrode 24 to be used as a data line is formed, and then the n + amorphous silicon layer 22 is etched using the source / drain electrode 24 as a mask to etch the semiconductor layer. The surface of 20 is exposed to a predetermined portion.
제 4 단계로서, 도 1d에 도시된 바와 같이 상기 소오스/드레인 전극(24)을 포함한 반도체층 및 게이트 절연층 상에 보호층(예컨대, SiNx층)(26)을 증착한다. 이후, 칼라필터(미 도시) 및 블랙매트릭스(30)가 구비된 상부기판(28)과 제 1 내지 제 4 단계를 거쳐 제조된 하부기판(10)을 게이트 패드부가 오픈되도록 조립(assembly)하고, 그 사이에 액정(34)을 주입한 뒤, 밀봉재(32)를 사용하여 상기 상부/하부기판(28),(10)을 밀봉처리한 다음, 상기 게이트 패드부 상의 보호층(26) 및 게이트 절연막(18)을 건식식각법을 이용하여 제거해 주므로써, 공정 진행을 완료한다.As a fourth step, a protective layer (eg, a SiNx layer) 26 is deposited on the semiconductor layer including the source / drain electrodes 24 and the gate insulating layer as shown in FIG. 1D. Thereafter, the upper substrate 28 having the color filter (not shown) and the black matrix 30 and the lower substrate 10 manufactured through the first to fourth steps are assembled to open the gate pad part. After the liquid crystal 34 is injected therebetween, the upper / lower substrates 28 and 10 are sealed using a sealing material 32, and then the protective layer 26 and the gate insulating film on the gate pad portion are sealed. (18) is removed by dry etching to complete the process.
이와 같이 공정을 진행할 경우, TFT 제조시 게이트 패드부 상의 보호층(26) 과 게이트 절연층(18)을 마스크를 이용한 광식각 공정없이도 제거할 수 있게 되므로, 종래 공정 진행시 요구되던 4매의 마스크 수를 3매로 줄일 수 있게 되어 공정 단순화를 실현할 수 있게 된다.In this case, since the protective layer 26 and the gate insulating layer 18 on the gate pad portion can be removed without a photoetch process using a mask during TFT manufacturing, four masks required in the conventional process are required. The number of sheets can be reduced to three, so that the process can be simplified.
상술한 바와 같이 본 발명에 의하면, 기존에 4매의 마스크가 요구되어지던 박막트랜지스터 제조 공정을 3매의 마스크를 이용하여 실시할 수 있게 되므로, 공정 단순화를 실현할 수 있게 되어 비용 절감 및 수율 향상을 기할 수 있게 된다.As described above, according to the present invention, the thin film transistor manufacturing process, in which four masks were previously required, can be performed using three masks, so that process simplification can be realized, thereby reducing cost and improving yield. You will be able to.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970006888A KR100537020B1 (en) | 1997-03-03 | 1997-03-03 | Manufacturing Method of Liquid Crystal Display Device for IPS Mode Thin Film Transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970006888A KR100537020B1 (en) | 1997-03-03 | 1997-03-03 | Manufacturing Method of Liquid Crystal Display Device for IPS Mode Thin Film Transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980072232A true KR19980072232A (en) | 1998-11-05 |
| KR100537020B1 KR100537020B1 (en) | 2006-03-03 |
Family
ID=37179186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970006888A KR100537020B1 (en) | 1997-03-03 | 1997-03-03 | Manufacturing Method of Liquid Crystal Display Device for IPS Mode Thin Film Transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100537020B1 (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100561645B1 (en) * | 2003-10-13 | 2006-03-20 | 엘지.필립스 엘시디 주식회사 | Liquid Crystal Display Panel and Method of Fabricating the same |
| KR100556345B1 (en) * | 1998-11-24 | 2006-04-21 | 엘지.필립스 엘시디 주식회사 | A method of manufacturing in-plane switching mode liquid crystal display device |
| US7369202B2 (en) | 2003-10-14 | 2008-05-06 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display panel of horizontal electronic field applying type and fabricating method thereof |
| KR100864599B1 (en) * | 2000-03-17 | 2008-10-22 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method of manufacturing a liquid crystal display device |
| KR100869653B1 (en) * | 2000-03-16 | 2008-11-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Liquid crystal display device |
| US7714329B2 (en) | 2001-03-06 | 2010-05-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having thin film transistor |
| KR100971396B1 (en) * | 2003-10-28 | 2010-07-21 | 엘지디스플레이 주식회사 | The Method for Fabricating the LCD Device |
| KR101048698B1 (en) * | 2003-12-30 | 2011-07-12 | 엘지디스플레이 주식회사 | Liquid crystal display device and manufacturing method thereof |
| KR101067966B1 (en) * | 2003-12-29 | 2011-09-26 | 엘지디스플레이 주식회사 | In plane switching mode liquid crystal display device and method of fabricating thereof |
| KR101123452B1 (en) * | 2004-05-31 | 2012-03-26 | 엘지디스플레이 주식회사 | In Plane Switching Mode Liquid Crystal Display device and the fabrication method |
| US8144296B2 (en) | 2003-06-24 | 2012-03-27 | Lg Display Co., Ltd. | Method of fabricating array substrate for in-plane switching mode liquid crystal display device having double-layered metal patterns |
| KR101232547B1 (en) * | 2004-06-01 | 2013-02-12 | 엘지디스플레이 주식회사 | An array substrate for In-Plane-Switching mode LCD and the fabrication method thereof |
| US8576367B2 (en) | 2003-10-14 | 2013-11-05 | Lg Display Co., Ltd. | Liquid crystal display panel device with a transparent conductive film formed pixel electrode and gate pad and data pad on substrate and method of fabricating the same |
| US9048146B2 (en) | 2000-05-09 | 2015-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US9059045B2 (en) | 2000-03-08 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050105422A (en) | 2004-05-01 | 2005-11-04 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display panel and fabricating method thereof |
| KR20210154297A (en) | 2020-06-11 | 2021-12-21 | 삼성디스플레이 주식회사 | Pixel of an organic light emitting diode display device, and organic light emitting diode display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62183433A (en) * | 1986-02-07 | 1987-08-11 | Fujitsu Ltd | Production of active matrix liquid crystal display panel |
| KR950008931B1 (en) * | 1992-07-22 | 1995-08-09 | 삼성전자주식회사 | Manufacturing method of display pannel |
| JPH10325961A (en) * | 1994-03-17 | 1998-12-08 | Hitachi Ltd | Active matrix type liquid crystal display device |
| KR0141766B1 (en) * | 1994-04-18 | 1998-06-15 | 구자홍 | Manufacturing method of liquid crystal display elements |
| KR960024603A (en) * | 1994-12-22 | 1996-07-20 | 김광호 | Thin film transistor liquid crystal display device and manufacturing method thereof |
-
1997
- 1997-03-03 KR KR1019970006888A patent/KR100537020B1/en not_active IP Right Cessation
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100556345B1 (en) * | 1998-11-24 | 2006-04-21 | 엘지.필립스 엘시디 주식회사 | A method of manufacturing in-plane switching mode liquid crystal display device |
| US9368514B2 (en) | 2000-03-08 | 2016-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US9786687B2 (en) | 2000-03-08 | 2017-10-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US9059045B2 (en) | 2000-03-08 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| KR100869653B1 (en) * | 2000-03-16 | 2008-11-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Liquid crystal display device |
| KR100892575B1 (en) * | 2000-03-16 | 2009-04-08 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | A method of manufacturing a liquid crystal display device |
| US9298056B2 (en) | 2000-03-16 | 2016-03-29 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method of manufacturing the same |
| KR100864599B1 (en) * | 2000-03-17 | 2008-10-22 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method of manufacturing a liquid crystal display device |
| US9429807B2 (en) | 2000-05-09 | 2016-08-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US9048146B2 (en) | 2000-05-09 | 2015-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US7875886B2 (en) | 2001-03-06 | 2011-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a thin film transistor |
| US7714329B2 (en) | 2001-03-06 | 2010-05-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having thin film transistor |
| US8053781B2 (en) | 2001-03-06 | 2011-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having thin film transistor |
| US8614780B2 (en) | 2003-06-24 | 2013-12-24 | Lg Display Co., Ltd. | Array substrate for in-plane switching mode liquid crystal display device having double-layered metal patterns and method of fabricating the same |
| US8259272B2 (en) | 2003-06-24 | 2012-09-04 | Lg Display Co., Ltd. | Array substrate for in-plane switching mode liquid crystal display device having double-layered metal patterns and method of fabricating the same |
| US8373834B2 (en) | 2003-06-24 | 2013-02-12 | Lg Display Co., Ltd. | Array substrate for in-plane switching mode liquid crystal display device having double-layered metal patterns and method of fabricating the same |
| US8144296B2 (en) | 2003-06-24 | 2012-03-27 | Lg Display Co., Ltd. | Method of fabricating array substrate for in-plane switching mode liquid crystal display device having double-layered metal patterns |
| KR100561645B1 (en) * | 2003-10-13 | 2006-03-20 | 엘지.필립스 엘시디 주식회사 | Liquid Crystal Display Panel and Method of Fabricating the same |
| US8576367B2 (en) | 2003-10-14 | 2013-11-05 | Lg Display Co., Ltd. | Liquid crystal display panel device with a transparent conductive film formed pixel electrode and gate pad and data pad on substrate and method of fabricating the same |
| US7369202B2 (en) | 2003-10-14 | 2008-05-06 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display panel of horizontal electronic field applying type and fabricating method thereof |
| KR100971396B1 (en) * | 2003-10-28 | 2010-07-21 | 엘지디스플레이 주식회사 | The Method for Fabricating the LCD Device |
| KR101067966B1 (en) * | 2003-12-29 | 2011-09-26 | 엘지디스플레이 주식회사 | In plane switching mode liquid crystal display device and method of fabricating thereof |
| KR101048698B1 (en) * | 2003-12-30 | 2011-07-12 | 엘지디스플레이 주식회사 | Liquid crystal display device and manufacturing method thereof |
| KR101123452B1 (en) * | 2004-05-31 | 2012-03-26 | 엘지디스플레이 주식회사 | In Plane Switching Mode Liquid Crystal Display device and the fabrication method |
| KR101232547B1 (en) * | 2004-06-01 | 2013-02-12 | 엘지디스플레이 주식회사 | An array substrate for In-Plane-Switching mode LCD and the fabrication method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100537020B1 (en) | 2006-03-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100537020B1 (en) | Manufacturing Method of Liquid Crystal Display Device for IPS Mode Thin Film Transistor | |
| KR101335007B1 (en) | Array substrate of thin film transistor liquid crystal display and method for manufacturing the same | |
| CN100397223C (en) | Liquid crystal display device and fabricating method thereof | |
| US5874326A (en) | Method for fabricating thin film transistor | |
| JP2015525000A (en) | Thin film transistor, array substrate, manufacturing method thereof, display | |
| KR20040095045A (en) | Thin film transistor array substrate and fabricating method thereof | |
| JP2009139929A (en) | Thin film transistor substrate, liquid crystal display device including same, and its manufacturing method | |
| CN101825815A (en) | TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) array baseplate and manufacturing method thereof | |
| US9281325B2 (en) | Array substrate, manufacturing method thereof and display device | |
| US6876406B2 (en) | Structure for preventing disconnection in liquid crystal display device and manufacturing method thereof | |
| KR100546707B1 (en) | Tin Film Transistor and method for forming the same | |
| KR20040061292A (en) | A method of fabricating liquid crystal display device | |
| KR100922792B1 (en) | Method for manufacturing array substrate of the liquid crystal display device | |
| US6157431A (en) | Liquid crystal display apparatus suppressed of orientation defect having metal film and photosensitive resin as a columnar spacer and fabrication method thereof | |
| KR20070072275A (en) | Vertical alignment mode liquid crystal display device and method of fabricating thereof | |
| US6861671B2 (en) | Thin film transistor liquid crystal display and fabrication method thereof | |
| KR20020002516A (en) | Method for forming gate electrode in liquid crystal display device | |
| KR100928493B1 (en) | Formation method of thin film transistor | |
| KR101030523B1 (en) | method for manufacturing array substrate of the liquid crystal display device | |
| KR101060417B1 (en) | LCD and its manufacturing method | |
| KR20020077047A (en) | Flat panel display and method for forming the same | |
| KR100729770B1 (en) | Liquid crystal display device | |
| KR19980072230A (en) | Method of manufacturing thin film transistor | |
| KR20040036987A (en) | Thin film transistor array panel for liquid crystal display and manufacturing method of the same | |
| KR100375734B1 (en) | Method of manufacturing TFT array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| AMND | Amendment | ||
| E601 | Decision to refuse application | ||
| J201 | Request for trial against refusal decision | ||
| AMND | Amendment | ||
| E902 | Notification of reason for refusal | ||
| B701 | Decision to grant | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20121115 Year of fee payment: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20131129 Year of fee payment: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20141128 Year of fee payment: 10 |
|
| EXPY | Expiration of term |