KR19980046280A - Semiconductor package - Google Patents
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- Publication number
- KR19980046280A KR19980046280A KR1019960064594A KR19960064594A KR19980046280A KR 19980046280 A KR19980046280 A KR 19980046280A KR 1019960064594 A KR1019960064594 A KR 1019960064594A KR 19960064594 A KR19960064594 A KR 19960064594A KR 19980046280 A KR19980046280 A KR 19980046280A
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- South Korea
- Prior art keywords
- chip
- lead
- pad
- semiconductor package
- leads
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체 패키지에 관한 것으로, 종래에는 칩의 상면에 센타패드 형태로 1열로 형성하여 다수개의 리드를 설치하는 것이 한계가 있었으나, 본 발명에서는 칩(11)의 상면에 패드(12)를 2열로 형성하고, 그 패드(12)의 양측에 리드(4)를 설치함으로써 패드(12)의 면적과 리드(4)의 폭을 종래와 동일하게 하면서 다핀화가 가능한 효과가 있다.The present invention relates to a semiconductor package, and in the past, it was limited to install a plurality of leads by forming one row in the form of a center pad on the upper surface of the chip. However, in the present invention, the pad 12 is disposed on the upper surface of the chip 11. By forming the rows and providing the leads 4 on both sides of the pads 12, the area of the pads 12 and the widths of the leads 4 are the same as in the prior art, so that the pinning can be performed.
Description
본 발명은 반도체 패키지(PACKAGE)에 관한 것으로, 특히 패드(PAD)를 칩(CHIP)의 상면 양측에 2열로 형성함으로써 다핀화를 실현할 수 있도록 하는데 적합한 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package (PACKAGE), and more particularly to a semiconductor package suitable for realizing multi-pinning by forming the pad (PAD) in two rows on both sides of the upper surface of the chip (CHIP).
도 1은 종래 반도체 패키지의 구성을 보인 상면도 및 종단면도로서, 도시된 바와 같이, 종래 반도체 패키지는 반도체 칩(1)과, 그 칩(1)의 상면 중앙에 1열로 형성되어 있는 다수개의 패드(2)와, 상기 칩(1)의 상면 양측에 절연성양면테이프(3)로 부착되는 다수개의 리드(LEAD)(4)와, 상기 패드(2)와 리드(4)를 각각 전기적으로 연결하는 금속와이어(5)와, 상기 리드(4)의 상면을 외부로 노출시킴과 아울러 상기 칩(1), 금속와이어(5), 리드(4)의 일정부분을 감싸도록 에폭시(EPOXY)로 몰딩되어 있는 몰딩부(6)로 구성되어 있다.1 is a top view and a longitudinal cross-sectional view showing a configuration of a conventional semiconductor package. As shown in the drawing, a conventional semiconductor package includes a semiconductor chip 1 and a plurality of pads formed in one row at the center of the upper surface of the chip 1. (2) and a plurality of leads (LEAD) 4 attached to both sides of the upper surface of the chip 1 by the insulating double-sided tape (3), and the pad (2) and the lead (4) electrically connected to each other The metal wire 5 and the upper surface of the lead 4 are exposed to the outside and molded with epoxy to surround a portion of the chip 1, the metal wire 5, and the lead 4. It consists of the molding part 6 which exists.
이와 같이 구성되어 있는 종래 반도체 패키지는 반도체 칩(1)의 상면 양측에 절연성양면테이프(3)를 이용하여 다수개의 리드(4)를 부착하고, 그 리드(4)와 상기 칩(1)의 상면 중앙에 1열로 형성되어 있는 다수개의 패드(2)를 각각 금속와이어(5)로 연결하는 와이어본딩(WIRE BONDING)을 실시하며, 상기 리드(4)의 상면을 외부로 노출시킴과 아울러 상기 칩(1), 금속와이어(5), 리드(4)의 일정부분을 감싸도록 에폭시로 몰딩(MOLDING)하여 몰딩부(6)를 형성하여 패키지를 완성한다.In the conventional semiconductor package configured as described above, a plurality of leads 4 are attached to both sides of the upper surface of the semiconductor chip 1 by using an insulating double-sided tape 3, and the leads 4 and the upper surface of the chip 1 are attached. Wire bonding is performed to connect the plurality of pads 2 formed in one row at the center with metal wires 5, respectively, and expose the upper surface of the lead 4 to the outside, and the chip ( 1), the metal wire (5), the molding (MOLDING) with epoxy so as to surround a portion of the lead (4) to form a molding portion 6 to complete the package.
그러나, 상기와 같이 구성되는 종래 반도체 패키지는 패드(2)가 칩(1)의 상면 중앙부분에 1열로 형성되어 있어서, 리드(4)의 수를 늘려서 다핀화를 구성하는데 한계가 있는 문제점이 있었다. 즉, 패드(2)가 중앙에 있는 상태에서의 다핀화를 실현하기 위해서는 패드(2)의 크기를 작게하고 리드(4)의 폭을 미세하게 하여야 하는데, 이와 같이 패드(2)와 리드(4)의 크기를 작게하는 것은 한계가 있는 것이다.However, the conventional semiconductor package configured as described above has a problem in that the pads 2 are formed in one row at the center of the upper surface of the chip 1, thereby increasing the number of leads 4 to form the multi-pinning. . That is, in order to realize the multi-pinning in the state where the pad 2 is in the center, the size of the pad 2 should be made small and the width of the lead 4 should be made fine. Reducing the size of) is limited.
상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 패키지의 다핀화를 실현할 수 있도록 하는데 적합한 반도체 패키지를 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention devised in view of the above problems is to provide a semiconductor package suitable for realizing multi-pinning of a package.
도 1은 종래 반도체 패키지의 구성을 보인 상면도 및 종단면도.1 is a top view and a longitudinal cross-sectional view showing a configuration of a conventional semiconductor package.
도 2는 본 발명 반도체 패키지의 구성을 보인 상면도 및 종단면도.Figure 2 is a top view and a longitudinal cross-sectional view showing the configuration of the semiconductor package of the present invention.
도 3는 본 발명 반도체 패키지가 실장된 상태를 보인 종단면도.Figure 3 is a longitudinal sectional view showing a state in which the semiconductor package of the present invention is mounted.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 칩12 : 패드11: chip 12: pad
13 : 절연성양면테이프14 : 리드13: insulating double-sided tape 14: lead
15 : 금속와이어16 : 몰딩부15 metal wire 16: molding part
상기와 같은 본 발명의 목적을 달성하기 위하여 반도체 칩과, 그 칩의 상면 양측에 2열로 형성되는 패드와, 상기 패드의 양측에 각각 나열설치되며 칩의 상면에 절연성양면테이프로 접착고정되는 다수개의 리드와, 그 리드와 상기 패드를 각각 전기적으로 연결하는 금속와이어와, 상기 리드의 상면을 외부로 노출시킴과 아울러 상기 칩, 금속와이어, 리드의 일정부분을 감싸도록 에폭시로 몰딩되는 몰딩부를 구비하여서 구성되는 것을 특징으로 반도체 패키지가 제공된다.In order to achieve the object of the present invention as described above, a plurality of semiconductor chips, pads formed in two rows on both sides of the upper surface of the chip, and arranged on both sides of the pads and adhered and fixed by insulating double-sided tape on the upper surface of the chip A lead, a metal wire electrically connecting the lead and the pad, respectively, and an upper part of the lead exposed to the outside, and a molding part formed of epoxy to cover the chip, the metal wire, and a portion of the lead. A semiconductor package is provided, which is configured.
이하, 상기와 같이 구성되는 본 발명 반도체 패키지의 구성을 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the configuration of the semiconductor package according to the present invention configured as described above will be described in detail with reference to embodiments of the accompanying drawings.
도 2는 본 발명 반도체 패키지의 구성을 보인 상면도 및 종단면도로서, 도시된 바와 같이, 본 발명 반도체 패키지는 반도체 칩(11)과, 그 칩(11)의 상면 양측에 2열로 형성되며 칩(11)의 외부연결단자가 되는 다수개의 패드(12)와, 그 패드(12)의 양측에 설치되며 칩(11)의 상면에 절연성양면테이프(13)으로 고정부착되는 다수개의 리드(14)와, 상기 패드(12)와 리드(14)를 각각 전기적으로 연결하는 금속와이어(15)와, 상기 리드(14)의 상면을 외부로 노출시킴과 아울러 상기 칩(11), 패드(12), 금속와이어(15), 리드(14)의 일정부분을 감싸도록 에폭시로 몰딩되는 몰딩부(16)로 구성된다.2 is a top view and a longitudinal cross-sectional view showing the configuration of a semiconductor package of the present invention. As shown in the drawing, the semiconductor package of the present invention is formed in two rows on both sides of the semiconductor chip 11 and the top surface of the chip 11. A plurality of pads 12 serving as external connection terminals of the 11 and a plurality of leads 14 installed on both sides of the pads 12 and fixed to the upper surface of the chip 11 with an insulating double-sided tape 13. The metal wire 15 electrically connecting the pad 12 and the lead 14 to each other, and the top surface of the lead 14 are exposed to the outside, and the chip 11, the pad 12, and the metal are exposed to the outside. The wire 15 is composed of a molding part 16 molded with epoxy to surround a portion of the lead 14.
즉, 종래에는 칩(1)의 상면에 센타패드(CNETER PAD) 형태로 1열로 형성하여 다수개의 리드(4)를 설치하는 것이 불가능하였으나, 본 발명에서는 칩(11)의 상면에 패드(12)를 2열로 형성하고, 그 패드(12)의 양측에 리드(4)를 설치함으로써 패드(12)의 면적과 리드(4)의 폭(WIDTH)을 종래와 동일하게 하면서 다핀화가 가능한 것이다.That is, in the related art, it is impossible to install a plurality of leads 4 by forming one row in the form of a center pad on the top surface of the chip 1, but in the present invention, the pad 12 is disposed on the top surface of the chip 11. Is formed in two rows, and by providing the leads 4 on both sides of the pad 12, the pin 12 can be made multi-pinned while making the area of the pad 12 and the width WIDTH of the lead 4 the same as before.
상기와 같이 구성되는 본 발명 반도체 패키지의 제조방법을 설명하면 다음과 같다.Referring to the manufacturing method of the semiconductor package of the present invention configured as described above are as follows.
먼저, 상기 반도체 칩(11)의 상면에 2열로 다수개의 패드(12)를 형성한다. 그런 다음 그 패드(12)의 양측에 다수개의 리드(14)를 절연성양면테이프(13)으로 고정부착한다. 그런 다음, 상기 리드(14)와 상기 패드(12)를 금속와이어(15)로 연결하는 와이어 본딩을 실시한다. 그런 다음, 마지막으로 상기 다수개의 리드(14) 상면을 외부로 노출시킴과 아울러 상기 칩(11), 패드(12), 금속와이어(15), 리드(14)의 일정부분을 감싸도록 에폭시로 몰딩하여 몰딩부(16)를 형성하는 몰딩공정을 실시하여 완성한다.First, a plurality of pads 12 are formed in two rows on an upper surface of the semiconductor chip 11. Then, a plurality of leads 14 are fixedly attached to both sides of the pad 12 with an insulating double-sided tape 13. Then, wire bonding is performed to connect the lead 14 and the pad 12 with a metal wire 15. Then, finally, the upper surface of the plurality of leads 14 are exposed to the outside, and molded with epoxy to cover a portion of the chip 11, the pad 12, the metal wire 15, and the lead 14. By the molding process to form the molding unit 16 is completed.
그리고, 상기 패드(12)를 2열로 형성하는 방법은 통상의 적층배선을 하는 방법으로 메탈라인을 필요한 장소로 연장형성하고, 그 상면에 절연막을 형성하며, 패드형성부를 에칭하는 방법으로 형성한다.In the method of forming the pads 12 in two rows, a metal line is extended to a required place by a normal lamination method, an insulating film is formed on the upper surface thereof, and the pad forming part is etched.
상기와 같이 구성되는 패키지(P)는 뒤집어서 도 3와 같이 인쇄회로기판(20)의 상면에 솔더(21)를 이용하여 상기 노출된 리드(14)를 고정부착함으로써 실장하여 사용하게 된다.The package P configured as described above is turned upside down and fixed by attaching the exposed lead 14 using the solder 21 to the upper surface of the printed circuit board 20 as shown in FIG. 3.
이상에서 상세히 설명한 바와 같이 본 발명 반도체 패키지는 반도체 칩의 상면에 2열로 다수개의 패드를 형성하고, 그 패드의 양측에 다수개의 리드를 설치함으로써, 종래 보다 패드와 리드의 크기를 작게하지 않으면서도 2배로 리드수를 늘일 수 있게 되어 다핀화를 실현할 수 있는 효과가 있다.As described in detail above, in the semiconductor package according to the present invention, a plurality of pads are formed in two rows on an upper surface of a semiconductor chip, and a plurality of leads are provided on both sides of the pad, thereby reducing the size of the pads and the leads as compared to the prior art. Since the number of leads can be increased by double, there is an effect that the pinning can be realized.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960064594A KR100206975B1 (en) | 1996-12-12 | 1996-12-12 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960064594A KR100206975B1 (en) | 1996-12-12 | 1996-12-12 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980046280A true KR19980046280A (en) | 1998-09-15 |
| KR100206975B1 KR100206975B1 (en) | 1999-07-01 |
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ID=19487364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960064594A KR100206975B1 (en) | 1996-12-12 | 1996-12-12 | Semiconductor package |
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| Country | Link |
|---|---|
| KR (1) | KR100206975B1 (en) |
-
1996
- 1996-12-12 KR KR1019960064594A patent/KR100206975B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR100206975B1 (en) | 1999-07-01 |
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