KR19980038873A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR19980038873A KR19980038873A KR1019960057813A KR19960057813A KR19980038873A KR 19980038873 A KR19980038873 A KR 19980038873A KR 1019960057813 A KR1019960057813 A KR 1019960057813A KR 19960057813 A KR19960057813 A KR 19960057813A KR 19980038873 A KR19980038873 A KR 19980038873A
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- South Korea
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- film
- gate insulating
- oxide film
- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 20
- 239000007789 gas Substances 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 17
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 5
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 5
- 229910052731 fluorine Inorganic materials 0.000 description 5
- 239000011737 fluorine Substances 0.000 description 5
- 230000002265 prevention Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Chemical group 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000510 noble metal Chemical group 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical group [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Chemical group 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
Abstract
본 발명은 게이트 절연막을 다층 구조로 형성하여 게이트 절연막의 열화를 방지할 수 있는 반도체 소자의 제조방법에 관한 것으로, 반도체 기판 상에 열산화막, 완충 산화막 및 확산 방지막이 순차적을 적층된 게이트 절연막을 형성하는 단계, 게이트 절연막 상에 폴리실리콘막 및 텅스텐 실리사이드막을 순차적으로 형성하는 단계 및 텅스텐 실리사이드막과 폴리실리콘막 및 게이트 절연막을 식각하여 게이트 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method of manufacturing a semiconductor device capable of preventing the deterioration of the gate insulating film by forming a gate insulating film in a multi-layer structure, the gate insulating film in which a thermal oxide film, a buffer oxide film and a diffusion barrier film are sequentially stacked on the semiconductor substrate And sequentially forming a polysilicon film and a tungsten silicide film on the gate insulating film, and etching the tungsten silicide film, the polysilicon film, and the gate insulating film to form a gate electrode.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 게이트 절연막의 열화를 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to provide a method for manufacturing a semiconductor device capable of preventing deterioration of a gate insulating film.
대부분의 집적회로에서 낮은 비저항과 고온의 안정도를 가지는 금속 실리사이드가 접촉 재료로서 사용된다. 실리사이드는 고유의 조성과 각기의 화학적 성질을 갖는 금속-실리콘 화합물이다. 상기 금속은 내화성 금속족인 몰리브덴, 탄타륨, 티타늄, 텅스텐 또는 귀금속 원자인 코발트, 니켈, 백금 등과 반응한 화합물로 구성된다.In most integrated circuits, metal silicides having low resistivity and high temperature stability are used as contact materials. Silicides are metal-silicon compounds with inherent composition and respective chemical properties. The metal is composed of a compound reacted with molybdenum, tantalum, titanium, tungsten or a noble metal atom such as cobalt, nickel, platinum and the like.
한편, 상기 게이트 전극용 재료로 각광을 받고 있는 실리사이드 물질은 텅스텐 실리사이드(WSi2)로서, 폴리실리콘에 비해 낮은 비저항과 고온에서의 안정도를갖는 장점이 있다. 반면, 텅스텐 실리사이드는 산화막과의 접착력이 나쁘기 때문에, 대부분의 게이트 전극은 폴리실리콘막과 텅스텐 실리사이드가 적층된 폴리사이드 구조로 형성된다.Meanwhile, the silicide material, which has been spotlighted as the gate electrode material, is tungsten silicide (WSi 2 ), which has advantages of low specific resistance and stability at high temperature compared to polysilicon. On the other hand, since tungsten silicide has poor adhesion to an oxide film, most gate electrodes are formed of a polyside structure in which a polysilicon film and tungsten silicide are laminated.
이하, 상기한 폴리사이드 구조의 게이트 전극의 제조방법을 도 1A 내지 도 1B를 참조하여 설명한다.Hereinafter, a method of manufacturing the gate electrode having the polyside structure will be described with reference to FIGS. 1A to 1B.
먼저, 도 1A에 도시된 바와 같이, 반도체 기판(11) 상에 소정 두께의 게이트 산화막(12) 및 도핑된 폴리실리콘막(13)을 순차적으로 형성한다. 이어서, WF6및 SiH4의 화학반응을 이용하여 폴리실리콘막(13) 상부에 텅스텐 실리사이드막(14)을 형성한다. 그리고, 텅스텐 실리사이드막(14) 상에 포토리소그라피 공정에 의한 난반사를 방지하기 위한 난반사 방지막(15)을 형성한다.First, as shown in FIG. 1A, a gate oxide film 12 and a doped polysilicon film 13 having a predetermined thickness are sequentially formed on the semiconductor substrate 11. Subsequently, a tungsten silicide film 14 is formed on the polysilicon film 13 by using a chemical reaction of WF 6 and SiH 4 . Then, the diffuse reflection prevention film 15 for preventing the diffuse reflection by the photolithography process is formed on the tungsten silicide film 14.
도 1B에 도시된 바와 같이, 난반사 방지막(15) 상부에 포토리소그라피 공정으로 마스크 패턴(도시되지 않음)을 형성한다. 상기 마스크 패턴을 이용하여 하부의 난반사 방지막(15), 텅스텐 실리사이드막(14), 폴리실리콘막(l3) 및 게이트 산화막(12)을 식각하여 게이트 전극을 형성한다.As shown in FIG. 1B, a mask pattern (not shown) is formed on the diffuse reflection prevention film 15 by a photolithography process. A gate electrode is formed by etching the lower antireflection film 15, the tungsten silicide film 14, the polysilicon film l3, and the gate oxide film 12 using the mask pattern.
그러나, 상기한 방법으로 게이트 전극을 형성한 후, 열처리 공정을 실시하게되는데, 이때 텅스텐 실리사이드막(14)에 함유되어 있던 불소(F)가 상기 열처리 공정에 의해 확산되어 게이트 산화막(12)과 폴리실리콘막(13)의 계면에 모이게 된다.However, after the gate electrode is formed by the above-described method, a heat treatment process is performed. At this time, fluorine (F) contained in the tungsten silicide film 14 is diffused by the heat treatment process, and the gate oxide film 12 and the poly The silicon film 13 is collected at the interface.
그리고, 계면에 모인 불소는 실리콘과 산소의 결합(Si-0)을 깨고, 실리콘과 결합하여 실리콘과 불소의 결합(Si-F)을 이룬다. 이에 따라, 게이트 산화막(12)의 특성이 열화되어 결국 소자의 신뢰성을 저하시키는 문제가 발생한다.In addition, the fluorine collected at the interface breaks the bond between silicon and oxygen (Si-0) and combines with silicon to form a bond between silicon and fluorine (Si-F). As a result, the characteristics of the gate oxide film 12 deteriorate, resulting in a problem of lowering the reliability of the device.
이에, 본 발명은 상기한 문제점을 감안하여 창출된 것으로서, 게이트 절연막을 열산화막, CVD 산화막 및 CVD 질화막이 적층된 다층 구조로 형성함으로써 게이트 절연막의 열화를 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made in view of the above problems, and provides a method of manufacturing a semiconductor device capable of preventing the deterioration of the gate insulating film by forming the gate insulating film in a multilayer structure in which a thermal oxide film, a CVD oxide film, and a CVD nitride film are laminated. Has its purpose.
도 1A 및 도 1B는 종래의 폴리사이드 구조의 게이트 형성방법을 설명하기 위한 공정 단면도.1A and 1B are cross-sectional views for explaining a gate forming method of a conventional polyside structure.
도 2A 내지 도 2C는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위하여 순차적으로 나타낸 공정 단면도.2A through 2C are cross-sectional views sequentially illustrating the method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 열산화막21 semiconductor substrate 22 thermal oxide film
23 : CVD 산화막 24 : CVD 질화막23: CVD oxide film 24: CVD nitride film
25 : 폴리실리콘막 26 : 텅스텐 실리사이드막25 polysilicon film 26 tungsten silicide film
27 : 난반사 방지막27: diffuse reflection prevention film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 반도체 기판 상에 열산화막, 완층 산화막 및 확산 방지막이 순차적으로 적층된 게이트 절연막을 형성하는 단계, 상기 게이트 절연막 상에 폴리실리콘막 및 텅스텐 실리사이드막을 순차적으로 형성하는 단계 및, 상기 텅스텐 실리사이드막과 폴리실리콘막 및 게이트 절연막을 식각하여 게이트 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a gate insulating film in which a thermal oxide film, a complete oxide film, and a diffusion barrier film are sequentially stacked on a semiconductor substrate; and a polysilicon film and tungsten on the gate insulating film. And sequentially forming the silicide layer, and etching the tungsten silicide layer, the polysilicon layer, and the gate insulating layer to form a gate electrode.
상기 구성으로 된 본 발명에 의하면, 상기 게이트 전극의 형성 이후의 후속열처리 공정에서 텅스텐 실리사이드막으로부터 불소의 확산이 발생하더라도, 상기 확산 방지막에 의해 확산이 방지됨으로써, 게이트 절연막의 열화를 방지할 수 있다.According to the present invention having the above structure, even if fluorine is diffused from the tungsten silicide film in the subsequent heat treatment step after formation of the gate electrode, diffusion is prevented by the diffusion preventing film, thereby preventing deterioration of the gate insulating film. .
[실시예]EXAMPLE
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2A 내지 도 2C는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 개략적으로 나타낸 공정 단면도이다.2A to 2C are cross-sectional views schematically illustrating a method for forming a gate of a semiconductor device according to an embodiment of the present invention.
도 2A에 도시된 바와 같이, 반도체 기판(21) 상에 약 750 내지 850℃의 온도에서 산소(O2) 및 수소(H2) 개스를 이용하여 열산화막(22)을 형성한다. 이어서, 열산화막(22) 상부에 이후 형성될 CVD 질화막과 열산화막(22) 사이의 스트레스를 완충시키기 위한 완충 산화막으로서, 약 650 내지 750℃의 온도에서 약 10 내지 100cc/min의 TEOS(Tetra-Ethyl-Ortho-Silicate) 개스를 이용하여 CVD(Chemical Vapor Deposition) 산화막(23)을 형성한 다음, 약 850 내지 950℃의 온도와 질소(N2) 개스에서 열처리를 실시한다.As shown in FIG. 2A, a thermal oxide film 22 is formed on the semiconductor substrate 21 using oxygen (O 2 ) and hydrogen (H 2 ) gases at a temperature of about 750 to 850 ° C. Subsequently, as a buffer oxide film for buffering the stress between the CVD nitride film and the thermal oxide film 22 to be formed later on the thermal oxide film 22, a TEOS (Tetra-) of about 10 to 100 cc / min at a temperature of about 650 to 750 캜 A chemical vapor deposition (CVD) oxide film 23 is formed using an ethyl-ortho-silicate gas, and then heat-treated at a temperature of about 850 to 950 ° C. and a nitrogen (N 2 ) gas.
그리고 나서, CVD 산화막(23) 상부에 약 1,000 내지 l,200℃의 온도에서 약8 내지 12cc/min의 질소(N2) 개스와 약 3 내지 5cc/min의 산화질소(N2O) 개스를 이용하여 확산 방지막으로 작용할 CVD 질화막(24)을 형성한다. 이때, CVD 질화막(24)의 형성은 상기 산화질소 개스의 완전한 분해에 의해 상기 CVD 산화막(23)의 표면이 질화되도록 하기 위하여 고온에서 실시한다. 이에 따라, 열산화막(22), CVD 산화막(23) 및 CVD 질화막(24)이 순차적으로 적층된 다층 구조의 게이트 절연막을 완성하게 되는데, 상기 다층 구조의 게이트 절연막은 70 내지 100Å의 두께로 형성한다.Then, about 8 to 12 cc / min of nitrogen (N 2 ) gas and about 3 to 5 cc / min of nitric oxide (N 2 O) gas are deposited on the CVD oxide film 23 at a temperature of about 1,000 to 1,200 ° C. To form a CVD nitride film 24 to act as a diffusion barrier. At this time, the formation of the CVD nitride film 24 is performed at high temperature so that the surface of the CVD oxide film 23 is nitrided by the complete decomposition of the nitrogen oxide gas. As a result, a multi-layer gate insulating film in which the thermal oxide film 22, the CVD oxide film 23, and the CVD nitride film 24 are sequentially stacked is completed. The gate insulating film of the multilayer structure is formed to a thickness of 70 to 100 GPa. .
도 2B에 도시된 바와 같이, CVD 질화막(24) 상부에 도핑된 폴리실리콘막(25)을 형성하고, 폴리실리콘막(25) 상부에 WF6및 SiH4개스의 화학 반응을 이용하여, 텅스텐 실리사이드막(26)을 형성한다. 그리고 나서, 텅스텐 실리사이드막(26) 상에 포토리소그라피 공정에 의한 난반사를 방지하기 위하여 TiN 또는 옥시나이트라이드막을 난반사 방지막(27)으로서 형성한다.As shown in FIG. 2B, a doped polysilicon film 25 is formed on the CVD nitride film 24, and tungsten silicide is formed by using a chemical reaction of WF 6 and SiH 4 gas on the polysilicon film 25. A film 26 is formed. Then, a TiN or oxynitride film is formed as the antireflection film 27 on the tungsten silicide film 26 to prevent diffuse reflection by the photolithography process.
도 2C에 도시된 바와 같이, 난반사 방지막(27) 상부에 포토리소그라피 공정으로 마스크 패턴(도시되지 않음)을 형성한다. 상기 마스크 패턴을 이용하여 열산화막(22)이 노출되도록 하부의 난반사 방지막(27), 텅스텐 실리사이드막(26), 폴리실리콘막(25), CVD 질화막(24), CVD 산화막(23)을 식각하여 게이트 전극을 형성한다.As shown in FIG. 2C, a mask pattern (not shown) is formed on the diffuse reflection prevention film 27 by a photolithography process. By using the mask pattern, the lower diffuse reflection prevention layer 27, the tungsten silicide layer 26, the polysilicon layer 25, the CVD nitride layer 24, and the CVD oxide layer 23 are etched to expose the thermal oxide layer 22. A gate electrode is formed.
상기한 실시에에 의하면, 상기 게이트 전극의 형성 이후의 후속 열처리 공정에서 텅스텐 실리사이드막으로부터 불소의 확산이 발생하더라도, 상기 CVD 질화막에 의해 확산이 방지되으로써, 게이트 절연막의 열화를 방지할 수 있다. 이에 따라, 소자의 신뢰성을 향상시킬 수 있다.According to the above embodiment, even if fluorine is diffused from the tungsten silicide film in the subsequent heat treatment step after the formation of the gate electrode, diffusion is prevented by the CVD nitride film, thereby preventing deterioration of the gate insulating film. As a result, the reliability of the device can be improved.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
이상 설명한 바와 같이 본 발명에 의하면, 게이트 절연막의 열화를 방지할 수 있는 반도체 소자의 제조방법을 실현할 수 있게 된다.As described above, according to the present invention, it is possible to realize a method for manufacturing a semiconductor element which can prevent deterioration of the gate insulating film.
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| KR20030054669A (en) * | 2001-12-26 | 2003-07-02 | 주식회사 하이닉스반도체 | Method for forming a metal line |
| KR100403671B1 (en) * | 2000-02-11 | 2003-10-30 | 인터내셔널 비지네스 머신즈 코포레이션 | Diffusion barrier layer and semiconductor device containing same |
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| KR101050875B1 (en) * | 2005-09-23 | 2011-07-20 | 충북대학교 산학협력단 | Manufacturing method of single electron nano device and accordingly single electron nano device |
| KR100687410B1 (en) * | 2005-12-28 | 2007-02-26 | 동부일렉트로닉스 주식회사 | Method of forming the gate oxide in semiconductor device |
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| JPH05198821A (en) * | 1992-01-21 | 1993-08-06 | Kawasaki Steel Corp | Method of manufacturing semiconductor nonvolatile storage device |
| JP3436315B2 (en) * | 1992-03-31 | 2003-08-11 | 川崎マイクロエレクトロニクス株式会社 | Method of manufacturing MONOS type semiconductor nonvolatile memory device and method of manufacturing semiconductor device |
| JPH05343694A (en) * | 1992-06-05 | 1993-12-24 | Citizen Watch Co Ltd | Manufacture of nonvolatile semiconductor storage element |
| KR0135223B1 (en) * | 1994-09-08 | 1998-04-25 | 김주용 | Fabrication method of gate electrode in semiconductor device |
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| KR20030054669A (en) * | 2001-12-26 | 2003-07-02 | 주식회사 하이닉스반도체 | Method for forming a metal line |
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