KR102000759B1 - Adaptive bias circuit and power amplifier - Google Patents

Abstract

The present invention relates to an adaptive bias circuit and a power amplifier, wherein the bias circuit includes: an envelope detector for detecting an envelope of an input signal; A source voltage generator for generating a source voltage using a power supply voltage; And an envelope amplifier amplifying the envelope signal detected by the envelope detector to generate a first bias voltage by receiving the power supply voltage and the source voltage as a driving voltage. . ≪ / RTI >

Description

[0001] ADAPTIVE BIAS CIRCUIT AND POWER AMPLIFIER [0002]

The present invention relates to an adaptive bias circuit and a power amplifier.

Gradually, a wireless transceiver capable of transmitting / receiving a large amount of information due to the development of the information technology industry is required. In addition, a low-cost and low-power, high-performance wireless transceiver is required.

In such a wireless transceiver, most of the internal circuit blocks are integrated into a single chip using CMOS (Complementary Metal Oxide Semiconductor) process technology. However, due to the problem of CMOS process technology, It is implemented using InGaP (Indium Gallium Phosphide) / GaAs (Gallium Arsenide) HBT (Heterojunction Bipolar Transistor) process technology.

The compound semiconductor process technology such as the InGAP / GaAs HBT described above has a high manufacturing cost compared to the CMOS process technology and has to be formed in a multi-chip structure, and it is also difficult to be combined with a circuit block implemented in a CMOS process have. For this reason, there is a limitation in reducing the production cost of the radio transceiver. Therefore, research on a power amplifier based on a CMOS process is required.

Also, with the progress of high integration of wireless transceivers, it is required to integrate transmission and reception ends and integration with a front end stage. Accordingly, in order to realize a single system-on-chip (SoC), it is required that all the bias of the power amplifier be stabilized.

On the other hand, in a bias circuit for providing a bias voltage to a conventional power amplifier, an adaptive bias circuit capable of adjusting a bias voltage according to an envelope of an input signal is used.

Such an adaptive bias circuit includes an envelope amplifier circuit for detecting and amplifying an envelope of an input signal. The envelope amplifier circuit includes an envelope amplifier circuit, which is connected between a terminal supplied with a power supply voltage VDD and a terminal supplied with a source voltage VS, stacked transistors.

Since VDD and VS are supplied using a separate power supply circuit external to the power amplifier, the circuit is complicated and can be influenced from the outside, so that the source voltage may be fluctuated due to external influences, When the source voltage fluctuates, the operation of the envelope amplifier circuit sensitive to variations in the source voltage becomes unstable.

Patent Document 1 described in the following prior art document relates to an amplifier using a dynamic bias and does not disclose a technique for providing a source voltage of a bias circuit by using a power supply voltage of a bias circuit for stabilizing a bias voltage.

Japanese Patent Application Laid-Open No. 2013-123237

SUMMARY OF THE INVENTION The present invention provides a bias circuit and a power amplifier for providing a source voltage of a bias circuit using a power supply voltage of a bias circuit for stabilizing a bias voltage.

According to a first technical aspect of the present invention, the present invention provides an apparatus comprising: an envelope detector for detecting an envelope of an input signal; A source voltage generator for generating a source voltage using a power supply voltage; And an envelope amplifier amplifying the envelope signal detected by the envelope detector to generate a first bias voltage by receiving the power supply voltage and the source voltage as a driving voltage. And an adaptive bias circuit.

According to a second technical aspect of the present invention, the present invention also provides an envelope detection unit for detecting an envelope of an input signal; A source voltage generator for generating a source voltage using a power supply voltage; An envelope amplifier amplifying the envelope signal detected by the envelope detector to generate a first bias voltage by receiving the power supply voltage and the source voltage as a driving voltage; And an output distributor for stabilizing the first bias voltage; And an adaptive bias circuit.

In the first and second technical aspects of the present invention, the source voltage generator includes a current mirror circuit for generating a first current between the power supply voltage and ground, and for current mirroring the first current to generate a second current, ; And a voltage generation circuit for generating the source voltage by the resistance of the semiconductor element and the second current; . ≪ / RTI >

The current mirror circuit comprising: a first PMOS transistor having a source coupled to the power supply voltage terminal, a gate and a drain coupled to each other; A first NMOS transistor having a drain coupled to the drain of the first PMOS transistor of the current mirror circuit, a gate supplied with the control voltage, and a source coupled to ground; And a second PMOS transistor having a source coupled to the supply voltage terminal, a gate coupled to a gate of the first PMOS transistor, and a drain providing the second current; . ≪ / RTI >

A second NMOS transistor having a drain connected to the drain and source voltage terminals of the second PMOS transistor of the current mirror circuit, a gate supplied with the power supply voltage, and a source connected to the ground; And a stabilization circuit part connected between a drain and a source of the second NMOS transistor, for stabilizing a source voltage provided through the source voltage terminal; . ≪ / RTI >

According to a third aspect of the present invention, there is provided an apparatus for detecting an envelope of an input signal, the apparatus comprising: an envelope detector for detecting an envelope of an input signal; A source voltage generator for generating a source voltage using a power supply voltage; An envelope amplifier amplifying the envelope signal detected by the envelope detector to generate a first bias voltage by receiving the power supply voltage and the source voltage as a driving voltage; And an amplifier for amplifying the input signal according to the first bias voltage. And a power amplifier.

According to a fourth technical aspect of the present invention, the present invention also provides an envelope detection unit for detecting an envelope of an input signal; A source voltage generator for generating a source voltage using a power supply voltage; An envelope amplifier amplifying the envelope signal detected by the envelope detector to generate a first bias voltage by receiving the power supply voltage and the source voltage as a driving voltage; An output distributor for stabilizing the first bias voltage; And an amplifier for amplifying the input signal according to the first bias voltage. And a power amplifier.

In the third and fourth technical aspects of the present invention, the envelope amplifying section may include: a PMOS transistor having a source connected to the power supply voltage terminal, a gate connected to the output terminal of the envelope detecting section, and a drain connected to the first connecting node; And an NMOS transistor having a drain connected to the first connecting node, a gate connected to an output terminal of the envelope detector, and a source connected to the source voltage terminal; The NMOS transistor may have a drain and a body electrically connected to each other.

Wherein the source voltage generator comprises: a current mirror circuit for generating a first current between the power supply voltage and the ground, and current mirroring the first current to generate a second current; And a voltage generation circuit for generating the source voltage by the resistance of the semiconductor element and the second current; . ≪ / RTI >

The current mirror circuit comprising: a first PMOS transistor having a source coupled to the power supply voltage terminal, a gate and a drain coupled to each other; A first NMOS transistor having a drain coupled to the drain of the first PMOS transistor of the current mirror circuit, a gate supplied with the control voltage, and a source coupled to ground; And a second PMOS transistor having a source coupled to the supply voltage terminal, a gate coupled to a gate of the first PMOS transistor, and a drain providing the second current; . ≪ / RTI >

A second NMOS transistor having a drain connected to the drain and source voltage terminals of the second PMOS transistor of the current mirror circuit, a gate supplied with the power supply voltage, and a source connected to the ground; And a stabilization circuit part connected between a drain and a source of the second NMOS transistor, for stabilizing a source voltage provided through the source voltage terminal; . ≪ / RTI >

In the fourth technical aspect of the present invention, the output distributor generates a second bias voltage having a voltage level different from the first bias voltage using the first bias voltage, and the first and second bias voltages Voltage.

Wherein the amplifying unit comprises: a first power amplifier for amplifying the input signal according to the first bias voltage; And a second power amplifier for amplifying the input signal according to the second bias voltage. . ≪ / RTI >

According to the bias circuit and the power amplifier according to the embodiment of the present invention, the source voltage of the bias circuit is provided by using the operating voltage of the bias circuit for stabilizing the bias voltage so that the bias voltage according to the level of the input signal is adaptively A bias circuit which is insensitive to an external change can be provided. Accordingly, the power amplifier can be stably operated through a bias circuit that operates more stably. As a result, a bias circuit and a power amplifier .

1 is a block diagram of a bias circuit and a power amplifier according to an embodiment of the present invention.
2 is a block diagram of another configuration of a bias circuit and a power amplifier according to an embodiment of the present invention.
3 is a block diagram of another configuration of the bias circuit and the power amplifier according to the embodiment of the present invention.
4 is an internal circuit block diagram of the bias circuit and the power amplifier of FIG.
5 is another internal circuit block diagram of the bias circuit and the power amplifier of FIG. 2;
FIG. 6 is another internal circuit block diagram of the bias circuit and the power amplifier of FIG. 3; FIG.
7 is a circuit diagram of a source voltage generator according to an embodiment of the present invention.
8 is an exemplary diagram of an input signal according to an embodiment of the present invention.
9 is an exemplary view of a first bias voltage according to an embodiment of the present invention.
10 is an exemplary view of a second bias voltage according to an embodiment of the present invention.
11 is a graph of a source voltage and a bias voltage characteristic according to an embodiment of the present invention.
12 is a graph showing gain and efficiency (PAE) characteristics of a power amplifier according to an embodiment of the present invention.
13 is a graph showing a third order intermodulation distortion (IMD3) characteristic of a power amplifier according to an embodiment of the present invention.

It should be understood that the present invention is not limited to the embodiments described and that various changes may be made without departing from the spirit and scope of the present invention.

In addition, in each embodiment of the present invention, the structure, shape, and numerical values described as an example are merely examples for helping understanding of the technical matters of the present invention, so that the spirit and scope of the present invention are not limited thereto. It should be understood that various changes may be made without departing from the spirit of the invention. The embodiments of the present invention may be combined with one another to form various new embodiments.

In the drawings referred to in the present invention, components having substantially the same configuration and function as those of the present invention will be denoted by the same reference numerals.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

1 is a block diagram of a bias circuit and a power amplifier according to an embodiment of the present invention.

Referring to FIG. 1, a bias circuit according to an embodiment of the present invention may include an envelope detector 100, a source voltage generator 200, and an envelope amplifier 300.

In addition, the power amplifier according to the embodiment of the present invention may include the bias circuit and the amplification unit 500 described above.

The envelope detector 100 may receive the gate voltage VG as a driving voltage and detect the envelope of the input signal RFin input through the input terminal IN and the coupling capacitor C1.

For example, the input signal RFin may be a high-frequency signal having an envelope, as shown in FIG. The coupling capacitor C1 is a blocking capacitor that passes an alternating signal and cuts off the DC power.

The source voltage generator 200 may generate the source voltage VS using the power supply voltage VDD. For example, the power supply voltage VDD may be provided by a separate power supply. In order to minimize the influence from the outside, the source voltage VS may be applied to the bias circuit itself according to the embodiment of the present invention. And may be generated using the power supply voltage VDD.

The envelope amplifier 300 receives the power supply voltage VDD and the source voltage VS as a drive voltage and amplifies the envelope signal detected by the envelope detector 100 to generate a first bias voltage VB1, Can be generated.

The amplifier 500 amplifies the input signal RFin received through the input IN according to the first bias voltage VB1 and outputs the amplified input signal RFin through the output OUT. For example, the amplifier 500 may be a power amplifier that amplifies the power of the input signal RFin.

FIG. 2 is a block diagram of another configuration of a bias circuit and a power amplifier according to an embodiment of the present invention, and FIG. 3 is another configuration block diagram of a bias circuit and a power amplifier according to an embodiment of the present invention.

2 and 3, the bias circuit according to the embodiment of the present invention includes an envelope detector 100, a source voltage generator 200, an envelope amplifier 300, and an output distributor 400 .

In addition, the power amplifier according to the embodiment of the present invention may include the bias circuit and the amplification unit 500 described above.

The operations of the envelope detector 100, the source voltage generator 200, the envelope amplifier 300, and the amplifier 500 shown in FIGS. 2 and 3 are the same as those described with reference to FIG. As for the operation, the duplicate operation description may be omitted.

Referring to FIGS. 2 and 3, the output distributor 400 may stabilize the first bias voltage VB1.

3, the output distributor 400 generates a second bias voltage VB2 having a voltage level different from the first bias voltage VB1 using the first bias voltage VB1 Thereby providing the first and second bias voltages.

In this case, the amplifying unit 500 may include a first power amplifier 510 and a second power amplifier 520, and the first power amplifier 510 may amplify the first bias voltage VB1 And the second power amplifier 520 may amplify the input signal according to the second bias voltage VB2.

The output distributor 400 may include a resistor, a capacitor, and an inductor (not shown) to remove an AC component included in the first and second bias voltages VB1 and VB2 or to reduce a voltage variation to maintain a desired voltage level. Or passive elements of the passive components.

FIG. 4 is a block diagram of an internal circuit of the bias circuit and the power amplifier of FIG. 1, FIG. 5 is another internal circuit block diagram of the bias circuit and the power amplifier of FIG. 2, Other internal circuit block diagrams are also shown.

4, 5 and 6, the envelope detecting unit 100 may include a signal amplifying unit 110 and an envelope extracting unit 120.

The signal amplification unit 110 may include a MOS transistor M11 receiving a gate voltage VG for driving. The MOS transistor M11 may include a gate supplied with the input signal RFin through the coupling capacitor C1, a source connected to the ground, and a drain connected to the envelope extracting unit 120. [

The MOS transistor M11 of the signal amplifying unit 110 may amplify the input signal RFin and provide the amplified signal to the envelope extracting unit 120. [

For example, the envelope extractor 120 may include RC circuits R11 and C11 connected in parallel between the drain terminal of the MOS transistor M11 and the power supply voltage VDD terminal.

The RC circuits R11 and C11 of the envelope extracting unit 120 provide a signal to the envelope amplifier 300 from the drain of the MOS transistor M11 so that the low pass Filter to extract an envelope from the signal output from the signal amplification unit 110 and provide the extracted envelope to the envelope amplification unit 300.

Here, the envelope extracting unit 120 is not limited to the RC circuits R11 and C11, and can be applied as long as it can extract an envelope of a high frequency signal.

For example, the envelope amplifier 300 may include a PMOS transistor MP31 and an NMOS transistor MN31.

The PMOS transistor MP31 may include a source connected to the power supply voltage VDD, a gate connected to the output terminal of the envelope detector 100, and a drain connected to the first connection node N1.

The NMOS transistor MN31 may include a drain connected to the first connection node N1, a gate connected to the output terminal of the envelope detector 100, and a source connected to the source voltage VS.

Accordingly, since the gates of the PMOS transistor MP31 and the NMOS transistor MN31 are supplied with the envelope signal from the envelope detector 100, the PMOS transistor MP31 and the NMOS transistor MN31 are connected to the envelope detector 100 according to an envelope signal.

For example, when a signal having a large input to the envelope detecting unit 100 is input, the output voltage of the envelope detecting unit 100 falls to a constant voltage from the power source voltage VDD. Next, at the output terminal of the envelope amplifying unit 300, the initial bias voltage is raised to a constant voltage. More specifically, when the voltage level of the envelope signal is high, the PMOS transistor MP31 and the NMOS transistor MN31 operate in the off state and the on state, respectively, so that the source voltage VS lower than the power supply voltage VDD becomes the first When the voltage level of the envelope signal is low, the PMOS transistor MP31 and the NMOS transistor MN31 operate in the on state and the off state, respectively, so that the power supply voltage VDD becomes the first bias voltage VB1, (VB1).

Accordingly, the first bias voltage VB1 that is adaptively variable according to the voltage level of the envelope signal can be output.

Meanwhile, the drain and the body of the NMOS transistor MN31 may be electrically connected to each other.

Accordingly, if the first bias voltage is equal to or greater than a predetermined value, the PN junction diode of the NMOS transistor MN31 is turned on, and the first bias voltage may be limited so as not to exceed the predetermined voltage .

Accordingly, it is possible to implement a function of limiting the first bias voltage without employing a separate limit circuit. As a result, the envelope amplifying unit 200 can perform the function of limiting the first bias voltage by using a gate oxidation Can be protected from gate oxide breakdown.

Referring to FIG. 5, for example, the output distributor 400 may include at least first and second dividing resistors R41 and R42 connected in series between the power supply voltage VDD and ground. And the first bias voltage VB1 may be provided at a connection node between the first and second split resistors R41 and R42.

The first and second dividing resistors R41 and R42 may be connected to the first and second capacitors C41 and C42 in parallel. And the first and second capacitors C41 and C42, the first bias voltage VB1 can be stabilized.

The implementation circuit of the output divider 400 as described above is one example, but it is not limited thereto.

6, the output distributor 400 includes at least first, second and third dividing resistors R41, R42 and R43 connected in series between the power supply voltage VDD and the ground And the first bias voltage VB1 may be provided at the connection node between the first and second division resistors R41 and R42 and the connection node between the second and third division resistors R42 and R43 may be provided. The second bias voltage VB2 may be provided.

In this case, the first and second capacitors C41 and C42 may be connected in parallel to the first and third distribution resistors R41 and R43, respectively. The first, second, and third split resistors R41 R42 and R43 and the first and second capacitors C41 and C42 can stabilize the second bias voltage VB2.

The implementation circuit of the output divider 400 as described above is one example, but it is not limited thereto.

3 and 6, for example, the amplification unit 500 includes a first power amplifier 510 and a second power amplifier 520 connected in parallel to each other to increase amplification efficiency can do.

The first power amplifier 510 amplifies the input signal according to the first bias voltage VB1 and the second power amplifier 520 amplifies the input signal according to the second bias voltage VB2. The input signal can be amplified.

7 is a circuit diagram of a source voltage generator according to an embodiment of the present invention.

Referring to FIG. 7, for example, the source voltage generator 200 may include a current mirror circuit 210 and a voltage generator circuit 220.

The current mirror circuit 210 may generate a first current I1 between the power supply voltage VDD and ground and generate a second current I2 by current mirroring the first current I1 have.

The voltage generation circuit 220 includes a semiconductor device having a resistance determined according to the magnitude of the power supply voltage VDD and a second current source Can be generated.

For example, the current mirror circuit 210 may include a first PMOS transistor MP21, a first NMOS transistor MN21, and a second PMOS transistor MP22.

The first PMOS transistor MP21 may include a source connected to the power supply voltage VDD, a gate and a drain connected to each other.

The first NMOS transistor MN21 may include a drain connected to the drain of the first PMOS transistor MP21 of the current mirror circuit 210, a gate supplied with the control voltage VC, and a source connected to the ground have.

The second PMOS transistor MP22 includes a source connected to the power supply voltage VDD, a gate connected to the gate of the first PMOS transistor MP21, and a drain for providing the second current I2 can do.

At this time, the first NMOS transistor MN21 may generate the first current I1 according to the control voltage VC, and may change the first current IC when the control voltage VC is varied And the first current I1 may be constant when the control voltage VC is fixed. Accordingly, the first current I1 may flow through the first PMOS transistor MP21 and the second PMOS transistor MP22.

The second PMOS transistor MP22 is connected to the first PMOS transistor MP21 through a current mirror to generate a first current I1 flowing through the first PMOS transistor MP21 Current mirror to generate a second current I2.

Here, if the second PMOS transistor MP22 is the same size as the first PMOS transistor MP21, the second current I2 may be the same as the first current I1, The second current can be determined according to the size ratio of the two transistors.

The voltage generation circuit 220 may include a second NMOS transistor MN22 and a stabilization circuit 222, for example.

The second NMOS transistor MN22 includes a drain connected to the drain and source voltage terminal TS of the second PMOS transistor MP22 of the current mirror circuit 210, a gate supplied with the power supply voltage VDD, It may include a source connected to ground.

Here, the second NMOS transistor MN22 may be a resistor when the power supply voltage VDD is supplied as a gate to operate in a triode region, so that the equivalent resistance of the second NMOS transistor MN22 A voltage determined by the second current I2 may be provided as the source voltage VS.

Further, when the second NMOS transistor MN22 acts as a resistor in the triode region, the fluctuation of the source voltage VS due to the change of the second current I2 can be reduced. Thus, the source voltage VS can be made insensitive to external influences.

The stabilization circuit part 222 may be connected between the drain and the source of the second NMOS transistor MN22 to stabilize the source voltage VS provided through the source voltage terminal TS.

For example, the stabilization circuit unit 222 may include a capacitor C21 as shown in FIG. 7, but is not limited thereto, and may be applied to any circuit capable of stabilizing a voltage.

8 is an exemplary diagram of an input signal according to an embodiment of the present invention.

Referring to FIG. 8, for example, the input signal RFin may be a high-frequency signal having an envelope, such as a wireless LAN communication signal or a cellular communication signal. In FIG. 8, a signal waveform swinging approximately +1.5 V and -1.5 V around approximately 3,5 V is shown, but this is not limitative.

FIG. 9 is a diagram illustrating a first bias voltage according to an embodiment of the present invention, and FIG. 10 illustrates an example of a second bias voltage according to an embodiment of the present invention.

9, the first bias voltage VB1 is a voltage determined according to the voltage level of the envelope signal extracted from the input signal RFin, and is changed from 0 V to 0.60 V according to the voltage level of the envelope signal .

10, the second bias voltage VB2 is a voltage determined according to the voltage level of the envelope signal extracted from the input signal RFin, and is changed from 0 V to 0.30 V according to the voltage level of the envelope signal .

The first and second bias voltages VB1 and VB2 shown in Figs. 9 and 10 are one example, but are not limited thereto.

11 is a graph of a source voltage and a bias voltage characteristic according to an embodiment of the present invention.

In Fig. 11, G1 is a source voltage graph according to the prior art, and G2 is a source voltage graph according to an embodiment of the present invention. VB1 and VB2 are graphs of the first and second bias voltages, respectively.

Referring to G1 and G2 shown in FIG. 11, it can be seen that according to the reference technique, the source voltage (VS of G1) varies sensitively according to the control voltage VC provided from the outside, (VS of G2) is insensitive to the control voltage VC which is an external voltage rather than the source voltage by the conventional technique.

12 is a graph showing gain and efficiency (PAE) characteristics of a power amplifier according to an embodiment of the present invention. 12, G11 is an output power-gain graph for a reference source voltage VS, G12 is an output power-gain graph at a +0.01 variation of a reference source voltage VS, G13 is a reference source voltage VS 0.0 > -0.01 < / RTI > And G21, G22, and G23 are graphs of output power-efficiency (PA3) according to the respective source voltages.

Referring to G11, G12, and G13 in FIG. 12, it can be seen that the gain (GAIN) of the power amplifier according to the embodiment of the present invention hardly changes even if the source voltage VS is varied due to external influences such as a temperature change .

Referring to G21, G22 and G23, it can be seen that the efficiency of the power amplifier according to the embodiment of the present invention hardly changes even if the source voltage VS is varied due to external influences such as a temperature change.

13 is a graph showing a third order intermodulation distortion (IMD3) characteristic of a power amplifier according to an embodiment of the present invention.

13, G11 is the output power-to-three-order intermodulation distortion (IMD3) graph for the reference source voltage VS, G12 is the output power- (IMD3) graph, and G13 is a graph of the output power-to-three-order intermodulation distortion (IMD3) at the -0.01 variable reference source voltage (VS).

13, the third order intermodulation distortion IMD3 of the power amplifier according to the embodiment of the present invention is approximately -40 [Hz] even if the source voltage VS is varied due to external influences such as a temperature change, dBc], but there is no significant change.

According to the embodiment of the present invention as described above, it is possible to provide a bias circuit adaptively adaptive to the level of an input signal, to provide a bias circuit insensitive to an external change, It is possible to make the power amplifier operate stably through the circuit, and as a result, a bias circuit and a power amplifier advantageous for integration can be provided.

100: envelope detector
200: source voltage generator
210: current mirror circuit
220: voltage generating circuit
222: stabilization circuit part
300: Envelope amplifier section
400: output distribution section
500: amplification unit
VDD: Power supply voltage
VS: source voltage
VB1: first bias voltage
I1: first current
I2: Secondary current
MP21: first PMOS transistor
MN21: first NMOS transistor
MP22: Second PMOS transistor
MN22: second NMOS transistor
MP31: PMOS transistor
MN31: NMOS transistor

Claims (20)

An envelope detector for detecting an envelope of the input signal;
A source voltage generator for generating a source voltage using a power supply voltage; And
An envelope amplifier amplifying the envelope signal detected by the envelope detector to generate a first bias voltage by receiving the power supply voltage and the source voltage as a driving voltage; Lt; / RTI >
Wherein the source voltage generator comprises:
A current mirror circuit for generating a first current between the power supply voltage and ground and for mirroring the first current to generate a second current; And
A semiconductor device having a resistance determined according to the magnitude of the power supply voltage; a voltage generation circuit for generating the source voltage by the resistance of the semiconductor device and the second current; Containing
Adaptive bias circuit.
delete 2. The current mirror circuit according to claim 1,
A first PMOS transistor having a source connected to the power supply voltage terminal, a gate and a drain connected to each other;
A first NMOS transistor having a drain coupled to the drain of the first PMOS transistor of the current mirror circuit, a gate supplied with the control voltage, and a source coupled to ground; And
A second PMOS transistor having a source coupled to the supply voltage terminal, a gate coupled to a gate of the first PMOS transistor, and a drain providing the second current;
/ RTI >
The voltage generation circuit according to claim 3,
A second NMOS transistor having a drain connected to the drain and source voltage terminals of the second PMOS transistor of the current mirror circuit, a gate supplied with the power supply voltage, and a source connected to ground; And
A stabilization circuit part connected between a drain and a source of the second NMOS transistor, for stabilizing a source voltage provided through the source voltage terminal;
/ RTI >
An envelope detector for detecting an envelope of the input signal;
A source voltage generator for generating a source voltage using a power supply voltage;
An envelope amplifier amplifying the envelope signal detected by the envelope detector to generate a first bias voltage by receiving the power supply voltage and the source voltage as a driving voltage; And
An output distributor for stabilizing the first bias voltage; Lt; / RTI >
Wherein the source voltage generator comprises:
A current mirror circuit for generating a first current between the power supply voltage and ground and for mirroring the first current to generate a second current; And
A semiconductor device having a resistance determined according to the magnitude of the power supply voltage; a voltage generation circuit for generating the source voltage by the resistance of the semiconductor device and the second current; Containing
Adaptive bias circuit.
delete 6. The current mirror circuit according to claim 5,
A first PMOS transistor having a source connected to the power supply voltage terminal, a gate and a drain connected to each other;
A first NMOS transistor having a drain coupled to the drain of the first PMOS transistor of the current mirror circuit, a gate supplied with the control voltage, and a source coupled to ground; And
A second PMOS transistor having a source coupled to the supply voltage terminal, a gate coupled to a gate of the first PMOS transistor, and a drain providing the second current;
/ RTI >
The voltage generation circuit according to claim 7,
A second NMOS transistor having a drain connected to the drain and source voltage terminals of the second PMOS transistor of the current mirror circuit, a gate supplied with the power supply voltage, and a source connected to ground; And
A stabilization circuit part connected between a drain and a source of the second NMOS transistor, for stabilizing a source voltage provided through the source voltage terminal;
/ RTI >
An envelope detector for detecting an envelope of the input signal;
A source voltage generator for generating a source voltage using a power supply voltage;
An envelope amplifier amplifying the envelope signal detected by the envelope detector to generate a first bias voltage by receiving the power supply voltage and the source voltage as a driving voltage; And
An amplifier for amplifying the input signal according to the first bias voltage; Lt; / RTI >
Wherein the source voltage generator comprises:
A current mirror circuit for generating a first current between the power supply voltage and ground and for mirroring the first current to generate a second current; And
A semiconductor device having a resistance determined according to the magnitude of the power supply voltage; a voltage generation circuit for generating the source voltage by the resistance of the semiconductor device and the second current; Containing
Power amplifier.
The apparatus of claim 9, wherein the envelope amplifying unit comprises:
A PMOS transistor having a source connected to the power supply voltage terminal, a gate connected to the output terminal of the envelope detector, and a drain connected to the first connection node; And
An NMOS transistor having a drain connected to the first connection node, a gate connected to the output terminal of the envelope detector, and a source connected to the source voltage terminal; Lt; / RTI >
Wherein the NMOS transistor has a drain and a body electrically connected to each other.
delete 10. The current mirror circuit according to claim 9,
A first PMOS transistor having a source connected to the power supply voltage terminal, a gate and a drain connected to each other;
A first NMOS transistor having a drain coupled to the drain of the first PMOS transistor of the current mirror circuit, a gate supplied with the control voltage, and a source coupled to ground; And
A second PMOS transistor having a source coupled to the supply voltage terminal, a gate coupled to a gate of the first PMOS transistor, and a drain providing the second current;
≪ / RTI >
The voltage generating circuit according to claim 12,
A second NMOS transistor having a drain connected to the drain and source voltage terminals of the second PMOS transistor of the current mirror circuit, a gate supplied with the power supply voltage, and a source connected to ground; And
A stabilization circuit part connected between a drain and a source of the second NMOS transistor, for stabilizing a source voltage provided through the source voltage terminal;
≪ / RTI >
An envelope detector for detecting an envelope of the input signal;
A source voltage generator for generating a source voltage using a power supply voltage;
An envelope amplifier amplifying the envelope signal detected by the envelope detector to generate a first bias voltage by receiving the power supply voltage and the source voltage as a driving voltage;
An output distributor for stabilizing the first bias voltage; And
An amplifier for amplifying the input signal according to the first bias voltage; Lt; / RTI >
Wherein the source voltage generator comprises:
A current mirror circuit for generating a first current between the power supply voltage and ground and for mirroring the first current to generate a second current; And
A semiconductor device having a resistance determined according to the magnitude of the power supply voltage; a voltage generation circuit for generating the source voltage by the resistance of the semiconductor device and the second current; Containing
Power amplifier.
15. The receiver of claim 14,
A PMOS transistor having a source connected to the power supply voltage terminal, a gate connected to the output terminal of the envelope detector, and a drain connected to the first connection node; And
An NMOS transistor having a drain connected to the first connection node, a gate connected to the output terminal of the envelope detector, and a source connected to the source voltage terminal; Lt; / RTI >
Wherein the NMOS transistor has a drain and a body electrically connected to each other.
delete 15. The current mirror circuit according to claim 14,
A first PMOS transistor having a source connected to the power supply voltage terminal, a gate and a drain connected to each other;
A first NMOS transistor having a drain coupled to the drain of the first PMOS transistor of the current mirror circuit, a gate supplied with the control voltage, and a source coupled to ground; And
A second PMOS transistor having a source coupled to the supply voltage terminal, a gate coupled to a gate of the first PMOS transistor, and a drain providing the second current;
≪ / RTI >
The voltage generation circuit according to claim 17,
A second NMOS transistor having a drain connected to the drain and source voltage terminals of the second PMOS transistor of the current mirror circuit, a gate supplied with the power supply voltage, and a source connected to ground; And
A stabilization circuit part connected between a drain and a source of the second NMOS transistor, for stabilizing a source voltage provided through the source voltage terminal;
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The apparatus of claim 18, wherein the output distributor comprises:
And generates a second bias voltage having a voltage level different from the first bias voltage using the first bias voltage to provide the first and second bias voltages.
20. The apparatus according to claim 19,
A first power amplifier for amplifying the input signal according to the first bias voltage; And
A second power amplifier for amplifying the input signal according to the second bias voltage;
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