KR101914060B1 - Method of analyzing power consumption and electrothermal behavior of VLSI chips and computer-readable medium storing the same - Google Patents

Method of analyzing power consumption and electrothermal behavior of VLSI chips and computer-readable medium storing the same Download PDF

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KR101914060B1
KR101914060B1 KR1020150187530A KR20150187530A KR101914060B1 KR 101914060 B1 KR101914060 B1 KR 101914060B1 KR 1020150187530 A KR1020150187530 A KR 1020150187530A KR 20150187530 A KR20150187530 A KR 20150187530A KR 101914060 B1 KR101914060 B1 KR 101914060B1
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semiconductor chip
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신영수
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한국과학기술원
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00—Arrangements for measuring electric power or power factor
    • G01R21/02—Arrangements for measuring electric power or power factor by thermal methods, e.g. calorimetric
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2803—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads

Abstract

A method for thermal-power analysis of a highly integrated semiconductor chip includes modeling a semiconductor chip and a package structure surrounding the semiconductor chip with a simplified semiconductor chip to establish an electrothermal equation representing power consumption at a certain temperature The structure being represented by the heat transfer coefficient of the surface of the simplified semiconductor chip), the temperature of the simplified semiconductor chip in the first section of the operating temperature range of the simplified semiconductor chip and the second section of the simplified semiconductor chip, And a step of calculating the temperature and power consumption of the semiconductor chip based on the heat transfer equation and the quadratic polynomial.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for analyzing a heat of a highly integrated semiconductor chip and a computer readable recording medium storing the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thermal-power analysis of a semiconductor chip, and more particularly, to a method for analyzing a heat of a highly integrated semiconductor chip and a computer-readable recording medium storing the same.

In chip design, there are two main methods of thermal analysis. When a semiconductor chip is floor planned, thermal analysis is used to locate the optimal floor plan, locate the hot spots, and determine the location of the thermal sensors. In the other analysis technique, an analysis is performed to determine whether a specific cooling and package structure is suitable for a given chip.

Since conventional analysis techniques require numerous iterative calculations, it is time-consuming and can not be performed on all chips.

1. United States Patent No. 8,352,230 2. Korean Patent Publication No. 2014-0062515

It is an object of the present invention to provide a method for analyzing the heat of a highly integrated semiconductor chip, which can shorten the time required to perform all the chips.

It is an object of the present invention to provide a computer-readable recording medium storing a method for analyzing the heat of a highly integrated semiconductor chip.

According to an aspect of the present invention, there is provided a method for analyzing a heat of a highly integrated semiconductor chip, which includes modeling a semiconductor chip and a package structure surrounding the semiconductor chip into a simplified semiconductor chip, Wherein the package structure is expressed by a heat transfer coefficient of the surface of the simplified semiconductor chip, the first section of the operating temperature range of the simplified semiconductor chip, and the second section of the operating temperature range of the simplified semiconductor chip, Approximating power consumption depending on a temperature of the simplified semiconductor chip in a second section continuous to the first section with a second-order polynomial, and calculating a temperature of the semiconductor chip based on the heat transfer equation and the second- And calculating power consumption.

In an exemplary embodiment, the electrothermal equation may satisfy Equation (1) below.

[Equation 1]

Figure 112015127614113-pat00001

(The above Equation 1 from the T am is the simplified external to the semiconductor die temperature, R th is the thermal resistance of the simplified semiconductor chip, T is the temperature of the simplified semiconductor chip, P is the simplified semiconductor chip satisfy R th = 1 / (Ah) , represents a consumption power consumed by the, a represents the surface area of the simplified semiconductor chip, h represents the heat transfer coefficient of the surface of the simplified semiconductor chip.)

The quadratic polynomial can be expressed by the following Equation 2 in the first and second intervals, respectively.

&Quot; (2) "

Figure 112015127614113-pat00002

(Where m is a minimum value of the operating temperature range of the simplified semiconductor chip, M is a maximum value of the operating temperature range of the simplified semiconductor chip, I is an arbitrary value between m and M, a 1 and a 2 are positive real numbers, a 2 > a 1 , b 1 is less than or equal to m, and b 2 is less than or equal to I.)

The temperature T of the chip can satisfy the following formula (3) based on the above-described equations (1) and (2).

&Quot; (3) "

Figure 112015127614113-pat00003

(Equation 3)

Figure 112015127614113-pat00004
Lt; / RTI >
Figure 112015127614113-pat00005
A, b and c represent a 1 , b 1 and c 1 in the first section and a 2 , b 2 and c 2 in the second section, respectively.

If B 2 -4ac is less than 0, it may indicate that the thermal equilibrium temperature of the semiconductor chip is not present.

When B 2 -4ac is 0 or more, it can indicate that the thermal equilibrium temperature of the semiconductor chip exists.

The root mean square of the error of the temperature measured at the plurality of sample temperatures within the operating temperature range of the semiconductor chip is minimized so as to approximate the quadratic polynomial,

Figure 112015127614113-pat00006
And
Figure 112015127614113-pat00007
A derivative that is continuous in the I a, b, c, and looking at I, a, b, c is in the first section represents a 1, b 1, c 1 , in the second region a 2, b 2 , c 2 , and the root mean square of the error can satisfy the following equation (4).

&Quot; (4) "

Figure 112015127614113-pat00008

(Where N is the number of sample temperatures).

According to an aspect of the present invention, there is provided a method for analyzing a heat of a highly integrated semiconductor chip, which includes modeling a semiconductor chip and a package structure surrounding the semiconductor chip into a simplified semiconductor chip, Wherein the package structure is expressed by a heat transfer coefficient of the surface of the simplified semiconductor chip, the first section of the range of the operating temperature of the semiconductor chip, and the second section of the temperature range of the semiconductor chip, A step of approximating the power consumption depending on the temperature of the semiconductor chip in a second section continuous to the first section by a second order polynomial and a step of calculating a temperature and a power consumption of the semiconductor chip based on the heat transfer equation and the second order polynomial .

In an exemplary embodiment, the instantaneous heat transfer equation may satisfy Equation (5) below.

&Quot; (5) "

Figure 112015127614113-pat00009

(Wherein in formula 5] in T am is the simplified external temperature of the semiconductor chip, R th is the thermal resistance, T (t) of the simplified semiconductor chip has a temperature of the simplified semiconductor chip, P is the simplification a represents the power consumed by the semiconductor chip, and satisfy R th = 1 / (Ah) , a represents the surface area of the simplified semiconductor chip, h represents the heat transfer coefficient of the surface of the simplified semiconductor chip, C th represents the heat capacity of the simplified semiconductor chip, C th = V p Cp, and C p, V, and p represent the specific heat, volume, and density of the simplified semiconductor chip, respectively.

The quadratic polynomial can be expressed by the following Equation 2 in the first and second intervals, respectively.

&Quot; (6) "

Figure 112015127614113-pat00010

M represents a minimum value of the operating temperature range of the chip, M represents a maximum value of the operating temperature range of the chip, I represents any value between m and M, a 1 and a 2 represent A 2 > a 1 , b 1 is less than or equal to m, and b 2 is less than or equal to I.)

The temperature T (t) of the chip may satisfy the following formula (7) based on the above-mentioned equations (5) and (6).

&Quot; (7) "

Figure 112015127614113-pat00011

(A, b, and c in the above equation (7) represent a 1 , b 1 , and c 1 in the first section and a 2 , b 2 , and c 2 in the second section.

When B 2 -4ac is larger than 0, it indicates that a thermal equilibrium temperature exists, and the above equation (7) can satisfy the following equation (8).

&Quot; (8) "

Figure 112015127614113-pat00012

(Equation 8)

Figure 112015127614113-pat00013
ego,
Figure 112015127614113-pat00014
.

When B 2 -4ac is smaller than 0, it means that there is no thermal equilibrium temperature, and the above Equation (7) can satisfy Equation (9) below.

&Quot; (9) "

Figure 112015127614113-pat00015

(Equation 9)

Figure 112015127614113-pat00016
.

When B 2 -4ac is equal to 0, it represents an unstable thermal equilibrium state, and the above-mentioned equation (7) can satisfy the following equation (10).

&Quot; (10) "

Figure 112015127614113-pat00017

(Equation 10)

Figure 112015127614113-pat00018
.

The root mean square of the error of the temperature measured at the plurality of sample temperatures within the operating temperature range of the semiconductor chip is minimized so as to approximate the quadratic polynomial,

Figure 112015127614113-pat00019
And
Figure 112015127614113-pat00020
A derivative that is continuous in the I a, b, c, and looking at I, a, b, c is in the first section represents a 1, b 1, c 1 , in the second region a 2, b 2 , c 2 , and the root mean square of the error can satisfy the following equation (4).

&Quot; (4) "

Figure 112015127614113-pat00021

(Where N is the number of sample temperatures).

According to another aspect of the present invention, there is provided a computer-readable recording medium having recorded thereon a computer program for executing a method for analyzing a thermal power of a highly integrated semiconductor chip according to an embodiment of the present invention, And modeling a package structure surrounding the semiconductor chip with a simplified semiconductor chip to establish an electrothermal equation representing power consumption at a certain temperature (the package structure has a heat transfer coefficient of the surface of the simplified semiconductor chip , The power consumption depending on the temperature of the simplified semiconductor chip in the first section of the operating temperature range of the simplified semiconductor chip and the second section subsequent to the first section is approximated by the second order polynomial And the temperature of the semiconductor chip based on the heat transfer equation and the quadratic polynomial equation And a step of calculating the power ratio.

According to another aspect of the present invention, there is provided a computer-readable recording medium having recorded thereon a computer program for executing a method for analyzing a thermal power of a highly integrated semiconductor chip according to an embodiment of the present invention, And modeling a package structure surrounding the semiconductor chip with a simplified semiconductor chip to establish a transient electrothermal equation that represents power consumption over time, the package structure comprising a heat transfer of the surface of the simplified semiconductor chip Approximating a power consumption depending on a temperature of the semiconductor chip in a first section of a range of an operating temperature of the semiconductor chip and a second section continuing to the first section by a second order polynomial, Temperature and power consumption of the semiconductor chip based on the heat transfer equation and the quadratic polynomial equation .

Therefore, according to embodiments of the present invention, the heat-power analysis of a highly integrated semiconductor chip can be performed in a short time using a quadratic equation rather than an iterative numerical calculation.

1 shows a package structure to which a heat-power analysis method according to embodiments of the present invention can be applied.
FIG. 2 shows a simplified semiconductor chip in which the package structure of FIG. 1 is modeled to apply a thermal-power analysis method according to embodiments of the present invention.
3 is a graph showing the total power consumption of the semiconductor chip according to the temperature.
4 is a flow chart illustrating a method for analyzing the thermal power of a highly integrated semiconductor chip according to embodiments of the present invention.
5 is a graph showing the equation (5).
FIG. 6 is a flowchart illustrating a method of analyzing a heat-power of a highly integrated semiconductor chip according to embodiments of the present invention.
7 is a graph showing T (t) when B 2 -4ac is greater than zero.
8 is a graph showing T (t) when B 2 -4ac is smaller than zero.
9 is a graph showing T (t) when B 2 -4ac is 0;
10 is a block diagram illustrating a computing system used to perform an analysis method in accordance with an embodiment of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 shows a package structure to which a heat-power analysis method according to embodiments of the present invention can be applied.

1, a package structure 10 to which a thermal-power analysis method according to embodiments of the present invention can be applied includes a ball grid array 12 stacked on a printed circuit board 11, a ball grid array And a highly integrated semiconductor chip 20 formed on the substrate 13 and the substrate 13 formed on the substrate 12. The heat spreader 31 and the heat sink 33 for discharging the heat generated from the highly integrated semiconductor chip 20 to the outside can be formed on the highly integrated semiconductor chip 20.

FIG. 2 shows a simplified semiconductor chip in which the package structure of FIG. 1 is modeled to apply a thermal-power analysis method according to embodiments of the present invention.

Referring to FIG. 2, the package structure 10 of FIG. 1 may be modeled as a simplified semiconductor chip 100, as in FIG. 2, wherein the simplified semiconductor chip 100 corresponds to a thermal model of the package structure 10. And complicated structures such as the printed circuit board 11, the ball grid array 12, the heat spreader 31 and the heat sink 33 are formed by the heat transfer coefficient h of the surface of the simplified semiconductor chip 100 Can be expressed. The heat transfer coefficient h may be determined by the structure and material of the package structure 10 and the external environment thereof.

2, when the external temperature T am of the simplified semiconductor chip 100 and the consumed power P consumed in the simplified semiconductor chip 100 are given, the simplified semiconductor chip 100 is simplified, The temperature T of the fuel cell 100 may satisfy the following equation (1).

[Equation 1]

Figure 112015127614113-pat00022

The satisfy the above formula 1] R th is the simplified represents the thermal resistance of the semiconductor chip (100), R th = 1 / (Ah) from, A represents the surface area of the simplified semiconductor chip 100 .

In Equation (1), the left term represents the amount of thermal energy exiting to the outside by convection, and the right term represents the amount of thermal energy generated due to the power consumption of the simplified semiconductor chip 100, ] Can be solved to obtain the thermal equilibrium temperature of the semiconductor chip 100.

In the simplified semiconductor chip 100 shown in FIG. 2, the temperature of the simplified semiconductor chip 100 with respect to time can be expressed by the following equation (2).

&Quot; (2) "

Figure 112015127614113-pat00023

In the above formula (2), T am is the external temperature of the simplified semiconductor chip 100, R th is the thermal resistance of the simplified semiconductor chip 100, T (t) the temperature, P satisfies the simplified represents the power consumed by the semiconductor chip (100), R th = 1 / (Ah) and, a represents the surface area of the simplified semiconductor chip (100), h is represents a heat transfer coefficient of the surface of the simplified semiconductor chip 100, C th represents the thermal capacity of the semiconductor chip 100 to simplify the, C th = VρCp and, Cp, V, ρ is the simplified semiconductor chip, respectively The specific heat, the volume, and the density of the substrate 100.

Solving the above equation (2), it is possible to obtain the column with time.

In the heat-power analysis of the conventional semiconductor chip, the power consumption (P) in the above-mentioned Equations (1) and (2) is defined as a temperature-independent constant. If the power consumption (P) is a temperature-independent constant, [Equation 1] and [Equation 2] are simple linear equations or linear differential equations.

However, when the leakage current generated in the semiconductor chip is considered, since the power consumption P depends on the temperature of the semiconductor chip, the solutions of the equations (1) and (2) can not be obtained easily.

3 is a graph showing the total power consumption of the semiconductor chip according to the temperature.

FIG. 3 empirically shows an aspect in which the total power consumption of the semiconductor chip varies depending on the temperature of the semiconductor chip when the leakage current is taken into consideration. The tendency is well approximated by the following equation (3).

&Quot; (3) "

Figure 112015127614113-pat00024

In Equation (3), Pdy denotes a dynamic power independent of the temperature of the semiconductor chip,

Figure 112015127614113-pat00025
Indicates a leakage current depending on the temperature of the semiconductor chip, and it can be seen that it exponentially increases with increasing temperature. Also, β is a constant related to the leakage current. Also, the solid line in Fig. 3 represents the total power consumption by Equation (3), and each of the circles represents the total power consumption calculated by the simulation tool at a given temperature.

When [Equation 1] is substituted for P (T) in [Equation 3], the result can be expressed by Equation (4) below.

&Quot; (4) "

Figure 112015127614113-pat00026

[Equation 4] is a nonlinear equation for T, and it is generally necessary to obtain the solution using an iterative numerical analysis technique.

As described above, the conventional analysis method for predicting the power consumption and the temperature change of the chip in consideration of the leakage current of the semiconductor chip is performed through the following series of processes.

(a) First, the temperature of the semiconductor chip is substituted into the right term of Equation (4) to calculate the power consumption of the semiconductor chip with respect to the initial temperature, and the T of the left term is obtained while the power consumption is fixed.

(b) Substituting T obtained from (a) into the right term of [Equation 4] again performs the procedure of (a).

(c) Repeat steps (a) and (b) until the temperature (T) is constant.

In the conventional method, as shown in (c), it takes a long time because steps (a) and (b) are repeated until the temperature (T) becomes constant. In addition, it is not suitable for analysis at the level of the entire chip or when the number of analysis is required a lot because other analysis methods require numerous repetitive calculation operations.

4 is a flow chart illustrating a method for analyzing the thermal power of a highly integrated semiconductor chip according to embodiments of the present invention.

Referring to FIGS. 1, 2 and 4, in a method for analyzing the heat of a highly integrated semiconductor chip, a semiconductor chip 20 and a package structure surrounding the semiconductor chip are modeled by a simplified semiconductor chip 100, An electrothermal equation representing the power consumption of the battery is established (S110). The above-mentioned electrothermal equation can be expressed as Equation (1).

The power consumption depending on the temperature of the simplified semiconductor chip in the first section of the operating temperature range of the simplified semiconductor chip 100 and the second section subsequent to the first section is approximated by the second order polynomial ( S130). The quadratic polynomial can be expressed by the following equation (5).

&Quot; (5) "

Figure 112015127614113-pat00027

Where M is the minimum value of the operating temperature range of the simplified semiconductor chip 100, M is the maximum value of the operating temperature range of the simplified semiconductor chip 100, I is the maximum value of the operating temperature range of the semiconductor chip 100, A 1 and a 2 are positive real numbers, a 2 > a 1 , b 1 is not more than m, and b 2 satisfies I or less.

The root mean square of the error of the temperature measured at the plurality of sample temperatures within the operating temperature range of the semiconductor chip 20 is minimized so that the approximation of Equation (5)

Figure 112015127614113-pat00028
And
Figure 112015127614113-pat00029
A derivative that is continuous in the I a, b, c, and looking at I, a, b, c is in the first section represents a 1, b 1, c 1 , in the second region a 2, b 2 , c 2 , and the root mean square of the error can be expressed by the following equation (6).

&Quot; (6) "

Figure 112015127614113-pat00030

In Equation (6), N represents the number of sample temperatures.

The temperature and power consumption of the semiconductor chip 20 are calculated on the basis of the heat transfer equation and the quadratic polynomial equation (S150).

5 is a graph showing the equation (5).

5, a 1 and a 2 are positive real numbers, a 2 > a 1 , b 1 is less than or equal to m, and b 2 is less than or equal to I

Figure 112015127614113-pat00031
Can be defined as a monotone increasing function.

In FIG. 5, the circles represent the first period

Figure 112015127614113-pat00032
), And the portion represented by the triangle represents the second section (
Figure 112015127614113-pat00033
), Which is a quadratic equation.

Instead of P in Equation (1), Equation (5)

Figure 112015127614113-pat00034
The following equation (7) is derived.

&Quot; (7) "

Figure 112015127614113-pat00035

The suffix indicating the interval in (7) is omitted.

If T is obtained from the equation (7), the temperature of the semiconductor chip 20 can be expressed by the following equation (8).

&Quot; (8) "

Figure 112015127614113-pat00036

In Equation 8,

Figure 112015127614113-pat00037
Lt; / RTI >
Figure 112015127614113-pat00038
A, b and c represent a 1 , b 1 and c 1 in the first section and a 2 , b 2 and c 2 in the second section, respectively.

Therefore, the temperature T of the semiconductor chip 20 is obtained from the equation (8), and the power consumption P of the semiconductor chip 20 is calculated from the temperature T of the semiconductor chip 20 using the equation (1) Can be obtained. Therefore, it is not necessary to repeatedly obtain the temperature and power consumption of the semiconductor chip 20 at all. The thermal state of the semiconductor chip according to the temperature can be predicted according to the sign of B 2 -4ac.

For example, when B 2 -4ac is less than 0, this indicates that the thermal equilibrium temperature of the semiconductor chip 20 is not present. That is, when the heat resistance of the semiconductor chip 20 is too high and the heat dissipation is not good or the power consumption of the semiconductor chip 20 is too high, the internal temperature of the semiconductor chip 20 rises, ) Can cause a thermal runaway phenomenon. As described above

Figure 112015127614113-pat00039
Wow
Figure 112015127614113-pat00040
Is a monotone increasing function. Therefore, if B 2 -4ac is smaller than 0 in either of the first interval and the second interval, the same condition is satisfied in other intervals.

For example, if B 2 -4ac is greater than or equal to zero, then Equation (7) will have at least one real number solution. If there are two solutions, a low temperature is adopted. Because high temperatures indicate unstable equilibrium temperatures. However, the solution obtained from the equation (7) for the first section or the second section has meaning only when it exists within the section.

Figure 112015127614113-pat00041
Wow
Figure 112015127614113-pat00042
Is a monotone increasing function, it is impossible mathematically to generate a meaningful solution in both the first and second sections.

FIG. 6 is a flowchart illustrating a method of analyzing a heat-power of a highly integrated semiconductor chip according to embodiments of the present invention.

Referring to FIGS. 1, 2 and 6, in the method of analyzing the heat of a highly integrated semiconductor chip, the semiconductor chip 20 and the package structure surrounding the semiconductor chip are modeled by the simplified semiconductor chip 100, An instantaneous electrothermal equation representing the power consumption is established (S210). The instantaneous heat transfer equation can be expressed as Equation (2).

The power consumption depending on the temperature of the simplified semiconductor chip in the first section of the operating temperature range of the simplified semiconductor chip 100 and the second section subsequent to the first section is approximated by the second order polynomial ( S230). The quadratic polynomial can be expressed as Equation (5).

If Equation (5) is substituted for P in Equation (2), the temperature of the semiconductor chip 20 with respect to time can be expressed as Equation (9) below.

&Quot; (9) "

Figure 112015127614113-pat00043

In Equation (9), a, b and c denote a 1 , b 1 and c 1 in the first section and a 2 , b 2 and c 2 in the second section.

If B 2 -4ac is larger than 0 in Equation (9), it indicates that the thermal equilibrium temperature of the semiconductor chip 20 exists, and T (t) can be expressed by the following equation (10).

&Quot; (10) "

Figure 112015127614113-pat00044

In the above equation (10)

Figure 112015127614113-pat00045
ego,
Figure 112015127614113-pat00046
.

7 is a graph showing T (t) when B 2 -4ac is greater than zero.

Referring to FIG. 7, it can be seen that the temperature of the semiconductor chip 20 converges to T 1 with the lapse of time.

If B 2 -4ac is less than 0 in Equation (9), it means that there is no thermal equilibrium temperature of the semiconductor chip 20, and T (t) can be expressed by Equation (11) below.

&Quot; (11) "

Figure 112015127614113-pat00047

In Equation (11)

Figure 112015127614113-pat00048
.

8 is a graph showing T (t) when B 2 -4ac is smaller than zero.

Referring to FIG. 8, it can be seen that the temperature of the semiconductor chip 20 diverges in the arctan form with the lapse of time.

Represents the incomplete thermal equilibrium state of the semiconductor chip 20 when B 2 -4ac is 0 in Equation (9), and T (t) can be expressed by Equation (12) below.

&Quot; (12) "

Figure 112015127614113-pat00049

In the above equation (12)

Figure 112015127614113-pat00050
.

Equation (12) shows an unstable equilibrium state in which a thermal runaway may occur even if there is a thermal equilibrium temperature of the semiconductor chip 20 but a slight temperature change or thermal change.

9 is a graph showing T (t) when B 2 -4ac is 0;

Referring to FIG. 9, it can be seen that the temperature of the semiconductor chip 20 converges to T 1 with the lapse of time.

10 is a block diagram illustrating a computing system used to perform an analysis method in accordance with an embodiment of the present invention.

10, a computing system 300 may include a processor 310, a main memory 320, an input / output device 330, a display device 340, and a storage device 350. The processor 310, the main memory 320, the input / output device 330, the display device 340, and the storage device 350 may be interconnected via the system bus 305.

The processor 310 may be configured as a single core or a multicore. The input / output device 330 may be a keyboard, a mouse, a printer, or the like. The main memory 320 may be a DRAM or an SRAM. The display device 340 may be a display device such as an LCD, an LED display, an OLED display, or the like. The storage device 350 may be a hard disk drive (HDD), a solid state drive (SSD), or the like. The storage device 350 may store the analysis method of FIG. 1 or the design method of FIG. 6 in computer readable program code 360. The program code 360 may be loaded into the main memory 320 and executed by the processor 310 and may output simulation results to the input / output device 330 or the display device 340 as a result of execution. That is, when the program code 360 is executed in the main memory 320 by the processor 310, the user inputs the device parameters of the flat transistor and the corner transistors through the input / output device 330, And output the simulation result to the input / output device 330 or display it on the display device 340. That is, the graph as shown in FIGS. 7 to 9 may be displayed on the display device 350.

Embodiments of the present invention can be widely applied to the field of heat-power analysis of highly integrated semiconductor chips.

While the present invention has been described with reference to the preferred embodiments thereof, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined in the appended claims. It will be understood.

Claims (17)

Modeling a semiconductor chip and a package structure surrounding the semiconductor chip with a simplified semiconductor chip and establishing an electrothermal equation representing power consumption at a certain temperature (the package structure includes a surface of the simplified semiconductor chip Expressed as heat transfer coefficient);
Approximating the power consumption depending on the temperature of the simplified semiconductor chip in a first section of the operating temperature range of the simplified semiconductor chip and a second section continuing to the first section with a second order polynomial; And
Calculating a temperature and a power consumption of the semiconductor chip based on the heat transfer equation and the quadratic polynomial,
The above-mentioned heat transfer equation satisfies the following formula (1)
[Equation 1]
Figure 112018023222284-pat00082

(The above Equation 1 from the T am is the simplified external to the semiconductor die temperature, R th is the thermal resistance of the simplified semiconductor chip, T is the temperature of the simplified semiconductor chip, P is the simplified semiconductor chip A represents the surface area of the simplified semiconductor chip, and h represents the heat transfer coefficient of the surface of the simplified semiconductor chip), Rth = 1 / (Ah)
The second polynomial is represented by the following Equation 2 in the first and second intervals,
&Quot; (2) "
Figure 112018023222284-pat00083

(Where m is a minimum value of the operating temperature range of the simplified semiconductor chip, M is a maximum value of the operating temperature range of the simplified semiconductor chip, I is an arbitrary value between m and M, a 1 and a 2 are positive real numbers, a 2 > a 1 , b 1 is less than or equal to m and b 2 is less than or equal to I)
Wherein the temperature T of the chip satisfies the following formula (3) based on the above-mentioned equations (1) and (2).
&Quot; (3) "
Figure 112018023222284-pat00084

(Equation 3)
Figure 112018023222284-pat00085
Lt; / RTI >
Figure 112018023222284-pat00086
A, b and c represent a 1 , b 1 and c 1 in the first section and a 2 , b 2 and c 2 in the second section, respectively. delete delete delete The method according to claim 1,
Wherein when B 2 -4ac is less than 0, the thermal equilibrium temperature of the semiconductor chip does not exist. The method according to claim 1,
And B 2 -4ac is 0 or more, the thermal equilibrium temperature of the semiconductor chip is present. The method according to claim 1,
To approximate this quadratic polynomial
Wherein a root mean square of an error of a temperature measured at a plurality of sample temperatures within an operating temperature range of the semiconductor chip is minimized,
remind
Figure 112018023222284-pat00056
And
Figure 112018023222284-pat00057
B, c, and I, which are successive in the I,
wherein a, b and c represent a 1 , b 1 and c 1 in the first section and a 2 , b 2 and c 2 in the second section and the root mean square of the error is expressed by the following equation 4]. ≪ / RTI >
&Quot; (4) "
Figure 112018023222284-pat00058

(Where N is the number of sample temperatures). Modeling a semiconductor chip and a package structure surrounding the semiconductor chip with a simplified semiconductor chip to establish a transient electrothermal equation representing power consumption over time, the package structure comprising a surface of the simplified semiconductor chip Lt; / RTI >
Approximating a power consumption depending on a temperature of the semiconductor chip in a first section of an operating temperature range of the semiconductor chip and a second section continuing to the first section with a second order polynomial; And
And calculating the temperature and power consumption of the semiconductor chip based on the heat transfer equation and the quadratic polynomial. 9. The method of claim 8,
The instantaneous heat transfer equation
(5): " (5) "
&Quot; (5) "
Figure 112015127614113-pat00059

(Wherein in formula 5] in T am is the simplified external temperature of the semiconductor chip, R th is the thermal resistance, T (t) of the simplified semiconductor chip has a temperature of the simplified semiconductor chip, P is the simplification a represents the power consumed by the semiconductor chip, and satisfy R th = 1 / (Ah) , a represents the surface area of the simplified semiconductor chip, h represents the heat transfer coefficient of the surface of the simplified semiconductor chip, C th represents the heat capacity of the simplified semiconductor chip, C th = V p Cp, and C p, V, and p represent the specific heat, volume, and density of the simplified semiconductor chip, respectively. 10. The method of claim 9,
Wherein the quadratic polynomial is represented by the following Equation (2) in the first section and the second section, respectively.
&Quot; (6) "
Figure 112015127614113-pat00060

M represents a minimum value of the operating temperature range of the chip, M represents a maximum value of the operating temperature range of the chip, I represents any value between m and M, a 1 and a 2 represent A 2 > a 1 , b 1 is less than or equal to m, and b 2 is less than or equal to I.) 11. The method of claim 10,
Wherein the temperature T (t) of the chip satisfies the following formula (7) based on the above-mentioned equations (5) and (6).
&Quot; (7) "
Figure 112015127614113-pat00061

(A, b, and c in the above equation (7) represent a 1 , b 1 , and c 1 in the first section and a 2 , b 2 , and c 2 in the second section. 12. The method of claim 11,
And B 2 -4ac is greater than 0, the thermal equilibrium temperature is present, and the equation (7) satisfies the following equation (8).
&Quot; (8) "
Figure 112015127614113-pat00062

(Equation 8)
Figure 112015127614113-pat00063
ego,
Figure 112015127614113-pat00064
. 12. The method of claim 11,
And B 2 -4ac is smaller than 0, the thermal equilibrium temperature does not exist, and the equation (7) satisfies the following equation (9).
&Quot; (9) "
Figure 112015127614113-pat00065

(Equation 9)
Figure 112015127614113-pat00066
. 12. The method of claim 11,
And B 2 -4ac is equal to 0, the equation (7) satisfies the following equation (10): " (10) "
&Quot; (10) "
Figure 112015127614113-pat00067

(Equation 10)
Figure 112015127614113-pat00068
. 11. The method of claim 10,
To approximate this quadratic polynomial
The root mean square of the error of the temperature measured at a plurality of sample temperatures within the operating temperature range of the chip is minimized,
remind
Figure 112015127614113-pat00069
And
Figure 112015127614113-pat00070
B, c, and I, which are successive in the I,
wherein a, b and c represent a 1 , b 1 and c 1 in the first section and a 2 , b 2 and c 2 in the second section and the root mean square of the error is expressed by the following equation 11]. ≪ / RTI >
&Quot; (11) "
Figure 112015127614113-pat00071

(Where, N represents the number of sample temperatures). delete A computer-readable recording medium having recorded thereon a computer program for executing a method of thermal-power analysis of a highly integrated semiconductor chip on a computer,
Modeling a semiconductor chip and a package structure surrounding the semiconductor chip with a simplified semiconductor chip to establish a transient electrothermal equation representing power consumption over time, the package structure comprising a surface of the simplified semiconductor chip Lt; / RTI >
Approximating a power consumption depending on a temperature of the semiconductor chip in a first section of an operating temperature range of the semiconductor chip and a second section continuing to the first section with a second order polynomial; And
And calculating the temperature and power consumption of the semiconductor chip based on the electrothermal equation and the quadratic polynomial.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008225590A (en) * 2007-03-09 2008-09-25 Sony Corp Electronic device, supply power control method and program
US20100023903A1 (en) 2008-07-25 2010-01-28 Eddy Pramono Method and apparatus for multi-die thermal analysis
US20120210285A1 (en) 2008-06-24 2012-08-16 Vinod Kariat Method and apparatus for thermal analysis of through-silicon via (tsv)

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008225590A (en) * 2007-03-09 2008-09-25 Sony Corp Electronic device, supply power control method and program
US20120210285A1 (en) 2008-06-24 2012-08-16 Vinod Kariat Method and apparatus for thermal analysis of through-silicon via (tsv)
US20100023903A1 (en) 2008-07-25 2010-01-28 Eddy Pramono Method and apparatus for multi-die thermal analysis

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