KR101803014B1 - Light emitting diode - Google Patents

Light emitting diode Download PDF

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Publication number
KR101803014B1
KR101803014B1 KR1020110084680A KR20110084680A KR101803014B1 KR 101803014 B1 KR101803014 B1 KR 101803014B1 KR 1020110084680 A KR1020110084680 A KR 1020110084680A KR 20110084680 A KR20110084680 A KR 20110084680A KR 101803014 B1 KR101803014 B1 KR 101803014B1
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South Korea
Prior art keywords
layer
light emitting
type
pad portion
emitting diode
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KR1020110084680A
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Korean (ko)
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KR20130022030A (en
Inventor
김종규
이소라
양명학
곽준식
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서울바이오시스 주식회사
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Publication of KR20130022030A publication Critical patent/KR20130022030A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

A light emitting diode is disclosed. The light emitting diode includes a substrate; A plurality of light emitting cells formed on the substrate, each including a p-type region and an n-type region; And a wiring layer formed to connect the p-type region and the n-type region of the neighboring light emitting cells. The interconnection layer includes a contact layer / a reflective layer / a barrier layer / a bonding layer, the contact layer is formed of Ni, Cr, or Ti, the reflective layer is formed of Al, and the bonding layer is formed of Au do.

Description

[0001] LIGHT EMITTING DIODE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode including a compound semiconductor, and more particularly to an AC-driven light emitting diode.

BACKGROUND ART [0002] Light emitting diodes (LEDs) have been widely used in display devices and backlight devices, which are made of compound semiconductors, in particular compound semiconductors based on Group III nitride compounds. Recently, light emitting diodes The use area is widening.

A typical light emitting diode repeats on / off according to the direction of the current under an AC power supply. Therefore, when such a light emitting diode is directly connected to an AC power source, the light emitting diode does not emit light continuously, and is easily damaged by a reverse current. As a technique for solving the problem of such a light emitting diode, a light emitting diode which can be directly connected to a high voltage AC power source is disclosed in International Publication No. WO 2004/023568 (A1), "LIGHT-EMITTING DEVICE HAVING LIGHT Lt; / RTI > et al., Entitled " -EMITTING ELEMENTS. &Quot;

1 is a view for explaining a conventional AC light emitting diode. Referring to FIG. 1, the AC light emitting diode 1 includes quadrangular light emitting cells 4 formed by forming Group III nitride compound semiconductor layers on an insulating substrate, particularly, a sapphire substrate 2. On the substrate 2, electrode pads 3a and 3b are formed. Each of the light emitting cells 4 includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer sandwiched therebetween, and a transparent electrode layer such as an ITO layer may be formed thereon. In addition, the plurality of light emitting cells 4 are formed by dividing a plurality of the compound semiconductor layers as described above.

The conventional light emitting diode 1 includes an n-type electrode pad 6 and a p-type electrode pad 8 on the light emitting cell 4. In the light emitting cell 4, a part of the region is removed to a certain depth from the top, and a part of the middle layer of the light emitting cell 4 is exposed. The exposed layer is usually an n-type semiconductor layer, And an n-type electrode pad 6 is formed in one region of the layer. The p-type electrode pad 8 is formed in the p-side region on the uppermost layer of the light emitting cell 4. The n-type electrode pad 6 and the p-type electrode pad 8 are formed to be linear or bar-shaped and positioned to face each other at opposite corners of the light-emitting cell 4. The electrode pads 3a and 3b and the light emitting cells 4 therebetween are connected in series by the wires 5. The p-type electrode pad 8 and the n-type electrode pad 8 of adjacent light emitting cells are connected by the wiring 5. The wiring 5, the p-type electrode pad 8 and the n-type electrode pad 8 may be portions of the wiring layer formed together by the step cover process.

In such a conventional light emitting diode, when the distance between the n-type electrode pad 6 and the p-type electrode pad 8 is large in the light emitting cell, the current concentrates only on the periphery of the p- Type electrode pad 8, as shown in FIG. When the p-type electrode pad 8 is positioned close to the n-type electrode pad 6, the brightness of the region between the p-type electrode pad 8 and the n-type electrode pad 6 will increase. However, The brightness between the electrode pad 8 and the edge of the light emitting cell is greatly reduced. This greatly hinders the uniformity of light emission of the light emitting diode, and is a great obstacle to the large-sized light emitting diode.

In addition, there is a conventional type of light emitting diode in which both the n-type electrode pads and the p-type electrode pads are formed in a quadrangular or circular shape and these electrode pads are arranged to face diagonally at both corners of the light emitting cells. The light emitting diodes of the light emitting diodes were bright only around the p-type electrode pad 8, so that the uniformity of light emission was not good.

In addition, conventionally, a wiring layer including an n-type electrode pad, a p-type electrode pad, and a pad connecting portion connecting between them is formed by a step cover process, and the light emitting cells on the substrate are electrically connected to the wiring layer. At this time, conventionally, a wiring layer including a Cr / Au laminated structure is mainly used, Cr serves as a contact layer, and Au serves as a bonding layer. In the wiring layer of the conventional Cr (contact layer) / Au (bonding layer) structure, optical loss due to light absorption by Au is large.

One of the problems to be solved by the present invention is to provide a light emitting diode improved in luminous efficiency and light output by improving the reflectivity of a wiring layer including a p-type pad portion and an n-type pad portion without deteriorating electrical characteristics.

SUMMARY OF THE INVENTION Accordingly, one object to be solved by the present invention is to provide a light emitting diode including a plurality of light emitting cells on a substrate, through improvement in structure and arrangement of a p-type pad portion and an n- To provide a light emitting diode with an improved structure in which dispersion is good and its current dispersion becomes more uniform.

According to an aspect of the present invention, there is provided a light emitting diode comprising: a substrate; A plurality of light emitting cells formed on the substrate, each including a p-type region and an n-type region; And a wiring layer formed to connect the p-type region of the neighboring light emitting cells with the n-type region, wherein the wiring layer includes a lamination structure of a contact layer / a reflection layer / a barrier layer / a bonding layer, , Cr, or Ti, the reflective layer is formed of Al, and the bonding layer is formed of Au.

According to one embodiment, the method further comprises an adhesion enhancing layer formed on the bonding layer, wherein the adhesion enhancing layer comprises Ti.

According to one embodiment, the contact layer is a Ni layer having a thickness of 5 to 50 Angstroms.

According to one embodiment, the reflective layer is an Al layer having a thickness of 1000 to 3000 ANGSTROM, and the bonding layer is an Au layer having a thickness of 0.5 um or more.

According to one embodiment, the barrier layer preferably comprises a multi-layer structure in which Ni / Ti multilayer, Ni / Pt monolayer, or Ni / Pt is repeated.

According to one embodiment, the wiring layer includes a p-type pad portion formed in the p-type region, an n-type pad portion formed in the n-type region, and a p-type pad portion and an n- And a pad connecting portion for connecting the pad connecting portion.

According to an embodiment of the present invention, the straight lines connecting the center portion and both ends of the p-type pad portion are isosceles triangles, the straight line connecting the both ends of the n-type pad portion is parallel to the base of the isosceles triangle, The apex angle of the isosceles triangle is set at 90 degrees or more.

According to the present invention, the light emitting efficiency and the light output of the light emitting diode can be improved by improving the reflectivity of the p-type pad portion and the n-type pad portion without deteriorating the electrical characteristics. In addition, in the light emitting diode including a plurality of light emitting cells on a substrate, the present invention can improve the current dispersion effect through the optimal structure and arrangement of the p-type pad portion and the n-type pad portion which are a part of the wiring layer electrically connecting the light- have. Such optimum structure and optimal placement includes making the distance between the p-type pad portion and the n-type pad portion as close as possible and uniform throughout the predetermined area of the light emitting cell. In addition, by minimizing the area where the p-type pad portion and the n-type pad portion are not opposed to each other while minimizing the distance from the p-type pad portion to the n-type pad portion, .

1 is a plan view for explaining a conventional light emitting diode;
2 is a plan view illustrating a light emitting diode according to an embodiment of the present invention;
FIG. 3 is an enlarged plan view of a part of the light emitting diode shown in FIG. 2, and is a plan view for explaining light emitting cells adjacent to each other and a wiring layer pattern therebetween.
FIG. 4 is an enlarged plan view of a part of the light emitting diode shown in FIG. 2, and is a plan view for explaining a wiring layer pattern between the first light emitting block and its neighboring light emitting cell and between the first light emitting block and the light emitting cell.
FIG. 5 is an enlarged plan view of a part of the light emitting diode shown in FIG. 2, and is a plan view for explaining a wiring layer pattern between the second light emitting block and its neighboring light emitting cell, and between the second light emitting block and the light emitting cell.
6 is a cross-sectional view illustrating a cross-sectional structure of a light emitting diode according to an embodiment of the present invention.
6A and 6B are enlarged cross-sectional views for showing the cross-sectional structure of the above-described wiring layer in the n-type region and the p-type region, respectively, in the circle "D" Cross sections.
FIGS. 8A and 8B are photographs showing the results of a light emission uniformity test of a light emitting diode according to an embodiment of the present invention and a conventional light emitting diode (comparative example). FIG.
9A and 9B are photographs showing a comparison between the example using Ni as the contact layer and the example using Cr in the laminated structure of the wiring layer described in Fig.
10A and 10B are graphs comparing n-ohmic characteristics before heat treatment and n-ohmic characteristics after heat treatment when Cr is used as the contact layer in the lamination structure of the wiring layers illustrated in FIG.
11 is a graph comparing n-ohmic characteristic changes before and after the heat treatment when Ni is used as the contact layer in the lamination structure of the wiring layers described in Fig.
12 is a graph showing changes in forward voltage (VF) of light emitting diodes before and after heat treatment.
13 is a graph showing the change of the amorphous characteristics before and after the heat treatment depending on the type of the barrier layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience.

2 is a plan view illustrating a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 2, the light emitting diode includes a substrate 20 and a plurality of light emitting cells 40. An n-type pad portion 60 and a p-type pad portion 80 are formed on each of the light emitting cells 40. The plurality of light emitting cells 40 are formed on a single substrate 20 and the n-type pad unit 60, the p-type pad unit 80 and the adjacent light emitting cells 40, 40 Type pad portion 60 and the p-type pad portion 80 connecting the n-type pad portion 60 and the p-type pad portion 80 between the first and second pad portions 80 and 80 '.

In this embodiment, the n-type pad portion 60, the p-type pad portion 80, and the pad connecting portion 52 are included in one wiring layer (i.e., step cover layer) Which are formed integrally and simultaneously.

In addition, the light emitting diode according to the present embodiment includes a p-type first electrode pad 80 'and an n-type second electrode pad 60 "so that power can be received from the outside, The first electrode pad 80 'and the second electrode pad 60' 'are formed in the first light emitting block 40' and the second light emitting block 40 ', respectively.

The first and second light emitting blocks 40 'and 40' 'include a first electrode pad 80' and a second electrode pad 60 '' as input and output terminals. But the term " light-emitting block " is defined for the purpose of distinguishing it from other light-emitting cells 40 in this specification.

The first light emitting block 40 'includes the terminal n-type pad portions 60' and 60 'together with the p-type first electrode pad 80', and the second light emitting block 40 ' And a terminal p-type pad portion 80 " together with the n-type second electrode pad 60 ".

As described above, the pad connecting portion 52 connects the n-type pad portion 60 and the p-type pad portion 80 of the neighboring light emitting cells 40, 40. Between the terminal n-type pad portions 60 ', 60' of the first light emitting block 40 'and the p-type pad portion 80 of the adjacent light emitting cell 40 at one end of the array, And are connected by connection portions 52 'and 52'.

The second terminal pad connection portion 52 '' is formed between the p-type pad portion 80 '' of the second light emitting block 40 '' at the other end of the array and the n-type pad portion 60 of the adjacent light emitting cell 40 ' ).

In the present embodiment, the first and second electrode pads 80 'and 60' ', the terminal n-type pad portion 60' and the terminal p-type pad portion 80 ' The connection portions 52 ', 52 " can also be formed integrally and simultaneously with the wiring layer as described above. That is, the distal and middle n-type pad portions 60 ', 60, the distal and middle p-type pad portions 80 ", 80, the distal and middle pad connections 52', 52" All belong to one wiring layer formed at the same time, but are term-defined as described above according to their respective positions and functions.

Although not shown, the light emitting cells 40 may be formed of two or more arrays on a single substrate, and these arrays may be connected in antiparallel connection so as to be driven under an AC power source.

According to the present embodiment, the pad connecting portions 52, 52 ', 52 " serving as wirings are formed integrally and simultaneously with the n-type pad portions 60 and 60' and the p-type pad portions 80 and 80 & But it is also conceivable to form the n-type pad portion and the p-type pad portion first and connect the neighboring n-type pad portion and the p-type pad portion to the later-formed pad connection portion of the layered or wire structure.

An insulating substrate capable of electrically insulating the light emitting cells 40 is used for the substrate 20. As the growth substrate for growing the nitride semiconductor layers constituting the light emitting cells 40, a sapphire substrate is preferred. The light emitting cells 40 may be formed to have the same area, but may have different areas. The light emitting cells 40 may sequentially include an n-type semiconductor layer, an active layer, and a p-type semiconductor layer from the substrate 20, and a transparent electrode layer such as an ITO layer may be formed on the p- .

FIG. 3 shows an enlarged view of two neighboring light emitting cells 40 and 40.

Referring to FIG. 3, each of the light emitting cells 40 includes a substantially rectangular frame having first and second lateral sides S1 and S2 and first and second long sides S3 and S4. The first and second lateral sides S1 and S2 have a longer length than the first and second long sides S3 and S4. The light emitting cells 40 may be formed of a plurality of light emitting cells 40 that share the right and left edges of most of the edges thereof, that is, the first and second long sides S3 and S4, the second side S2 and the first side S1, Type region 40p and an n-type region 40n defined between one side edge of the light emitting cell 40, that is, between the first lateral side S1 and the P-type region 40p.

The n-type region 40n is formed by partially etching a part of the depth of the active layer and the p-type semiconductor layer, and additionally the n-type semiconductor layer in the laminated structure of the light emitting cells including the n-type semiconductor layer, the active layer and the p- And the n-type semiconductor layer is exposed in a relatively concaved form. A transparent electrode layer such as an ITO layer may be formed on the p-type semiconductor layer. In this case, the upper surface of the transparent electrode layer directly contacts the p-type pad portion 80 in the p-type region 40n.

 In this embodiment, the n-type region 40n is present in a partial length region of the center of the first lateral side S1, and a linear n-type pad portion 60 is formed in the n- And is formed parallel to the lateral side S1. In this embodiment, for the purpose of preventing the area of the p-type region 40p from being reduced, the n-type region 40n is formed only in a part of the center of the first lateral side S10, The n-type region 40n can be formed over substantially the entire length of the step S10. Also in this case, the n-type pad portion 60 may be formed in a straight line parallel to the first lateral side S1 at a position adjacent to the first lateral side S1.

On the p-type region 40p, a p-type pad portion 80 formed in a substantially linear shape at a position adjacent to the second lateral side S2 is provided. The p-type pad portion 80 is laterally symmetrical with respect to a vertical center line passing through the center portion c thereof and the center of the n-type pad portion 60.

The lateral length of the p-type pad portion 80 is larger than the lateral length of the n-type pad portion 60 and the center portion c is biased toward the second lateral side S2. An isosceles triangle having a vertex angle of 90 degrees or more is formed when a center portion (c) of the P-type pad portion (80) and both ends of the P-type pad portion (80) are connected by a straight line. The arrangement and structure of the pad portions 60 and 80 are such that the n-type pad portion 60 and the p-type pad portion 80 face each other despite the lateral length of the relatively small n-type pad portion 60 And the distance from each of both ends of the n-type pad portion 60 to both ends of the p-type pad portion 80 is reduced.

However, when the p-type pad portion 80 is formed with the same trajectory as the isosceles triangle described above, the region between the p-type pad portion 80 and the rear edge thereof, that is, 80 will not be confronted with the n-type pad portion 60 will become larger.

The area of such a region is set such that the p-type pad portion 80 is connected to the main pad portion 82 of an arcuate or straight shape and the first lateral portion 82 adjacent to the n-type pad portion 60 from both ends of the main pad portion 82 And a pair of straight outer pad extending portions 84 extending toward the outer circumferential surface S1. The end portions of each of the pair of outer pad extending portions 84 serve as both ends of the p-type pad portion 80. In this case, since the main pad portion 82 and the outer pad extension portion 84 are biased rearward from the both sides of the isosceles triangle toward the second lateral side S1, the P-type pad portion 80 may be formed in the shape or pattern of the above-described structure, which is an isosceles triangle formed by straightly connecting the both ends of the pad portion 60 and the center portion c of the pad portion 60 without decreasing the area of the region not facing the n-type pad portion 60 .

Also, it is preferable that the main pad portion 82 is formed in an arcuate shape in which straight lines or curved lines intersecting upward with respect to the center portion c. In addition, each of the pair of outer pad extension portions 84 preferably extends in the vertical direction from the main pad portion 82, that is, parallel to the first and second long sides S3 and S4.

The p-type pad portion 80 includes a center pad extension portion 83 extending in the vertical direction from the center portion c of the main pad portion 82 to the n-type pad portion 60 ). So that the center portion c and pad portions in the vicinity of the center portion c are not separated from the n-type pad portion 60 too far. At this time, the minimum distance from each of the outer pad extending portions 84 to the n-type pad portion 60 is greater than or equal to the minimum distance from the central pad extending portion 83 to the n-type pad portion 60 .

The n-type pad portion 60 and the p-type pad portion 80 are formed on the basis of a virtual vertical straight line passing through the center of the n-type pad portion 60 and the center portion c of the p- It is good that all are symmetrical structure. In the present embodiment, the central portion c of the p-type pad portion 80 and the linear n-type pad portion 60 are parallel to the base of the isosceles triangle formed by straight lines, At this time, the linear length of the n-type pad portion 60 is shorter than the base of the isosceles triangle as described above. At this time, even if the n-type pad portion 60 does not have a complete linear shape, a straight line connecting both ends of the n-type pad portion 60 is parallel to the base of the isosceles triangle and shorter than the base side good. Further, the base side is parallel to the first lateral side S1 and the second lateral side S2 constituting the long side of the rim of the light emitting cell.

The pad connection part 52 is formed to pass through a gap between two neighboring light emitting cells 40 and 40 so that the n-type pad part 60 and the p-type pad part 80 of the two adjacent light emitting cells 40, ). As described above, it is preferable that the pad connecting portion 52, the n-type pad portion 60 and the p-type pad portion 80 are included in a single step cover layer or wiring layer formed by the step cover process Do. 3, the pad connecting portion 52 is formed to connect the center portion (c) of the p-type pad portion 80 with the center of the n-type pad portion 60. However, in a position where the arrangement of the light emitting cells 40 is difficult, it is preferable that the pad connecting portion 52 is connected at one end to the pad portion, in particular, the bent point or the intersection point of the p-type pad portion 80 Reference)

Referring to FIG. 4, a first light emitting block 40 'and a neighboring neighboring light emitting cell 40 are enlarged.

Referring to FIG. 4, the first light emitting block 40 'is located at a corner of the edge of the substrate, and is substantially parallel to the neighboring light emitting cells 40. The first light emitting block 40 'and the light emitting cell 40 are formed together by the same processes so that the first light emitting block 40' The same semiconductor layers as those of the first embodiment are included in the same structure.

The first light emitting block 40 'includes opposing lateral sides corresponding to the first and second lateral sides S1 and S2 and the first and second longitudinal sides S3 and S4 of the light emitting cells 40, And includes a substantially rectangular frame having facets facing each other.

Like the light emitting cell 40, the first light emitting block 40 'has a length longer than that of each of the lateral sides, respectively. The first light emitting block 40 'includes a rectangular P-type region 40p', an n-type region 40p 'defined between a part of the rim of the first light emitting block 40' and the P-type region 40p ' 40n 'in the upper portion. The n-type region 40n 'includes a region formed along each of two edges of the first light emitting block 40' and a both edge region of a lateral side adjacent to the light emitting cell.

The n-type region 40n 'of the first light emitting block 40' is formed by partially laminating the active layer and the p-type semiconductor layer in the laminated structure of the light emitting cells including the n-type semiconductor layer, the active layer and the p- And the n-type semiconductor layer is exposed in a relatively concaved form. A transparent electrode layer such as an ITO layer may be formed on the p-type semiconductor layer. In this case, the upper surface of the transparent electrode layer is directly connected to the p-type first electrode pad 80 ' Touch.

The p-type first electrode pad 80 'is electrically connected to an external power source by, for example, bonding wires to serve as a terminal of the light emitting diode. A p-type first electrode pad 80' As shown in Fig. In the n-type region 40n 'of the first light emitting block 40', a pair of terminal n-type pad portions 60 'and 60' are formed symmetrically.

Each of the pair of terminal n-type pad portions 60 'and 60' is separated from the upper and lower lateral sides of the first light emitting block 40 'in a predetermined length region of the upper transverse center adjacent to the light emitting cell 40 Symmetrically along left and right sides and right and left longitudes of the upper transverse side of the first light emitting block 40 '. The two divided terminal n-type pad portions 60 'and 60' are connected to the single p-type pad portion 80 of the neighboring light emitting cell 40 by two symmetrical terminal pad connection portions 52 'and 52' , And the end pad connection portions 52 'and 52' are integrated in the p-type pad portion 80. It is preferred that the two end pad connection portions 52 'and 52' are symmetrical in the left and right direction and have a line shape parallel to each other.

The structure in which the connection structure between the first light emitting block 40 'and the neighboring light emitting cell 40, that is, the n-type pad portions and the pad connecting portions divided into two, It makes the dispersion better.

In the meantime, a certain length region of the center of the upper transverse portion where the two n-type pad portions 60 'and 60' of the first light emitting block 40 'are separated includes the p-type region of the first light emitting block 40' Type region 40p ', which is caused by the location of the first electrode pad 80' having a relatively large area on the p-type region 40p ' To compensate for the reduction of the light emitting area in the light emitting device.

Referring to FIG. 5, a second light emitting block 40 '' and a neighboring neighboring light emitting cell 40 are enlarged.

Referring to FIG. 5, the second light emitting block 40 '' is located at the other corner of the edge of the substrate and is substantially parallel to the neighboring light emitting cell 40 '. The second light emitting block 40 '' may be positioned diagonally to the first light emitting block 40 '. The second light emitting block 40 '' and the light emitting cell 40 are formed together by the same processes so that the second light emitting block 40 ' The same semiconductor layers as those of the first embodiment are included in the same structure.

The second light emitting block 40 " has opposing lateral sides corresponding to the first and second lateral sides S1 and S2 and the first and second longitudinal sides S3 and S4 of each light emitting cell 40, And includes a substantially rectangular frame having facets facing each other.

Like the light emitting cell 40, the second light emitting block 40 " has a length longer than each of the lateral sides of each of the lateral sides. The second light emitting block 40 " includes an n-type region 40p ' ' defined between the rim of the light emitting block and the p-type region 40p "Quot; 40n "). At this time, the n-type region 40n " includes a region that is concavely extended from the center of the upper lateral center to the p-type region of the rim of the second light emitting block 40 " Shaped second electrode pad 60 " is formed.

The n-type region 40n " of the second light-emitting block 40 " is formed by laminating the active layer and the p-type semiconductor layer in the laminated structure of the light emitting cells including the n-type semiconductor layer, the active layer and the p- To expose the n-type semiconductor layer in a relatively concaved form. A transparent electrode layer such as an ITO layer may be formed on the p-type semiconductor layer. In this case, a terminal p-type pad portion 80 " is directly formed on the upper surface of the transparent electrode layer of the p-type region 40p " .

The n-type second electrode pad 60 " is electrically connected to an external power source, for example, by a bonding wire, and serves as a terminal of the light emitting diode. The terminal p-type pad portion 80 " formed in the p-type region 40p " of the second light emitting block 40 " is connected to the imaginary vertical straight line & Which is symmetrical with respect to the center of the cup. Due to the shape of the cup cross-section, the terminal p-type pad portion 80 " is formed such that the main pad portion 82 " and the second electrode pad 60 " from both ends of the main pad portion 82 " And a pair of straight, outline pad extensions 84 ", 84 " In addition, the terminal p-type pad portion 80 " has a central portion c " in the main pad portion 82, which is biased vertically toward the neighboring light emitting cells 40, do.

The linear n-type pad portion 60 of the light emitting cell 40 and the p-type pad portion 80 " of the second light emitting block 40 " are electrically connected to the n-type pad portion 60 And is electrically connected by a terminal pad connection portion 52 " having a center portion c " of the terminal p-type pad portion 80 " on the second light emitting block 40 "

In addition, the terminal p-type pad portion 80 " of the second light emitting block 40 " has a cup cross-sectional shape surrounding the front surface and both sides of the second electrode pad 60 " ≪ / RTI > the current spreading in the " 40 "

6 is a cross-sectional view illustrating a cross-sectional structure of a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 6, the light emitting diode includes a single substrate 20, and a plurality of light emitting cells 40 as described above are formed on the single substrate 20. Each of the light emitting cells 40 includes an n-type semiconductor layer 42, a p-type semiconductor layer 44 located on one region of the n-type semiconductor layer 42, -Type semiconductor layer 44. The active layer 43 is formed of a single-crystal semiconductor. In addition, the light emitting diode includes a transparent electrode layer 46 in each light emitting cell 40. In addition, the light emitting diode includes an insulating layer 99 and a wiring layer 100. In the present embodiment, the wiring layer 100 is formed by a step cover process and includes the n-type pad portion 60, the p-type pad portion 80, and the pad connecting portion 52 integrally do. In addition, the light emitting diode may include a buffer layer 41 under the light emitting cell 40.

Referring again to FIG. 6, the n-type semiconductor layer 42, the active layer 43 and the p-type semiconductor layer 44 are formed of a gallium nitride semiconductor material, that is, (B, Al, In, Ga) N As shown in FIG. The n-type semiconductor layer 42 and the p-type semiconductor layer 44 are formed on the active layer 43 so as to emit light of a desired wavelength, for example, ultraviolet light or blue light, Is formed of a material having a larger band gap. The n-type semiconductor layer 42 and / or the p-type semiconductor layer 44 may be formed as a single layer or may have a multi-layer structure as shown in the figure. In addition, the active layer 43 may have a single quantum well structure or a multiple quantum well structure.

The n-type semiconductor layer 42 has stepped portions formed on the sidewalls. The n-type region 40n '(see Fig. 4) as described above is formed by the step portion. Here, the light emitting cell portion formed above the step portion with respect to the step portion formed on the n-type semiconductor layer 42 is defined as a mesa. The mesa sidewall may be inclined so that the width of the mesa becomes narrower as it goes up. The inclination angle of the mesa sidewalls with respect to the upper surface of the substrate 20 may be in the range of 15 degrees to 80 degrees. On the other hand, the n-type semiconductor layer 42 located under the mesa may also have a sloped side wall as it goes up from the substrate 20. The inclination angle of the sidewall of the n-type semiconductor layer 42 with respect to the upper surface of the substrate 20 may be in the range of 15 degrees to 80 degrees.

The inclined structure described above helps conformal deposition of other layers, such as the insulating layer 99 and the wiring layer 100, to be formed on the light emitting cells 40. Further, although not shown, a secondary insulating layer covering the elements entirely may be formed.

The inclination angle of the mesa sidewall may be the same as the inclination angle of the sidewall of the lower semiconductor layer 42 below the mesa sidewall, but the inclination angle may be adjusted differently. For example, the inclination angle of the mesa sidewall may be smaller than the inclination angle of the side wall of the n-type semiconductor layer 42. Accordingly, light generated in the active layer 43 can be easily emitted through the mesa sidewalls, thereby improving light extraction efficiency and securing a relatively wide light emitting cell region.

On the other hand, the above-described buffer layer 41 is adopted for alleviating the lattice mismatch between the substrate 20 and the n-type semiconductor layer 42 to be formed thereon, when the substrate 20 is a growth substrate, in particular, a sapphire substrate.

The transparent electrode layer 46 may be located on the upper surface of the upper semiconductor layer 44 and may have a smaller area than that of the upper semiconductor layer 44. That is, the transparent electrode layer 46 can be recessed from the edge of the upper semiconductor layer 44. Therefore, it is possible to prevent current from concentrating through the side wall of the light emitting cell 40 at the edge of the transparent electrode layer 46.

On the other hand, the insulating layer 99 covers the light emitting cells 40 almost entirely. The insulating layer 99 has openings on the n-type semiconductor layers 42 and also has openings on the p-type semiconductor layers 44 or the transparent electrode layer 46. On the other hand, the side walls of the light emitting cells 40 are covered with an insulating layer 99. The insulating layer 99 may also cover the substrate 20 in regions between the light emitting cells 40. The insulating layer 99 may be formed of a silicon oxide film (SiO 2 ) or a silicon nitride film.

A wiring layer 100 is formed on the insulating layer 67. [ The wiring layer 100 may be formed in the n-type region on the n-type semiconductor layer 42 and the p-type region on the p-type semiconductor layer 44 or the transparent electrode layer 46 through the openings in a predetermined pattern. At this time, the wiring layer 100 includes at least an n-type pad 60, a p-type pad 80, and a pad connecting portion 52 as shown in FIG.

The wiring layer 100 may be electrically connected to the underlying p-type semiconductor layer 44 through the transparent electrode layer 46. The wiring layer 100 electrically connects the n-type semiconductor layer 42 and the p-type semiconductor layer 44 of the adjacent light emitting cells 40 and 40 to form a serial array of the light emitting cells 40. A plurality of such arrays may be formed, and a plurality of arrays may be connected in antiparallel to each other and connected to an AC power source to be driven. Further, a bridge rectifier (not shown) connected to the serial array of the light emitting cells may be formed, and the light emitting cells may be driven by the bridge rectifier under the AC power. The bridge rectifier may be formed by connecting the light emitting cells having the same structure as the light emitting cells 40 by using wiring layers or wires. The wiring layer or wirings may be formed of a conductive material, for example, a doped semiconductor material such as polycrystalline silicon, or a metal.

Further, a secondary insulation layer 130 is further formed as a protective insulation layer so as to cover and protect the upper and side surfaces of the light emitting cells in which the wiring layer 100 is formed. The secondary insulation layer 130 may be made of SiO 2.

6A and 6B are enlarged cross-sectional views for showing the cross-sectional structure of the above-described wiring layer in the n-type region and the p-type region, respectively, in the circle "D" Sectional views.

As shown in Fig. 7A, the wiring layer 100 is formed on the n-type semiconductor layer 42 in the n-type region 40n (see Fig. 3). In addition, as shown in Fig. 7B, a p-type region 40p (see Fig. 3) is formed on the transparent electrode layer 46 on the p-type semiconductor layer 43. [ The wiring layer 100 may have a structure of a contact layer 101, a reflective layer 103, a barrier layer 106, a bonding layer 109, and an adhesion strengthening layer 111.

The contact layer 101 has a thickness in the range of 5 to 50 angstroms and is used for ohmic contact to the n-type semiconductor layer 42 of the n-type region 40n (see FIG. 3). The contact layer 101 may be formed of Ni, Cr, or Ti. When Ni is used for the contact layer 101, a relatively n-ohmic contact can be achieved with a relatively thin thickness, for example, a thickness of about 5 Å, so that the light loss can be reduced. The reflective layer 103 reflects the light generated in the active layer 43 to form pads and electrode pads 60, 60 ', 60 ", and 80' provided in the n- and p-regions of the light emitting cells and / , 80 ', 80 ", refer to Figs. 2 to 5) to prevent light from being absorbed and lost in the pad portions and the electrode pads. The reflective layer 103 is formed of aluminum (Al). The reflective layer 103 may have a thickness of about 1000 to 3000 ANGSTROM. The barrier layer 106 is used to prevent the intermixing of the bonding layer metal and the reflective layer metal to maintain the reflective function of the reflective layer 103. The barrier layer 106 may be formed of a dual layer 106a or 106 such as Cr / Pt, Ni / Ti, or Ni / Pt, but is not limited thereto. For example, Or Ni / Ti / Ni / Ti. The bonding layer 109 is formed of a bonding metal for bonding a bonding wire (not shown), and is formed of Au in this embodiment. The bonding layer 109 may be formed to a thickness of 1 um or more. In the wiring layer of the conventional Cr (contact layer) / Au (bonding layer) structure, optical loss due to light absorption by Au is large. However, according to this embodiment, by applying the Al reflection layer 103 on the contact layer 101, the optical loss can be greatly reduced in the region where the wiring layer 100 is present.

The Al reflective layer in the wiring layer 100, that is, the Al layer 103 is formed by reducing the resistance of the wiring layer 100 while minimizing the cross-sectional area of the Au bonding layer, that is, the Au layer 109, Thereby improving the efficiency of the light emitting diode. The resistance can be reduced by increasing the sectional area of the Au layer 109 in the wiring layer 100. In this case, the area occupied by the wiring layer 100 on the upper surface of the light emitting cell 40, which is the main light emitting surface of the light emitting cell 40 And the light emitting area of the light emitting cell 40 is reduced. Also, Au, which is a high-priced material, is often used, which causes a problem of an increase in manufacturing cost of the light emitting diode. According to this embodiment, the cross-sectional area of the wiring layer 100 is increased by the Al layer 103 added to the Au layer 109, thereby reducing the resistance. For example, by increasing the cross-sectional area (or thickness) of the Al layer 103 by keeping the cross-sectional area of the Au layer 109 equal to the cross-sectional area of the wiring layer including the conventional Cr (contact layer) / Au (bonding layer) Reducing resistance and increasing power efficiency. The structure for lowering the resistance of the wiring layer 100 by applying the Al layer 103 instead of increasing the cross-sectional area of the Au layer 109 is economically very advantageous because Al is lower in cost than Au.

However, Al and Au are materials that are likely to be intermixed chemically by diffusion. Therefore, the light emitting diode according to the present embodiment has the barrier layer 106 interposed between the Al reflective layer 103 and the Au bonding layer 109 as described above. The barrier layer 106 is positioned between the Al reflective layer 103 and the Au bonding layer 109 to prevent chemical diffusion between the Al reflective layer 103 and the Au bonding layer 109, The function of lowering the resistance of the wiring layer without increasing the cross-sectional area of the Au bonding layer 109 and the function of reducing the loss due to the light absorption, functions to increase the power efficiency under the Au bonding layer 109.

The adhesion strengthening layer 111 is made of Ti. The Ti adhesion strengthening layer 111 enhances the adhesion with SiO 2 constituting the secondary insulation layer 130 formed on the wiring layer 100 and thereby suppresses the peeling of the secondary insulation layer .

As described above, the wiring layer 100 having the structure of the contact layer / Al reflection layer / barrier layer / Au bonding layer 109 / adhesive strengthening layer has a reflectivity of 70 to 80% It was confirmed that the reflectivity was greatly improved from 30 to 45%.

[Experimental Example 1]

8A and 8B are photographs showing the results of the light emission uniformity test of a light emitting diode according to an embodiment of the present invention and a conventional light emitting diode (comparative example). The electrical characteristics of the comparative example were tested and compared. In both the example and the comparative example, an ITO layer having a thickness of 1200 ANGSTROM was used on the light emitting cell.

8A and 8B are photographs showing the results of the light emission uniformity test of a light emitting diode according to an embodiment of the present invention and a conventional light emitting diode (comparative example). The electrical characteristics of the comparative example were tested and compared. In both the example and the comparative example, an ITO layer having a thickness of 1200 ANGSTROM was used on the light emitting cell.

 As can be seen from the following Table 1, it can be seen that the power efficiency (light output) and power efficiency of the light emitting diode according to the present embodiment are greatly improved as compared with the light emitting diode of the comparative example. There is almost no difference in the forward voltage.

division Forward voltage Power Power efficiency
WPE (%) Avg. [V] Std Avg. [mW] Std Comparative Example 56.92 2.70 362.87 19.19 31.88 Example 56.82 0.55 418.5 5.7 36.8

The light emitting diode of this embodiment shown in Fig. 8A has a uniform brightness throughout the light emitting cell, whereas the light emitting diode of the comparative example shown in Fig. 8B has a large brightness difference between a portion close to the p- have. It should be noted that the regions appearing relatively dark in FIGS. 8A and 8B are actually light emitting regions.

The light emitting diode of this embodiment shown in Fig. 8A has a uniform brightness throughout the light emitting cell, whereas the light emitting diode of the comparative example shown in Fig. 8B has a large brightness difference between a portion close to the p- have. It should be noted that the regions appearing relatively dark in FIGS. 8A and 8B are actually light emitting regions.

[Experimental Example 2]

Figs. 9A and 9B are photographs showing a comparison between the example using Ni as the contact layer and the example using Cr in the laminated structure of the wiring layers described in Fig. 7. From these photographs, it was confirmed that the crystal of Ni shown in Fig. 9A is superior to the crystal of Cr shown in Fig. 9B.

[Experimental Example 3]

Figs. 10A and 10B are graphs showing n-ohmic characteristics before heat treatment and n-ohmic characteristics after heat treatment when Cr is used as a contact layer in the lamination structure of the wiring layers described in Fig. 7, 12 is a graph showing changes in the forward voltage (VF) of the light emitting diode before and after the heat treatment in comparison with that in the case of using the contact layer of Ni in the lamination structure of the wiring layers Graph.

Referring to FIGS. 10A, 10B, 11 and 12, when Ni is used as the contact layer, there is substantially no change in the n-ohmic characteristic due to the heat treatment process, whereas when Cr is used as the contact layer, - It is confirmed that the change of the Ohmic characteristic is large.

[Experimental Example 4]

[Table 2] below shows the difference in reflectivity and forward voltage of various samples in which the material of the barrier layer and the lamination structure in the lamination structure of the wiring layer described in Fig. 7 are different. At this time, Ni was used as the contact layer, Al was used as the reflective layer, Au was used as the bonding layer, and Ti was used as the adhesion strengthening layer in all the samples.

Sample Reflectivity (%) Forward voltage
(as-dep / SSP) Cr / Pt (reference) 76.6 ↑ 55.3 / 55.8 V  Ni / Pt 77.5 55.3 / 55.5 V Ni 1000 Å 78.1 55.4 / 55.6 V Ni / Ti 78.3 55.4 / 56.3 V (Ni / Ti) 2 77.9 55.3 / 55.5 V

13 is a graph showing changes in the ohmic characteristics before and after the heat treatment depending on the type of the barrier layer. From FIG. 13, no substantial change in the ohmic characteristics was found before and after the heat treatment due to all the barrier layers used in the experiments.

Claims (7)

Board;
A plurality of light emitting cells formed on the substrate, each including a p-type region and an n-type region; And
And a wiring layer formed to connect the p-type region and the n-type region of neighboring light emitting cells,
Wherein the wiring layer includes a laminated structure of a contact layer / a reflective layer / a barrier layer / a bonding layer,
Wherein the contact layer is formed of Ni, Cr, or Ti, the reflective layer is formed of Al, the bonding layer is formed of Au,
The wiring layer includes a p-type pad portion formed in the p-type region, an n-type pad portion formed in the n-type region, and a pad connection portion connecting the p-type pad portion and the n-type pad portion of the adjacent light-
Wherein the straight lines connecting the center portion and both ends of the p-type pad portion form an isosceles triangle,
Wherein the n-type pad portion has a straight line connecting both ends parallel to the base of the isosceles triangle and smaller than the base,
Wherein the apex angle of the isosceles triangle is 90 degrees or more. The light emitting diode of claim 1, further comprising an adhesion strengthening layer formed on the bonding layer, wherein the adhesion strengthening layer comprises Ti. The light emitting diode of claim 1, wherein the contact layer is a Ni layer having a thickness of 5 to 50 angstroms. [4] The light emitting diode of claim 3, wherein the reflective layer is an Al layer having a thickness of 1000 to 3000 ANGSTROM, and the bonding layer is an Au layer having a thickness of 0.5 mu m or more. The light emitting diode of claim 1, wherein the barrier layer comprises a Ni / Ti multilayer, a Ni / Pt monolayer, or a multi-layer structure in which Ni / Pt is repeated. delete delete
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005150386A (en) 2003-11-14 2005-06-09 Stanley Electric Co Ltd Semiconductor device and its manufacturing method
KR100652864B1 (en) 2005-12-16 2006-12-04 서울옵토디바이스주식회사 Light emitting diode having an improved transparent electrode structure for ac power operation
JP2010529697A (en) * 2007-06-12 2010-08-26 セミエルイーディーズ コーポレーション Vertical LED with current induction structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005150386A (en) 2003-11-14 2005-06-09 Stanley Electric Co Ltd Semiconductor device and its manufacturing method
KR100652864B1 (en) 2005-12-16 2006-12-04 서울옵토디바이스주식회사 Light emitting diode having an improved transparent electrode structure for ac power operation
JP2010529697A (en) * 2007-06-12 2010-08-26 セミエルイーディーズ コーポレーション Vertical LED with current induction structure

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