KR101736796B1 - Apparatus and method for reducting noise of data signal - Google Patents

Abstract

The present invention provides an apparatus and a method for removing noise of a data signal, which adopt an automatic adaptive removal method in a noise removal structure using an analog signal. According to the present invention, the apparatus comprises: a data transition determining unit to determine whether data transition exists in an adjacent channel adjacent to a specific channel selected among two or more channels when using the two or more channels to transmit data; a signal gain calculation unit to calculate a gain of a first signal for transmitting data in the specific channel based on a polarity of a second signal related to data transition if the data transition is determined to exist in the adjacent channel; and a noise removal unit to finally remove noise from the first signal based on the gain of the first signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an apparatus and a method for removing noise of a data signal,

The present invention relates to an apparatus and a method for eliminating noise. And more particularly, to an apparatus and method for removing noise from a signal transmitting data.

When a data signal is transmitted from a transmission medium to a reception medium through a transmission path, various types of noise may be mixed with the data signal received by the reception medium. For example, when a data signal is transmitted using a plurality of channels connected in parallel, there is crosstalk noise in the noise mixed in the data signal.

However, the conventional noise cancellation method using a digital signal has a problem that the reliability of data is lowered because it can not effectively remove such crosstalk noise.

Also, the crosstalk noise becomes stronger as the interval is narrower between a plurality of channels connected in parallel. In the conventional noise cancellation method using a digital signal, there is a problem that the rate of removing crosstalk noise varies depending on the interval between channels have.

Korean Patent No. 393,621 proposes a device for removing noise from a data signal. However, the above-described problem can not be solved because this device uses digital signals to remove noise.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an apparatus and method for removing a noise of a data signal by adopting an automatic adaptive removal method in a noise canceling structure using an analog signal.

However, the objects of the present invention are not limited to those mentioned above, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

The present invention has been conceived to achieve the above-mentioned object, and it is an object of the present invention to provide a data transmission method and a data transmission method for transmitting data using at least two channels, A data transition judging unit for judging whether or not the data is transposed; A signal gain calculating unit for calculating a gain of a first signal transmitting data in the specific channel based on a polarity of a second signal related to the data transition if it is determined that the data transition is present in the adjacent channel; And a noise canceller for finally removing noise from the first signal based on the gain of the first signal.

Preferably, the data transition determining unit determines whether the data transition is present based on whether or not there is a potential difference in relation to the second signal transmitting the data in the adjacent channel.

Preferably, the noise canceller of the data signal includes: a first differential converter for converting a signal input to the specific channel into a first differential signal; And a differential signal processor for first removing the noise from the first differential signal using a signal input to the adjacent channel, wherein the signal gain calculator calculates the first differential signal having the noise removed first And is used as the first signal.

Preferably, the differential signal processing unit adds the signal obtained by differentiating the signal input to the adjacent channel to the first differential signal to remove the noise first.

Preferably, the differential signal processing unit first removes the noise using an adder based on current-based control or DAC (Digital Analog Converting) -based control.

Preferably, the noise canceller of the data signal may further include a second timing signal generator that generates a second timing signal when there is a potential difference between the first timing signal when there is no potential difference and the second timing signal when there is a potential difference A signal dividing section for dividing; And a signal polarity determination unit for determining the polarity of the second timing signal, wherein the signal gain calculation unit calculates a gain of the first signal based on the polarity of the second signal and the polarity of the second timing signal .

The apparatus may further include a sampling unit that samples the first timing signal and the second timing signal when the first signal is divided into the first timing signal and the second timing signal, And a delay unit for delaying the first timing signal sampled using different clock cycles and the sampled second timing signal, respectively, wherein the signal polarity determination unit determines the first polarity of the first And calculates a gain of the first signal based on the timing signal and the second timing signal.

Preferably, the apparatus for removing noise of the data signal includes a digital signal converter for converting the sampled first timing signal and the sampled second timing signal from a differential CML digital signal into a single-ended CMOS digital signal Wherein the delay unit delays the second timing signal by using a latch that delays a half clock cycle and a D flip flop that delays a clock cycle and uses two D flip flops that delay one clock cycle Thereby delaying the first timing signal.

Preferably, the signal gain calculating unit calculates a gain of the first signal based on signals obtained by integrating the first timing signal and the second timing signal.

Preferably, the signal gain calculator calculates a gain of the first signal based on a current of a charge pump, an integration capacitance, an AGC (Automatic Gain Control) gain, and a predetermined necessary factor, .

Preferably, the noise canceller is used to transmit the data to the wired line using the channels arranged in parallel.

In addition, the present invention provides a method for transmitting data using at least two channels, comprising the steps of: determining whether there is a data transition in an adjacent channel adjacent to a specific channel selected from the at least two channels; Calculating a gain of a first signal transmitting data in the specific channel based on a polarity of a second signal related to the data transition if it is determined that the data transition is present in the adjacent channel; And finally removing noise from the first signal based on the gain of the first signal.

Preferably, the determining step determines whether the data transition is present based on whether or not there is a potential difference in relation to the second signal transmitting the data in the adjacent channel.

Preferably, the step of converting the signal input to the specific channel into a first differential signal between the determining step and the calculating step may include: And first removing the noise from the first differential signal using a signal input to the adjacent channel, wherein the calculating step comprises: a step of removing the first differential signal from which the noise is first removed, 1 signal.

Preferably, the first removing step adds the signal obtained by differentiating the signal input to the adjacent channel to the first differential signal to remove the noise first.

Advantageously, the first removing step first removes the noise using an adder based on current based control or DAC (Digital Analog Converting) based control.

Preferably, when it is determined that the data transition is present in the adjacent channel between the determining step and the calculating step, the first signal is compared with the first timing signal when there is no potential difference, 2 timing signal; And determining the polarity of the second timing signal, wherein the calculating step calculates the gain of the first signal based on the polarity of the second signal and the polarity of the second timing signal.

Preferably, when the first signal is divided into the first timing signal and the second timing signal between the dividing step and the polarity determination step, the first timing signal and the second timing signal are Sampling; And delaying the first timing signal sampled and the second timing signal sampled using different clock cycles, respectively, wherein the step of determining the polarity includes the steps of: And calculates a gain of the first signal based on the first timing signal and the second timing signal.

Preferably, between the sampling step and the delaying step, the sampled first timing signal and the sampled second timing signal are converted from a differential CML digital signal into a single-ended CMOS digital signal Wherein the delaying step includes delaying the second timing signal by using a latch for delaying a half clock cycle and a D flip flop for delaying a clock cycle, And the first timing signal is delayed using flip-flops.

Preferably, the calculating step calculates a gain of the first signal based on signals obtained by integrating the first timing signal and the second timing signal.

Advantageously, the calculating step comprises calculating a gain of the first signal based on a current of a charge pump, an integration capacitance, an AGC (Automatic Gain Control) gain and a predetermined necessary factor, .

Preferably, the noise cancellation method is performed when the data is transmitted by wire using the channels arranged in parallel.

The present invention can achieve the following effects through the above-described configurations.

First, the crosstalk noise can be effectively removed by processing the corresponding channel signal using a gain obtained based on a value obtained by differentiating the adjacent channel signal and an edge component of the corresponding channel signal From which data reliability can be improved.

Secondly, the crosstalk noise can be effectively removed regardless of the spacing between the channels.

1 and 2 are reference diagrams illustrating eye degradation, which is simulated based on channel spacing deviation and shows various crosstalk strengths.
FIGS. 3 to 5 are reference diagrams for explaining the influence of positive crosstalk and negative crosstalk on the data transition of a forward signal.
6 is a schematic diagram of an adaptive XTC system in accordance with an embodiment of the present invention.
7 is a reference diagram for explaining a signal input from the mutual elimination to the comparator 1 or the comparator 2 in the adaptive XTC system.
FIG. 8 is a conceptual diagram schematically showing an internal configuration of a comparison unit constituting the adaptive XTC system.
Figure 9 is a table diagram illustrating the combinatorial logic needed to update the XTC gain on channel 1;
10 is a detailed view of an adaptive XTC system according to an embodiment of the present invention.
Fig. 11 is a reference diagram for explaining the signal at the portion A in Fig.
12 and 13 are reference diagrams for explaining experimental results of the control voltage for the XTC gain.
14 is a reference diagram for explaining rate control using a high-speed XTC adder.
15 and 16 are reference diagrams for explaining simulation results of the XTC adder.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to designate the same or similar components throughout the drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the preferred embodiments of the present invention will be described below, but it is needless to say that the technical idea of the present invention is not limited thereto and can be variously modified by those skilled in the art.

The fast input and output channels can be filtered by tap weights in a Decision Feedback Equalization (DFE) block to compensate for inter-symbol interference (ISI) and crosstalk caused by multiple adjacent channels. There is a need for adaptive techniques that optimize the settings to be used. Both inter-symbol interference and crosstalk tend to vary depending on channel length, process, temperature distribution, and so on. However, individually optimizing the above parameters may lead to a lane solution.

The present invention proposes an optimization technique for implementing XTC (Crosstalk Cancellation) in a DFE block (DFE block) to compensate both inter-symbol interference and crosstalk in high-speed input / output channels. The technique proposed in the present invention can be used to compensate for channel loss due to different crosstalk intensities when data is transmitted using, for example, a non-return-to-zero (NRZ) signal.

In multi-channel environments, high-speed performance depends on the adaptive calibration algorithm used in XTC.

The present invention proposes an algorithm in which high-speed XTC signaling techniques for single-end I / Os are developed with the adaptive correction algorithm.

The crosstalk signal generated between the multiple wire channels formed on the PCB is greatly influenced by the channel spacing between the different wire channels. Inter-symbol interference or crosstalk tends to vary between different wired channels due to changes in the PCB manufacturing process (changes that are made because the PCB is fabricated in different configurations for different parts assemblers) Therefore, an adaptive algorithm is needed.

The present invention proposes an adaptive XTC algorithm that works together with the DFE block to cope with the above-mentioned problems (changes that may occur in the PCB manufacturing process). In the above, the DFE block is for reducing inter-symbol interference.

The low power XTC architecture can achieve high signal integrity in harsh crosstalk environments. The present invention adopts an adaptive solution that uses power efficiently based on a predetermined scheme (Scheme) in the adaptive XTC algorithm in consideration of this point, and the adaptive solution itself also has a low power Mode.

Adaptive algorithms have been actively studied to find ways to optimally compensate for channel loss in a single data transmission channel. However, due to the slow pace of development of low power XTC architecture, the adaptive XTC algorithm remains an unknown subject. In addition, integrating adaptive XTC into existing DFEs remains an open issue.

The present invention proposes a new adaptive XTC algorithm to find a global optimal eye-opening. The adaptive XTC algorithm proposed in the present invention can achieve the best bit error rate performance by combining XTC and DFE.

The key to integrating the XTC with traditional ISI equalization techniques is that the maximum crosstalk amplitude is proportional to the maximum forward signal at which the data is sampled, And the fact that it occurs. At this time, the received signal, that is, the signal separated by the unit interval (UI) (unit interval) from the cursor timing, is used to adjust the coefficient of the XTC algorithm.

Generally, the maximum crosstalk generated between the Integer-UI Sampling points of the forward signal and the adaptive DFE associated with the independent operation of the XTC is feasible.

A system for achieving the above object with reference to the drawings is a system for data interference noise generated during parallel transmission of a high speed I / O integrated circuit using a parallel channel (multi-lane parallel) Type Adaptive analog crosstalk canceller will be described in detail.

- Understanding crosstalk behavior.

This section provides the results of analyzing the action of the crosstalk and also the results of analyzing the adaptive XTC algorithm proposed in the present invention.

The crosstalk strength is a strong function of the channel spacing. Figures 1 and 2 illustrate a simulated eye degradation based on various interchannel spacing.

FIG. 1 (a) is an example of a case where a channel-to-channel spacing is large (Larger channel spacing) and an inter-channel spacing is 480 mils. 1 (a) shows how a crosstalk 120 is generated by a signal transmitted to a second channel when a forward signal 110 is transmitted to a first channel. At this time, the signal output to the first channel has a form in which the forward signal 115 and the crosstalk signal 125 are combined as shown on the right side.

The signal output to the first channel in FIG. 1 (a) is the same as the Slight eye degradation shown in FIG. 2 (a).

FIG. 1 (b) is an example of a case where the interchannel spacing is medium (medium channel spacing), and an interchannel spacing is 240 mil. 1B shows a state where a crosstalk 120 is generated by a signal transmitted to a second channel when a forward signal 110 is transmitted to the first channel. At this time, the signal output to the first channel has a form in which the forward signal 115 and the crosstalk signal 125 are combined as shown on the right side.

The signal output to the first channel in FIG. 1 (b) is the same as the medium eye degradation shown in FIG. 2 (b).

FIG. 1C is an example of a case in which the interchannel spacing is small (smaller channel spacing), and an interchannel spacing is 120 mil. 1C shows a state where a crosstalk 120 is generated by a signal transmitted to a second channel when a forward signal 110 is transmitted to the first channel. At this time, the signal output to the first channel has a form in which the forward signal 115 and the crosstalk signal 125 are combined as shown on the right side.

The signal output to the first channel in FIG. 1 (c) is the same as Severe eye degradation shown in FIG. 2 (c).

As described above, FIGS. 1 and 2 are diagrams illustrating eye degradation, which is simulated based on channel spacing deviation and shows various crosstalk strengths.

When the inter-channel spacing is very narrow, the eye is completely closed as shown in Fig. 2 (c). The maximum amplitude of the crosstalk signal occurs at the timing of data transition in the adjacent channel. The detection of the maximum amplitude of the crosstalk signal and the maximum amplitude of the data signal can be achieved independently, and the adaptive loops of the XTC and DFE can be operated separately.

FIGS. 3 to 5 are reference diagrams for explaining the influence of positive crosstalk and negative crosstalk on the data transition of a forward signal. The following description refers to Figs. 3 to 5. Fig.

FIGS. 3 to 5 illustrate an eye diagram of a non-return-to-zero signal having crosstalk and a zoom-in version of a data transition timing. A zoom-in version of the data transition timing is as shown in FIG. In FIG. 4, reference numerals 140a and 140b indicate positive crosstalk, and reference numerals 150a and 150b indicate negative crosstalk. The point at which the two positive crosstalks 140a and 140b and the two negative crosstalks 150a and 150b meet corresponds to the sampling timing.

There are two types of crosstalk associated with data transitions. One of them is a positive crosstalk, and the other is a negative crosstalk.

If a data slicer is placed in the middle of a transition, the resulting digital values will have a positive impact due to crosstalk depending on the type of data transition of the adjacent forward signal Positive impact or Negative impact. In the above, the data slicer is triggered by the recovered clock.

The logical relationships that result in either a positive crosstalk impact and a negative crosstalk impact are as shown in the RHS table of FIG. 5 shows a change in the forward signal transition due to crosstalk from the adjacent channel.

3 (a) shows a case where a forward signal 110 is transited from 0 to 1 and an adjacent forward signal 130 is transited from 0 to 1. In Case 1, And the crosstalk 120 generated in the forward signal 110 due to the influence of the forward signal 130 is shown. The crosstalk 120 at this time is a negative crosstalk as shown in the upper left corner of Fig.

3B shows a case where the forward signal 110 is transited to [1 → 0] and the adjacent forward signal 130 transitions from [0 → 1] (Case 2) The crosstalk 120 generated in the forward signal 110 is shown. The crosstalk 120 at this time is negative crosstalk as shown in the right upper end of Fig.

3C shows the effect of the adjacent forward signal 130 when the forward signal 110 transitions from 0 to 1 and the forward forward signal 130 transitions from 1 to 0 The crosstalk 120 generated in the forward signal 110 is shown. The crosstalk 120 at this time is a positive crosstalk as shown in the lower left part of Fig.

3 (d) shows a case where the forward signal 110 is transited from [1 → 0] and the adjacent forward signal 130 transitions from [1 → 0] (Case 4) The crosstalk 120 generated in the forward signal 110 is shown. The crosstalk 120 at this time is a positive crosstalk as shown in the lower right part of Fig.

3 to 5, it can be seen that the polarity of the crosstalk impact depends only on the type of data transition from the adjacent channel, irrespective of the type of data transition of the forward signal.

- Adaptive XTC (Adaptive XTC)

In this section, the basic concept of the XTC algorithm, which has been proposed in the present invention and has been verified through simulation, will be described, and an appropriate expansion concept will also be described.

6 is a schematic diagram of an adaptive XTC system in accordance with an embodiment of the present invention. FIG. 6 shows a case in which there is one adjacent channel. In the present invention, it is also possible to have two or more adjacent channels.

As shown in FIG. 6, the adaptive XTC system 200 includes a first differential converter 213, a second differential converter 223, a mutual adder 230, A comparator 1 241, a logic processor and integrator 1 242, a comparator 2 251 and a logic processor and integrator 2 252.

The first differential converter 213 performs a function of converting the signal received from the input terminal 211 of the channel 1 receiver into a differential signal.

The signal input to the first differential converter 213 is the high-speed data signal transmitted from the channel 1 transmitter and the noise interfered from the channel 2 (single-ended). Referring to the graph on the right side of the first differential converter 213, a graph located on the upper side with respect to + indicates a channel 1 data signal, and a graph located on the lower side indicates an interference noise signal coming from channel 2.

The signal output from the first differential converter 213 is a differential signal obtained by converting an input signal (Single-ended) into a differential signal.

Meanwhile, the resistor 212 positioned between the input terminal 211 of the channel 1 receiving unit and the first differential converter 213 may be implemented with 50?.

The second differential converter 223 performs a function of converting the signal received from the input terminal 221 of the channel 2 receiver to a differential signal.

The signal input to the second differential converter 223 is a single-ended signal interfering with the high-speed data signal transmitted from the channel 2 transmitter and the channel 1. [ Referring to the graph on the right side of the second differential converter 223, a graph located on the upper side of + indicates a channel 2 data signal, and a graph located on the lower side indicates an interference noise signal coming from channel 1.

The signal output from the second differential converter 223 is a differential signal obtained by converting an input signal (Single-ended) into a differential signal.

Meanwhile, the resistor 222 located between the input terminal 221 of the channel 2 receiver and the second differential converter 223 may be implemented with 50?.

The signals input to the mutual removal unit 230 are the input signal 1 and the input signal 2. The input signal 1 is a signal (differential) in which the data signal of channel 1 is combined with the noise signal of channel 2, and the input signal 2 is a signal obtained by combining the data signal of channel 2 and the noise signal of channel 1.

The mutual elimination unit 230 generates a channel 2 interference noise canceling signal by differentiating the channel 2 data signal and adds the channel 2 interference noise canceling signal to the channel 1 (differential function) when channel 1 is a target channel and channel 2 is an adjacent channel of a target channel . The mutual elimination unit 230 performs a function of differentiating the channel 1 data signal to generate a channel 1 interference noise canceling signal and adding it to the channel 2 when the channel 2 is the target channel and the channel 1 is the adjacent channel of the target channel do.

The signals output by the mutual removal unit 230 are the output signal 1 and the output signal 2. Output signal 1 is a signal in which only the data signal of channel 1 is left and the noise signal of channel 2 is removed (differential). Output signal 2 is a signal in which only the data signal of channel 2 is left and the noise signal of channel 1 is removed.

The comparator 1 (241) receives the differential data signal (Differential) from which the interference noise is removed.

The comparator 1 241 detects the sign of the residual signal of the interference signal to be eliminated in the mutual elimination 230 (present at the edge timing) and transmits the signal to the logic processing and integrator 1 242 . At this time, the comparator 1 241 also transmits data information (center timing).

The comparator 1 241 outputs the sampled data at the center timing of the data eye diagram (Eye diagram) and the sampled data (single-ended) at the edge timing.

The logic processing and integration unit 1 242 receives a signal obtained by aligning a digital signal that senses the sign of the residual interference signal remaining at the edge timing and a signal obtained by sampling the data.

Logic processing and integration 1 242 performs the function of adjusting the noise removal strength as a result of integration.

The logic processing and integration unit 1 242 performs a function of outputting a digital signal for setting a direction for adjusting the noise cancellation signal intensity using the correlation between the residual signal of the interference signal and the data signal, .

The comparator 2 251 performs the same function as the comparator 1 241 and the logic processor and integrator 2 252 performs the same function as the logic processor and integrator 1 251.

7 is a reference diagram for explaining a signal input from the mutual elimination to the comparator 1 or the comparator 2 in the adaptive XTC system.

A signal input from the mutual removal unit 230 to the comparator 1 241 or the comparator 2 251 in the adaptive XTC system 200 may be represented by an eye diagram as shown in FIG. In the input signal, reference numeral 310 denotes data center timing, and reference numerals 320a and 320b denote data edge timing.

FIG. 8 is a conceptual diagram schematically showing an internal configuration of a comparison unit constituting the adaptive XTC system. Hereinafter, the comparator 1 (241) will be described as an example, but it is needless to say that the comparator 2 (251) has the same internal configuration as the comparator 1 (241).

8, the comparator 1 241 includes an edge slicer 411, a first CML to CMOS 412, a latch 413, a first D flip flop 414, a data slicer ; A second CML to CMOS 422; a second D flip flop 423; and a third D flip flop 424.

The edge slicer 411 performs a function of sampling 0 or 1 at the edge timing of the CML digital signal from the mutual remover 230.

The first CML to CMOS 412 functions to convert a differential CML digital signal into a single-ended CMOS digital signal.

The latch 413 performs a function of delaying the edge digital data by a half clock cycle.

The first D flip-flop 414 performs a function of delaying the data by one clock cycle.

The data slicer 421 performs a function of sampling 0 or 1 at the data center timing of the CML digital signal from the mutual remover 230.

The second CML to CMOS 422 functions to convert a differential CML digital signal into a single-ended CMOS digital signal.

The second D flip-flop 423 performs a function of delaying the center digital data by one clock cycle.

The third D flip-flop 424 performs a function of delaying the data by one clock cycle.

The comparator 1 241 compares the edge data (x ₁ [t _0.5 ]) of the channel 1 IP and the aligned center of the channel 1 IP through the first D flip-flop 414 and the third D flip- And transfers data (x ₁ [t ₁ ], x ₁ [t ₀ ]) to the logic processing and integration section 1 242.

Meanwhile, the comparison unit 2 251 compares the aligned edge data (x ₂ [t _0.5 ]) of the channel 2 IP and the aligned center data (x ₂ [t ₁ ]) of the channel 2 IP in the same manner as the comparison unit _{1 ], x 2 [t 0]} ) to be sent to the logic processing and a second integration section 252.

On the other hand, the logic processing and integration unit 1 242 may be configured as a channel 1 IP logic processing unit 1 and a channel 1 IP integration unit 1.

The channel 1 IP logic processing unit 1 is combinational logic, and the logic of the UP signal and the logic of the DN signal are as shown in FIG. Figure 9 is a table diagram illustrating the combinatorial logic needed to update the XTC gain on channel 1;

In FIG. 9, the sign between x ₁ [t ₀ ] and x ₁ [t ₁ ] means XOR. In Fig. 9, the following equation (1) holds.

The channel 1 IP integrating unit 1 integrates the UP and DN digital signals from the channel 1 IP logic processing unit 1 to generate an analog signal that determines whether the interference noise canceling signal is increased or decreased by integrating the two digital signals .

The adaptive XTC system has been schematically described with reference to FIGS. 6 to 9. FIG. Hereinafter, the adaptive XTC system will be described in more detail in one embodiment.

10 is a detailed view of an adaptive XTC system according to an embodiment of the present invention. And Fig. 11 is a reference diagram for explaining the signal at A portion in Fig.

FIG. 10 shows a system for implementing the adaptive XTC algorithm proposed by the present invention. The adaptive XTC algorithm at this time uses a logical relationship between the kind of data transition and the polarity of the resultant crosstalk .

The data slicer triggered by the recovered clock performs the function of determining the equalized signal. An edge slicer samples the data signal at transition timing, while at the same time the edge slicer detects whether a particular crosstalk is likely to produce a positive impact or a negative impact. The detected digital signals are used to provide an adaptive XTC loop.

CML-to-CMOS circuits convert differential signals, the output of the slicer, into digital signals. A combinational logic block generates UP pulses or DN pulses depending on the type of crosstalk (i.e. whether the crosstalk is positive crosstalk or negative crosstalk). The integrator updates the XTC gain by incorporating UP pulses or DN pulses. Digital delay blocks and combinational logic blocks are similar to phase detectors in a clock recovery block and can be shared to conserve power.

Since the ISI equalizer can not remove crosstalk, it causes timing jitter. DFE can mitigate the ISI that occurs without increasing crosstalk noise. However, certain jitter through crosstalk remains unaffected and reduces the horizontal eye margin.

Assuming that the recovered 0 ° clock provides rising-edge timing at the center of the data eye for the differential data slicer, the differential edge slicer ) Is triggered by a 180 ° clock and samples of the digital signal are generated at the data edge, x ₁ [t _0.5 ].

If the detected differential data signal is greater than 0 (crossing point) at any time during a period of the rising edge of the 180 ° clock, the differential data signal is positive This implies a positive crosstalk impact, and then the edge slicer and CML-to-CMOS blocks will have a value of one. The opposite is true.

Receiving a holding x ₁ [t _0.5] including 1/2 UI, and according to the digital delay blocks _{(Digital delay block), x 1} [t 0] all, x ₁ [t _0.5] and ₁ x [t _1] is compensated XTC (Combinational Logic Block) to determine whether the XTC compensation is over or under.

By using x ₁ [t ₀ ] and x ₁ [t ₁ ] from channel ₁ and using x ₂ [t ₀ ] and x ₂ [t ₁ ] from channel 2, It can be predicted that the data transitions may include either positive crosstalk or negative crosstalk.

If the detected digital signals x ₁ [t _0.5 ] and x ₂ [t _0.5 ] are the same as the predicted digital signal, then the XTC algorithm will not operate normally and then the combinational logic block will increase the specific XTC signal gain To generate the UP signal. The opposite is true.

Based on the above-described preceding logical hypothesis and the table in FIG. 5, a table of FIG. 9 is generated. Through an adaptive XTC loop, the edge samples are forced to have a zero mean.

The configurations shown in FIG. 10 have been described above with reference to FIG. 6 and FIG. 8. However, the detailed description of configurations that perform the same functions will be omitted here.

The first logic processing unit 451 and the first integrating unit 453 correspond to the channel 1 IP logic processing unit 1 and the channel 1 IP integrating unit 1 described above with reference to FIG. The second logic processing unit 452 and the second integrating unit 454 operate on the channel 2 signal and have the same functions as the first logic processing unit 451 and the first integrating unit 453, .

The digital delay 440 is a concept including a latch 413, D flip-flops 414, 423 and 424 for delaying a center timing signal and an edge timing signal, respectively.

The differential signal obtaining unit 431 constitutes a mutual elimination unit 230 and performs a function of obtaining a differential signal in which a data signal of channel 1 and a noise signal of channel 2 are combined. The differential signal obtaining unit 431 also obtains a differential signal in which the data signal of the channel 2 and the noise signal of the channel 1 are combined.

The AGC 432 constitutes a mutual remover 230 as in the differential signal obtaining unit 431 and is for adaptive equalization and performs an automatic gain control function.

On the other hand, FIG. 11 shows signals after ISI equalization in part A of FIG. Each reference numeral in Fig. 11 can be defined as follows.

330: Slicer sampling timing

341: Horizontal eye margin

342: Timing jitter

343: Center Digital data (Data center)

344: Edge digital data (Data edge)

351: 0 ° Clock (Clock)

352: 180 ° Clock

353: Rising edge

12 and 13 are reference diagrams for explaining experimental results of the control voltage for the XTC gain. FIG. 12 shows an internal circuit of an integrator or charge pump, and FIG. 13 is a graph showing control voltage converging (V _CONT ). The following description refers to Fig. 12 and Fig.

Hereinafter, a low-frequency feedback loop for the adaptive XTC will be described.

Detection blocks and combinational logic blocks generate UP pulses or DN pulses, which are supplied to a charge pump to update the control voltage for the XTC gain (XTC gain) Lt; / RTI >

The loop gain in the frequency domain can be expressed by the following equation.

Loop gain = 0.25 x (AIs / sC)

In the above, Is means the current value of the charge pump. C means integration capacitance. A means AGC gain. In the present invention, A may be set to a unit gain for convenience. 0.25 is a Necessary Factor, taking into account the fact that data transitions occur simultaneously with a 1/4 probability on both sides of channel 1 and channel 2.

Actually, the necessary coefficients depend on the patterns of channel 1 and channel 2. Because there is a single pole at zero frequency in the overall feedback-loop transfer function, the loop is stable with a pulse margin of less than 90.

The loop gain described above can be implemented and obtained by AGC, DFE Summer & Detectors, slicers, DFF & Combinational logic, an integrator, or charge pump, .

The update step voltage (V) in V _CONT for each symbol period is AIsTb / C. 1 (c), the simulation of the adaptive XTC algorithm proposed by the present invention will be described. For a 12 Gb / s application, set Tb to 83.3 ps. The other parameters are set as follows.

A = 1

Is = 50 μA

C = 1 pF

The difference in the control voltage from the initial value to the optimal converging value is 757 mV. Based on this setting, the theoretical converging time of the loop can be calculated as follows.

Convergence time = (757 mV x Tb) / (0.25 x? V) = 60.1 ns

Compared to the simulation value of 62 ns, it shows a 3.2% error due to the randomness of the data pattern. By increasing the current of the charge pump or decreasing the size of the capacitor, the updating voltage step can be increased to reduce the converging time.

However, due to the large step size, the large static state noise of the control voltage directly translates to more residual crosstalk noise after the XTC. This fact is clearly shown in FIGS. 12 and 13. FIG.

In practice this would be the expected channel spacing and the initial XTC gain for each PCB channel product.

14 is a reference diagram for explaining rate control using a high-speed XTC adder.

Top figure (Top) in Fig. 14 is a current-based g _m control circuit (Current-based g _m control circuit) a will in the figure, the lower Figure (Bottom) is a DAC based binary g _m control circuit (DAC-based binary g _m control circuit. 14, a signal input to the V _{I +} terminal and the V _{I -} terminal is a signal obtained by combining a forward signal and a crosstalk signal, and a signal input to the V _{F +} terminal and the V _{F -} terminal And a crosstalk cancellation signal. The signals output to the V _{O +} and V _{O -} terminals are forward signals.

Meanwhile, x1, x2 and x4 in the lower diagram in Fig. 14 mean the width of the MOSFET to be actually designed. For example, 1 탆 x 1, 1 탆 x 2, 1 탆 x 4, etc. If the picture becomes concrete, it is difficult to read intuitively. For convenience, it is displayed as x1, x2, x4 and the like.

15 and 16 are reference diagrams for explaining simulation results of the XTC adder.

Figures 15 and 16 show the simulation results of the XTC adder for different crosstalk levels, Impact at eye openings, and final V _CONT value.

The following description refers to Fig. 14 to Fig.

Figure 14 shows a high-speed signal adder circuit. 15 and 16 show simulation results of an adaptive XTC for various crosstalk strengths inversely proportional to channel spacings.

In FIG. 14, the upper RHS circuit (Circuit on the top RHS) shows an implementation of an adder block with an analogue control function. The ratio of the DC current in the forward path amplifier and the XTC path amplifier is controllable. The transconductance of the two paths share a common load, and the addition gain can be varied according to the gm ratio.

If the DC current at the load has a constant value regardless of the current ratio (i. E., As well as the gain), the DC values at the output nodes are determined such that the AC coupling capacitors are avoided at the next stage It is kept constant to be able to.

14, this block can be implemented using DAC-based current source switching. This circuit shows a 3-bit control, but it can be easily extended for high resolution control.

V _CONT is in the range of 0V to 1V, and the overall gain of the adder G is set to four values as a result of the simulation. When V _CONT is increased, a relatively larger XTC signal is added while the forward signal including the crosstalk signal thereafter decreases. In order to cope with various input signal levels, the adder with the gain control block precedes the XTC block and the DFE block.

15 shows the eye convergence of the XTC adder output. Referring to FIG. 15A, the left-hand diagram 511 shows an injected FEXT (injected FEXT) at a starting adaptation time of 198 mV _{p- p} . The central figure 512 represents the Eye of 26.2 ns in the situation during adaptation. The right side view 513 shows the eye of 52.4 ns after the convergence.

Referring to FIG. 15B, the left diagram 521 shows the injected FEXT (Injected FEXT) at the starting adaptation time: 2 x 198 mV _{p - p} . The central view 522 represents the Eye of 31 ns in a situation during adaptation (During adaptation). The right diagram 523 shows an eye of 62 ns at a time after convergence (After convergence).

Referring to FIG. 15C, the left-hand view 531 shows the injected FEXT (Injected FEXT) at the start of adaptation (starting adaptation): 3 × 198 mV _{p- p} . The central view 532 represents the Eye of 32.5 ns during the adaptation during adaptation. The right side view 533 shows an eye of 65 ns at a time after convergence (After convergence).

Figure 16 illustrates VCONT voltage adaptation. Converging values in (a) to (c) of FIG. 16 are respectively as follows.

16 (a): a = 0.616, a / (1-a) = 1.6

The convergence value in Fig. 16 (b): a = 0.757, a / (1-a) = 3.1

The convergence value in FIG. 16 (c): a = 0.831, a / (1-a) = 4.9

As shown in the simulation results shown in Figs. 15 and 16, V _CONT converges to a large value for large crosstalk values. It only takes a little longer to get to it as described above. The long settling times for large crosstalk values are due to a constant slope of settling.

This section does not take into account the MIMO signal in the analysis of the adaptive XTC loop. In fact, the MIMO signal does not affect the determination of the edge slicer. This is because the MIMO signal is a derivative of the crosstalk signal.

The theoretical MIMO signal value for the maximum crosstalk amplitude when the edge slicer determines the positive crosstalk impact or the negative crosstalk impact during the data transition is zero (Zero). As a result, the determination of the edge slicer is not affected.

While the large crosstalk strengths are maintained, the gains of the forward signals after the XTC adaptation tend to become smaller as shown in Figs. 15 and 16. The AGC block can adjust these various forward signal strengths with a constant signal amplitude.

Integration of both the adaptive XTC (Adaptive XTC) and the adaptive DFE (Adaptive DFE) is omitted herein.

The present invention described above is summarized as follows.

The present invention provides a new IP structure that automatically adjusts the interference cancellation intensity in an architecture that eliminates interference noise analogously in a PCB I / O channel environment that transmits high-speed data on a parallel channel.

In the wire-parallel transmission between the chip and the chip, interference noise occurs in the forward direction between adjacent PCB channels, which is referred to as crosstalk. Since the adjacent channel data patterns are independent of each other in the crosstalk, the interfered signals operate as noise.

Crosstalk noise is a deterministic noise that occurs with certain rules according to the state of data transition of the original channel (the channel that has the signal that becomes the source of noise) before interference. In a parallel channel, crosstalk noise interferes with the transition timing of data when it is coupled to a nearby channel. The narrower the spacing between parallel channels, the stronger the interference and the stronger the crosstalk noise.

A way to eliminate crosstalk is to differentiate the original signal analogously and subtract the current interference noise to the appropriate gain for the interleaved signal.

However, since the spacing between parallel PCB channels varies among different PCB component manufacturers, it is unclear to what degree the interference noise is added.

It is a matter of the present invention to automatically update the gain of the eliminator according to the type of polarity appearing in the data transition of the neighboring channel of the interference noise to remove the noise with the most appropriate intensity irrespective of the channel interval, , The new idea is to introduce an automatic adaptive cancellation method to the analog interference cancellation structure unlike the existing digital automatic cancellation method.

FIGS. 10 and 11 illustrate an overall noise canceller architecture including digital logic that updates the interference cancellation intensity by measuring the polarity of the aforementioned noise in real time.

15 and 16 show the result that the noise canceling intensity is automatically converged according to various kinds of interference noise intensities.

FIG. 14 shows an implementation of a circuit for analogically adjusting the intensity of an interference noise cancellation signal.

According to the present invention, it is possible to make the parallel high-speed data transmission signal cleaner, thereby technically leading to the effect of further increasing the transmission speed or reducing power consumption. The present invention provides a degree of freedom in the design requirements of the design of the PCB channel spacing due to the spacing between the channels, and it will be an opportunity to add significant added value in terms of IP.

The present invention can be applied to all products that perform high-speed data transmission by using a parallel channel such as LPDDR4, an application processor, and a memory device.

1 to 16, an embodiment of the present invention has been described. Best Mode for Carrying Out the Invention Hereinafter, preferred forms of the present invention that can be inferred from the above embodiment will be described.

The apparatus for removing noise of a data signal according to a preferred embodiment of the present invention includes a data transition determining unit, a signal gain calculating unit, and a noise removing unit.

When data is transmitted using at least two channels, the data transition determination unit determines whether there is a data transition in an adjacent channel adjacent to a specific channel selected from at least two channels.

The data transition determination unit may determine whether there is a data transition based on whether or not there is a potential difference with respect to the second signal for transmitting data in the adjacent channel.

If it is determined that there is a potential difference with respect to the second signal, the data transition determining unit determines that there is a data transition in the adjacent channel. On the other hand, if it is determined that there is no potential difference with respect to the second signal, the data transition determining unit determines that there is no data transition in the adjacent channel.

If the data transition determining unit determines that there is a data transition in the adjacent channel, the signal gain calculating unit calculates the gain of the first signal that transmits data in a specific channel based on the polarity of the second signal related to the data transition .

The signal gain calculating unit may calculate the gain of the first signal based on the signals obtained by integrating the first timing signal and the second timing signal.

The signal gain calculator may calculate the gain of the first signal based on a current of a charge pump, an integration capacitance, an AGC (Automatic Gain Control) gain, and a predetermined necessary factor.

The noise removing unit performs a function of finally removing noise from the first signal based on the gain of the first signal.

The apparatus for removing noise of a data signal may further include a first differential converter and a differential signal processor.

The first differential converter converts a signal input to a specific channel to a first differential signal. A signal input to a specific channel is a signal obtained by combining a data signal of a specific channel (eg, channel 1) and a noise signal of an adjacent channel (eg, channel 2).

The differential signal processing unit performs a function of first removing noise from the first differential signal using a signal input to the adjacent channel. The signal input to the adjacent channel in the above is the data signal of the adjacent channel (e.g., channel 2). The differential signal processing unit is a concept corresponding to mutual elimination.

The differential signal processing unit may remove the noise first by adding a signal obtained by differentiating the signal input to the adjacent channel to the first differential signal.

The differential signal processing unit can remove noise primarily by using an adder based on current-based control or DAC (Digital Analog Converting) -based control.

When the noise canceller of the data signal further includes the first differential converter and the differential signal processor, the signal gain calculator may use the first differential signal from which the noise is first removed as the first signal.

The apparatus for removing noise of a data signal may further include a signal division unit and a signal polarity determination unit.

The signal dividing unit divides the first signal into a first timing signal when there is no potential difference and a second timing signal when there is a potential difference when it is determined that there is a data transition in the adjacent channel. At this time, the signal dividing unit may use the first differential signal whose noise is firstly removed by the differential signal processing unit as the first signal. The first timing signal when there is no potential difference is a concept corresponding to the data center timing, and the second timing signal when there is a potential difference corresponds to the data edge timing.

The signal polarity determination unit performs a function of determining the polarity of the second timing signal.

When the noise canceling device of the data signal further includes the signal dividing section and the signal polarity judging section, the signal gain calculating section may calculate the gain of the first signal based on the polarity of the second signal and the polarity of the second timing signal.

The noise canceller of the data signal may further include a sampling unit and a delay unit.

The sampling unit performs sampling of the first timing signal and the second timing signal, respectively, when the first signal is divided into the first timing signal and the second timing signal.

The delay unit delays the first timing signal sampled and the second timing signal sampled using different clock cycles.

When the noise canceling apparatus of the data signal further includes a sampling unit and a delay unit, the signal polarity determination unit calculates the gain of the first signal based on the first timing signal and the second timing signal delayed by using different clock cycles .

The signal division unit, the sampling unit, the delay unit, and the signal polarity determination unit are concepts corresponding to the comparison unit.

The noise canceller of the data signal may further include a digital signal converter.

The digital signal converting unit converts the sampled first timing signal and the sampled second timing signal into a single-ended CMOS digital signal from a differential CML digital signal.

In this case, the delay unit performs a function of delaying the second timing signal by using a latch for delaying a half clock cycle and a D flip-flop for delaying one clock cycle. The delay unit also performs a function of delaying the first timing signal by using two D flip flops that delay one clock cycle.

The noise canceller described above can be used to transmit data to a wired line using channels arranged in parallel.

Next, an operation method of a device for removing noise of a data signal will be described.

First, when the data transition determining unit transmits data using at least two channels, it determines whether there is a data transition in a neighboring channel adjacent to a specific channel selected from at least two channels (Step A).

If it is determined that there is a data transition in the adjacent channel, the signal gain calculating unit calculates the gain of the first signal transmitting data in the specific channel based on the polarity of the second signal related to the data transition (Step B).

Thereafter, the noise removing unit removes noise from the first signal based on the gain of the first signal (Step C).

Between Step A and Step B, the first differential transformer converts a signal input to a specific channel into a first differential signal (Step A1). Thereafter, the differential signal processing unit first removes noise from the first differential signal using a signal input to the adjacent channel (Step A2). In this case, the signal gain calculator may use the first differential signal whose noise is removed first as a first signal.

On the other hand, if it is determined that there is a data transition in the adjacent channel between Step A and Step B (preferably between Step A2 and Step B), the signal division unit divides the first signal by the first timing signal in the absence of the potential difference, (Step A3). Then, the signal polarity determination unit determines the polarity of the second timing signal (Step A4). At this time, the signal gain calculating unit may calculate the gain of the first signal based on the polarity of the second signal and the polarity of the second timing signal.

Between Step A3 and Step A4, if the first signal is divided into the first timing signal and the second timing signal, the sampling unit samples the first timing signal and the second timing signal, respectively (Step A3a). Thereafter, the delay unit delays the first timing signal sampled and the sampled second timing signal using different clock cycles (Step A3b). At this time, the signal gain calculator may calculate the gain of the first signal based on the first timing signal and the second timing signal delayed by using different clock cycles.

Between Step A3a and Step A3b, the digital signal converter converts the sampled first timing signal and the sampled second timing signal from the differential CML digital signal into a single-ended CMOS digital signal. At this time, the delay unit delays the second timing signal by using a latch which delays a half clock cycle and a D flip flop which delays by one clock cycle, and by using two D flip flops which delay one clock cycle, Can be delayed.

It is to be understood that the present invention is not limited to these embodiments, and all elements constituting the embodiment of the present invention described above are described as being combined or operated in one operation. That is, within the scope of the present invention, all of the components may be selectively coupled to one or more of them. In addition, although all of the components may be implemented as one independent hardware, some or all of the components may be selectively combined to perform a part or all of the functions in one or a plurality of hardware. As shown in FIG. In addition, such a computer program may be stored in a computer readable medium such as a USB memory, a CD disk, a flash memory, etc., and read and executed by a computer to implement an embodiment of the present invention. As the recording medium of the computer program, a magnetic recording medium, an optical recording medium, a carrier wave medium, and the like can be included.

Furthermore, all terms including technical or scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined in the Detailed Description. Commonly used terms, such as predefined terms, should be interpreted to be consistent with the contextual meanings of the related art, and are not to be construed as ideal or overly formal, unless expressly defined to the contrary.

It will be apparent to those skilled in the art that various modifications, substitutions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. will be. Therefore, the embodiments disclosed in the present invention and the accompanying drawings are intended to illustrate and not to limit the technical spirit of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments and the accompanying drawings . The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

Claims (22)

A data transition determiner for determining whether there is a data transition in an adjacent channel adjacent to a specific channel selected from the at least two channels when data is transmitted using at least two channels;
A first signal for transmitting data in the specific channel is divided into a first timing signal when there is no potential difference and a second timing signal when there is a potential difference, ;
A signal polarity determination unit for determining the polarity of the second timing signal;
A signal gain calculating unit for calculating a gain of the first signal based on a polarity of a second signal related to the data transition and a polarity of the second timing signal; And
And a noise eliminator for finally removing noise from the first signal based on the gain of the first signal,
And a noise canceler for removing noise of the data signal. The method according to claim 1,
Wherein the data transition determining unit determines whether or not there is a data transition based on whether there is a potential difference with respect to the second signal transmitting the data in the adjacent channel. The method according to claim 1,
A first differential converter for converting a signal input to the specific channel into a first differential signal; And
And a differential signal processor for first removing the noise from the first differential signal using a signal input to the adjacent channel,
Further comprising:
Wherein the signal gain calculating unit uses the first differential signal whose noise is removed first as the first signal. The method of claim 3,
Wherein the differential signal processor removes the noise by adding the signal obtained by differentiating the signal input to the adjacent channel to the first differential signal. The method of claim 3,
Wherein the differential signal processor removes the noise by using an adder based on current-based control or DAC (Digital Analog Converting) -based control. delete The method according to claim 1,
A sampling unit for sampling the first timing signal and the second timing signal, respectively, when the first signal is divided into the first timing signal and the second timing signal; And
A delay unit for delaying the first timing signal sampled using different clock cycles and the sampled second timing signal,
Further comprising:
Wherein the signal polarity determination unit calculates the gain of the first signal based on the first timing signal and the second timing signal delayed by using different clock cycles, respectively. 8. The method of claim 7,
A digital signal conversion unit for converting the sampled first timing signal and the sampled second timing signal from a differential CML digital signal into a single-ended CMOS digital signal;
Further comprising:
The delay unit may delay the second timing signal by using a latch that delays a half clock cycle and a D flip-flop that delays a clock cycle, and by using two D flip-flops that delay one clock cycle, And the timing signal is delayed. The method according to claim 1,
Wherein the signal gain calculating unit calculates a gain of the first signal based on signals obtained by integrating the first timing signal and the second timing signal. The method according to claim 1,
The signal gain calculating unit may calculate the gain of the first signal based on a current of a charge pump, an integration capacitance, an AGC (Automatic Gain Control) gain, and a predetermined necessary factor And a noise canceling device for the data signal. The method according to claim 1,
Wherein the noise canceller is used to transmit the data by wire using the channels arranged in parallel. Determining whether there is a data transition in an adjacent channel adjacent to a specific channel selected from the at least two channels when data is transmitted using at least two channels;
Dividing a first signal for transmitting data in the specific channel into a first timing signal when there is no potential difference and a second timing signal when there is a potential difference, when it is determined that the data transition is present in the adjacent channel;
Determining a polarity of the second timing signal;
Calculating a gain of the first signal based on a polarity of a second signal related to the data transition and a polarity of the second timing signal; And
And finally removing noise from the first signal based on the gain of the first signal
And removing the noise from the data signal. 13. The method of claim 12,
Wherein the determining step determines whether or not there is a data transition based on whether there is a potential difference with respect to the second signal transmitting the data in the adjacent channel. 13. The method of claim 12,
Converting a signal input to the specific channel into a first differential signal; And
Removing the noise from the first differential signal by using a signal input to the adjacent channel
Further comprising:
Wherein the calculating step uses the first differential signal whose noise is removed first as the first signal. 15. The method of claim 14,
Wherein the first removing step adds the signal obtained by differentiating the signal input to the adjacent channel to the first differential signal to remove the noise first. 15. The method of claim 14,
Wherein the first removing step removes the noise by using an adder based on current-based control or DAC (Digital Analog Converting) -based control. delete 13. The method of claim 12,
Sampling the first timing signal and the second timing signal, respectively, if the first signal is divided into the first timing signal and the second timing signal; And
Delaying the first timing signal sampled using the different clock cycles and the sampled second timing signal;
Further comprising:
Wherein the determining of the polarity comprises calculating a gain of the first signal based on the first timing signal and the second timing signal delayed by using different clock cycles, respectively. 19. The method of claim 18,
Converting the sampled first timing signal and the sampled second timing signal from a differential CML digital signal into a single-ended CMOS digital signal
Further comprising:
Wherein the delaying step comprises delaying the second timing signal by using a latch for delaying a 1/2 clock cycle and a D flip-flop for delaying a clock cycle, and using the two D flip-flops for delaying one clock cycle, And delaying the first timing signal. 13. The method of claim 12,
Wherein the calculating step calculates the gain of the first signal based on signals obtained by integrating the first timing signal and the second timing signal. 13. The method of claim 12,
The calculating step may include calculating a gain of the first signal based on a current of a charge pump, an integration capacitance, an AGC (Automatic Gain Control) gain, and a predetermined necessary factor Wherein the noise signal is a noise signal. 13. The method of claim 12,
Wherein the noise cancellation method is performed when the data is transmitted through a wired line using the channels arranged in parallel.

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