WO2019167275A1 - Decision feedback equalizer and receiver using same - Google Patents

Decision feedback equalizer and receiver using same Download PDF

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Publication number
WO2019167275A1
WO2019167275A1 PCT/JP2018/008129 JP2018008129W WO2019167275A1 WO 2019167275 A1 WO2019167275 A1 WO 2019167275A1 JP 2018008129 W JP2018008129 W JP 2018008129W WO 2019167275 A1 WO2019167275 A1 WO 2019167275A1
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output
signal
threshold
decision feedback
flop
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PCT/JP2018/008129
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French (fr)
Japanese (ja)
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崇泰 乗松
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株式会社日立製作所
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Priority to PCT/JP2018/008129 priority Critical patent/WO2019167275A1/en
Publication of WO2019167275A1 publication Critical patent/WO2019167275A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/06—Control of transmission; Equalising by the transmitted signal

Definitions

  • the present invention relates to a receiver for high-speed wired transmission and a semiconductor integrated circuit that can be used for the receiver, and more particularly to a technique for increasing error resistance with respect to circuit linearity.
  • the gain varies depending on the signal amplitude due to the influence of the linearity of the circuit. Therefore, the gain becomes small in a pattern in which the minimum voltage is changed to the maximum voltage. Furthermore, when a decision feedback equalizer is used, an error in the previous data affects the next data, resulting in a lack of equalization, and a burst error in which the next data also becomes an error occurs.
  • an object of the present invention is to reduce bit errors caused by circuit linearity and data patterns.
  • One aspect of the present invention includes a first adder that adds a correction value to an input signal, a determiner that determines the output of the first adder as a logical value according to a first determination threshold, and a determiner A flip-flop that samples and holds the output of the flip-flop at the clock timing, and has a shift register that receives the output of the flip-flop and the clock and delays the output of the flip-flop every clock cycle.
  • a multiplier that multiplies the output by a correction coefficient and outputs a correction value
  • a correction coefficient calculator that calculates a correction coefficient for each clock timing from the output of the first adder and the output of the flip-flop
  • a determination threshold calculator that calculates a second determination threshold for each clock timing from the output of the first adder and the output of the flip-flop
  • a decision feedback equalizer having a second adder for outputting a first determination threshold the threshold value offset added to the determination threshold.
  • Another aspect of the present invention includes a linear equalizer that receives a received signal, performs waveform equalization and signal amplification, and the above-described decision feedback equalizer that uses an output of the linear equalizer as an input signal. It is a receiver equipped.
  • FIG. 3 is a block diagram showing a decision feedback equalizer according to the first embodiment. The graph which shows the effect of an Example.
  • Notations such as “first”, “second”, and “third” in this specification and the like are attached to identify the constituent elements, and do not necessarily limit the number, order, or contents thereof. is not.
  • a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.
  • the outline of the representative example of the embodiment described below includes the following features.
  • One example is to adjust the decision threshold so that an error does not occur even if the amplitude decreases due to linearity in a specific data transition pattern by giving an offset to the result of automatic convergence of the decision threshold of the value in a PAM modulated signal It is a receiver with means to do.
  • the linearity is greatly affected when the data transition is large and the voltage transitions from minimum to maximum or vice versa. At that time, the gain becomes smaller than other conditions, and the amplitude becomes smaller. Therefore, it is mistaken to be smaller or larger than the determination threshold. Therefore, it is possible to prevent such an error by adding an offset to the determination threshold value itself to make it smaller.
  • Fig. 1 shows an example of an electric signal transmission device.
  • a signal processing semiconductor integrated device for example, a substrate 101 on which a signal transmission ASIC (Application Specific Integrated Circuit) 102 is mounted and a data rate conversion semiconductor integrated device, for example, a substrate 106 on which a signal transmission ASIC 107 is mounted, are connected to a connector 103, communication A signal is transmitted and received between the signal transmission ASIC 102 and the signal transmission ASIC 107 by being connected via the medium 104 and the connector 105.
  • the communication medium 104 may be a line on a substrate or a communication cable. There may be a plurality of communication media 104 signals.
  • Fig. 2 shows another example of an electric signal transmission device.
  • a substrate 201 on which a signal transmission ASIC 202 and a rate conversion ASIC 203 are mounted and a substrate 207 on which a signal transmission ASIC 208 is mounted are connected via a connector 204, a communication medium 205, and a connector 206.
  • the signal rate of the signal transmission ASIC 202 is changed by the rate conversion ASIC 203.
  • the signal transmission ASIC 202 outputs two 28 Gbps signals
  • the rate conversion ASIC 203 converts the signal into one 56 Gbps signal, thereby converting the number of signals.
  • the signal output from the ASIC 202 is input to the rate conversion ASIC 203, and the data rate is converted and output.
  • the output of the rate conversion ASIC 203 is input to the ASIC 208 through the connector 204, the communication medium 205, and the connector 206.
  • the output of the ASIC 208 is input to the rate conversion ASIC 203 through the connector 206, the communication medium 205, and the connector 204.
  • the input signal is converted in data rate by the rate conversion ASIC 203, and the output of the rate conversion ASIC 203 is input to the signal transmission ASIC 202.
  • FIG. 3 is a block diagram of the signal transmission ASIC 102, the signal transmission ASIC 107, the signal transmission ASIC 202, and the signal transmission ASIC 208.
  • the signal transmission ASIC 102 when a configuration common to these signal transmission ASICs is described, it will be referred to as the signal transmission ASIC 102.
  • the signal transmission ASIC 102 includes a signal processing unit 301, a transmission unit 302, and a reception unit 303.
  • a signal processing unit 301 When the signal transmission ASIC 102 has a plurality of lanes, a plurality of transmission units 302 and reception units 303 are configured.
  • the transmission / reception is possible. However, the reception only or the transmission only may be used.
  • the transmission parallel data signal 311 from the signal processing unit 301 is sent to a MUX (Multiplexer) 304 in the transmission unit 302, and parallel-serial conversion is performed using a transmission unit clock 312 from a CDR (Clock and Data Recovery) 308.
  • the transmission serial data signal 313 subjected to the parallel-serial conversion is sent to an FFE (Feed Forward Equalizer) 305, and the FFE 305 equalizes the input signal and outputs a transmission signal 314.
  • FFE eed Forward Equalizer
  • the linear equalizer 306 in the receiving unit 303 receives the received signal 315 that has received the loss of the communication path, and performs waveform equalization and signal amplification.
  • the linear equalizer 306 operates to compensate for the high frequency region attenuated in the communication path.
  • the signal 316 amplified by the linear equalizer 306 is input to a decision feedback equalizer (DFE: Decision Feedback Equalizer) 307.
  • the decision feedback equalizer 307 operates so as to cancel the intersymbol interference component of data.
  • the DFE output 317 of the decision feedback equalizer 307 is input to the CDR 308, and the CDR 308 synchronizes the clock phase with the phase of the DFE output 317 and outputs the phase synchronization clock 318 and the transmission unit clock 312.
  • the CDR 308 serial-parallel converts the DFE output 317, and the parallel received parallel data signal 319 is input to the signal processing unit 301.
  • FIG. 4 shows a block diagram of the rate conversion ASIC 203.
  • the rate conversion ASIC 203 includes a receiving unit 401 and a transmitting unit 404 on the slow data rate side, a transmitting unit 403 and a receiving unit 405 on the fast data rate side, and a signal processing unit 402.
  • FIG. 4 shows an example in which the data rate is doubled.
  • Conversion from a low data rate to a high data rate is performed as follows.
  • the low-speed side upper bit received signal 421 is input to the linear equalizer 406, and the low-speed side lower bit received signal 422 is input to the linear equalizer 407, where waveform equalization and amplification are performed.
  • the linear equalizer 406 outputs the low speed side upper bit linear equalizer output signal 423 to the decision feedback equalizer 408, and the linear equalizer 407 outputs the low speed side lower bit linear equalizer output signal 424 to the decision feedback type. Output to the equalizer 409.
  • the decision feedback equalizer 408 cancels the intersymbol interference component of the low-speed high-order bit linear equalizer output signal 423 in synchronization with the low-speed high-order bit phase synchronization clock 426 received from the CDR 410, and determines the determined low-speed high-order bit.
  • a feedback equalizer output signal (upper bit data) 425 is transmitted to the CDR 410.
  • the decision feedback equalizer 409 cancels the intersymbol interference component of the low-speed upper bit linear equalizer output signal 423 in synchronization with the low-speed low-order bit phase synchronization clock 428 received from the CDR 410, and determines the determined low-speed low-order bit.
  • a feedback equalizer output signal (lower bit data) 427 is transmitted to CDR 410.
  • the CDR 410 receives the upper bit data 425 and the lower bit data 427, and synchronizes the clock phase with the data phase. Then, the upper bit data 425 and the lower bit data 427 are serial-parallel converted, and the low speed side upper bit reception parallel data 429 and the low speed side lower bit reception parallel data 430 are transmitted to the signal processing unit 402.
  • the signal processing unit 402 adjusts the bit positions of the low-speed side upper bit reception parallel data 429 and the low-speed side lower bit reception parallel data 430 and combines them into the high-speed side transmission parallel data 431.
  • the MUX 411 receives the high-speed transmission parallel data 431, performs parallel-serial conversion on the high-speed transmission parallel data 431 using the high-speed transmission clock 432 from the CDR 415, and outputs the high-speed transmission serial data 433.
  • the FFE 412 receives the high-speed transmission serial data 433, equalizes the waveform, and outputs a high-speed transmission signal 434.
  • Conversion from a high data rate to a low data rate is performed as follows.
  • the high-speed side received signal 435 is input to the linear equalizer 413, where the waveform is equalized and amplified.
  • the high speed side linear equalizer output signal 436 of the linear equalizer 413 is input to the decision feedback equalizer 414, and the decision feedback equalizer 414 is synchronized with the high speed side phase synchronization clock 438 received from the CDR 415.
  • the intersymbol interference component of the side linear equalizer output signal 436 is canceled, and the determined fast side decision feedback equalizer output signal 437 is transmitted to the CDR 415.
  • the CDR 415 receives the high-speed decision feedback equalizer output signal 437 and synchronizes the clock phase with the phase of the high-speed decision feedback equalizer output signal. Then, the high-speed side decision feedback equalizer output signal 437 is serial-parallel converted, and the high-speed side reception parallel data 439 is transmitted to the signal processing unit 402.
  • the signal processing unit 402 divides the high-speed side reception parallel data 439 into the low-speed side upper bit transmission parallel data 440 and the low-speed side lower bit transmission parallel data 441 and transmits them to the MUX 416 and the MUX 417, respectively.
  • the MUX 416 receives the low-speed side transmission unit clock 442 from the CDR 410, uses the low-speed side transmission unit clock 442 to perform parallel-serial conversion on the low-speed side upper bit transmission parallel data 440, and outputs the low-speed side upper bit transmission serial data signal 443 to the FFE 418. .
  • the MUX 417 receives the low-speed side transmission unit clock 442 from the CDR 410, uses the low-speed side transmission unit clock 442 to perform parallel-serial conversion on the low-speed side low-order bit transmission parallel data 441, and outputs the low-speed side low-order bit transmission serial data signal 444 to the FFE 419.
  • the FFE 418 equalizes the waveform of the low-speed upper bit transmission serial data signal 443 and outputs the low-speed upper bit transmission signal 445.
  • the FFE 419 equalizes the waveform of the low-speed low-order bit transmission serial data signal 444 and outputs a low-speed low-order bit transmission signal 446.
  • FIG. 5 shows an example of the linear equalizers 306, 406, 407, and 413.
  • the linear equalizer 306 will be cited.
  • the linear equalizer 306 has a differential amplifier configuration, and a pair of signal amplification transistor 1201, signal amplification transistor 1202, load resistors 1207, 1208, and degeneration.
  • a resistor 1203, a degeneration capacitor 1204, a constant current source 1205, and a constant current source 1206 are included.
  • the load resistor 1207 and the load resistor 1208 have the same size, and the transistor 1201 and the transistor 1202 have the same size.
  • the positive input signal 1209 is input to the transistor 1201 and amplified, and the negative output signal 1211 is output.
  • the negative input signal 1210 is input to the transistor 1202 and amplified, and the positive output signal 1212 is output.
  • the source 1213 of the transistor 1201 and the source 1214 of the transistor 1202 are connected by a degeneration resistor 1203 and a degeneration capacitor 1204 so that the voltage difference between the positive output signal 1212 and the negative output signal 1211 is positive.
  • the gain divided by the voltage difference between the input signal 1209 and the negative input signal 1210 is a value obtained by dividing the values of the load resistor 1207 and the load resistor 1208 by the parallel impedance of the degeneration resistor 1203 and the degeneration capacitor 1204. Therefore, the frequency characteristic of the gain in the linear equalizer is a high-pass filter characteristic, and the high frequency has a higher gain than the low frequency. Therefore, it is possible to correct the signal by amplifying the amplitude on the high frequency side with respect to the signal whose amplitude decreases as the frequency increases.
  • the linear equalizer 306 due to the effect of element miniaturization or the like, there may be a nonlinear characteristic that the gain decreases as the input signal increases. For this reason, when a multilevel signal is handled, the gain may vary depending on the state of data transition. For example, when a four-value symbol of 0, 1, 2, 3 is transmitted with an analog signal of 0, 1, 2, 3 mV by amplitude modulation, a sufficient gain is obtained at the transition from 0 to 1, but 0 to 3 There may be cases where the gain to the transition is not sufficient. When the linear equalizer 306 has insufficient equalization or non-linearity, the larger the transition between symbols, the more likely it is affected, and the upper and lower sides of the symbol are crushed. When multi-level determination is performed on the output of the linear equalizer 306 using a decision feedback equalizer, the conventional decision feedback equalizer drags an error in the previous data. Becomes even more prominent.
  • FIG. 6 shows the configuration of the decision feedback equalizer of the comparative example.
  • a decision feedback equalizer refers to an equalizer that includes a decision in a feedback loop.
  • the waveform is passed through a delay circuit and optimized by the least square method so that the error between the equalized waveform and the ideal waveform is minimized.
  • Intersymbol interference is reduced by multiplying the coefficient and adding it to the waveform immediately before the determined waveform.
  • a phenomenon in which the influence of the decision error does not converge to the equalized state may occur around the loop.
  • the decision feedback equalizer 307 includes an adder 501, a determiner 502, a flip-flop 503, a shift register (SR) 504, a tap coefficient multiplier 505, a tap coefficient multiplier 506, a tap coefficient multiplier 507, and a tap coefficient multiplier. 508, a tap coefficient multiplier 509, a tap coefficient calculator (TAPC) 510, and a determination threshold value calculator (THC) 511.
  • the tap coefficient calculator 510 and the determination threshold calculator 511 can be configured in a digital configuration, and can be realized by hardware such as an FPGA (Field Programmable Gate Array) or an ASIC.
  • the adder 501 adds the output of the tap coefficient multipliers 505, 506, 507, 508, and 509 to the input signal (IN) 521, and cancels the intersymbol interference component of the input signal 521.
  • the determiner 502 compares the output of the adder 501 with the determination threshold value 523 to determine a logical value. For example, in the case of a PAM4 determiner, the input value is determined as 0, 1, 2, or 3. The output of the determiner 502 is sampled and held by the flip-flop 503 at the edge timing of the clock (CLK) 522.
  • CLK clock
  • the output of the flip-flop 503 is output as a decision feedback equalizer output signal 524 which is an output of the decision equalizer, and is input to the tap coefficient multiplier 505 and the shift register 504.
  • the shift register 504 takes in the decision feedback equalizer output signal 524 and outputs data obtained by delaying the time for each cycle of the clock 522.
  • the signal delayed by one clock is input to the tap coefficient multiplier 506 of the second tap
  • the signal delayed by two clocks is input to the tap coefficient multiplier 507 of the third tap
  • the signal delayed by three clocks is the tap coefficient of the fourth tap.
  • a signal input to the multiplier 508 and delayed by 4 clocks is input to the tap coefficient multiplier 508 of the fifth tap.
  • the tap coefficient multipliers 505, 506, 507, 508, and 509 multiply the input data by the tap coefficients and output the results to the adder 501.
  • the tap coefficients of the tap coefficient multipliers 505, 506, 507, 508, and 509 are the tap coefficient calculator 510 and the output of the adder 501 and the output of the determination threshold calculator 511, and the determination feedback type equalizer output. Based on the signal 524, it is calculated at each timing of the clock 522.
  • the determination threshold value 523 is calculated at each timing of the clock 522 based on the output of the adder 501 and the determination feedback equalizer output signal 524 in the determination threshold calculator 511.
  • the waveform shaping that could not be equalized by the linear equalizer 306 by feeding back the output of the decision equalizer multiplied by the tap coefficient It is possible to do. However, since the output of the equalizer multiplied by the tap coefficient is fed back, once there is an error in the output, the influence of the error propagates to the subsequent data.
  • Fig. 7 shows the EYE waveform of the PAM4 modulation signal when circuit nonlinearity is affected.
  • signals that transition between “0”, “1”, “2”, and “3” symbols are superimposed.
  • Such a signal can be obtained as the output of the linear equalizers 306, 406, 407, 413.
  • These signals can be identified using determination threshold values 602, 603, and 604, and four values can be obtained.
  • the determination threshold 602 is, for example, + aV
  • the determination threshold 603 is, for example, -aV
  • the determination threshold 604 is, for example, 0V.
  • “3” can be determined when the input signal exceeds the determination threshold 602, and “2” can be determined between the determination thresholds 602 and 604.
  • the gain varies depending on the input amplitude.
  • a multilevel modulation signal such as PAM4
  • the signal amplitude is reduced as shown in FIG. 7 due to the data transition pattern, and the EYE aperture is narrowed.
  • the data pattern 601 transitioning from 0 ⁇ 3, 3 ⁇ there is no voltage difference between the determination threshold 602 and the determination threshold 603, and an error is likely to occur due to noise. In this way, errors tend to occur depending on the data pattern.
  • the margin above the determination threshold 602 and the margin below the determination threshold 603 are reduced, but the margin below the determination threshold 602 and the margin above the determination threshold 603 are It does not change. For this reason, it is considered that noise tolerance can be increased by moving the determination threshold value 602 and the determination threshold value 603 toward the margin. In a typical example, when a transition is made from the symbol x to the furthest symbol y, it is considered that the noise tolerance can be increased by moving the determination threshold for determining the symbol y so as to approach the symbol x.
  • the determination threshold value 602 is moved downward, the possibility of erroneous determination of symbol 3 as symbol 2 is reduced, but the possibility of erroneous determination of symbol 2 as symbol 3 is increased. Is required.
  • FIG. 8 shows an example of decision feedback equalizers 307, 408, 409, and 414 that realize a configuration in which noise tolerance is increased by moving the decision threshold.
  • the decision feedback equalizer 307 is referred to.
  • a threshold adder 701 is added to the configuration of FIG. 6, and a threshold offset (OS) 702 is added from an external register or the like.
  • the threshold adder 701 adds the threshold offset 702 to the determination threshold 523 and changes the determination threshold of the determiner 502. Thereby, an offset is added to the determination threshold value 602 and the determination threshold value 603 of FIG.
  • the determination threshold 602 When the determination threshold 602 is + aV, the determination threshold 603 is ⁇ aV, and the determination threshold 604 is 0V, if the offset (OS) is a negative value, the determination threshold 602 is + (a ⁇ OS) V and the determination threshold 603 is -(A-OS) V. As a result, as indicated by an arrow 700 in FIG. 7, the determination threshold 602 is lowered, the determination threshold 603 is increased, and the margin for the data pattern 601 that is easily affected by the nonlinearity of the circuit can be increased.
  • Figure 9 shows the simulation result of BER (Bit ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ Error ⁇ ⁇ Rate) when an offset is added to the threshold under the condition that the circuit has nonlinearity.
  • BER Bit ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ Error ⁇ ⁇ Rate
  • the offset is ⁇ 20 mV
  • the BER is improved by about one digit compared to when no offset is added.
  • an appropriate threshold value offset 702 is determined in advance from such simulation results and experimental results, and is input to the decision feedback equalizer 307 from the outside.
  • FIG. 10 shows a second embodiment.
  • a predetermined threshold offset 702 is input to the decision feedback equalizer 307.
  • the second embodiment when the signal correction amount in the decision feedback equalizer 307 is large, automatic adjustment is performed so as to apply a threshold offset.
  • the decision feedback equalizer 307 when the signal correction amount is large, the influence of the decision error is easily propagated and an error is likely to occur. For this reason, an error-prone state is determined, and a threshold offset is applied or a large threshold offset is applied.
  • the threshold offset to be added is automatically calculated based on the tap coefficient of the first tap of the decision feedback equalizer.
  • a fixed value is given.
  • a threshold offset can be adapted to the received loss to give a threshold offset according to conditions. Since only a fixed value is given in the first embodiment, it is necessary to take a margin for the optimum value. However, in the second embodiment, an optimum threshold offset can be given even if the conditions change.
  • the magnitude of the absolute value of the tap coefficient obtained by the tap coefficient calculator 510 of the decision feedback equalizer 307 is determined by the amplitude of the output of the decision equalizer. Since the threshold offset is preferably set to a larger value as the amplitude is larger, the magnitude relationship can be determined by the tap coefficient.
  • the tap coefficient of the first tap of the decision feedback equalizer is a coefficient for the immediately preceding signal, and the larger the tap coefficient of the first tap, the larger the signal correction amount by the decision feedback equalizer. For this reason, when the tap coefficient of the first tap is large, there is a high possibility that an error will occur in the next determination result when there is an error in the previous determination result.
  • the presence or absence of the threshold offset or the magnitude can be determined based on the absolute value of the tap coefficient.
  • the threshold offset based on the tap coefficient of the first tap, it is possible to improve the error by adding the threshold offset under the condition that the error is likely to occur.
  • the second embodiment includes a threshold offset determiner 901 that determines a threshold offset from a tap coefficient.
  • the threshold offset determiner 901 In response to the input of the tap coefficient 525, the threshold offset determiner 901 outputs a threshold offset 902 according to an internal function.
  • the threshold offset 902 is added to the determination threshold 523 in the threshold adder 701, and the addition result is used as the determination threshold of the determiner 502.
  • the simplest example of the internal function of the threshold offset determiner 901 is to truncate after the decimal point to discard the lower bits of the tap coefficient 525. Moreover, you may combine functions, such as a linear function and a quadratic function, and truncation after a decimal point. Further, it is possible to prevent the threshold offset from being added or output unless the absolute value of the tap coefficient 525 is a certain value or more. There is also a method in which the output of the threshold offset determiner 901 is also inclined according to the tap coefficient.
  • FIG. 11 shows a third embodiment.
  • a function selection signal (SL) 1001 is input to the threshold value offset determiner 901 compared to the second embodiment.
  • the internal function of the threshold offset determiner 901 can be selected from a register or the like outside the decision feedback equalizer.
  • the formula for calculating the threshold offset from the tap coefficient can be changed after the LSI is manufactured. This makes it possible to select an effective function based on the evaluation without redesign even if there is a defect in the function parameters at the design stage. Therefore, the design period can be shortened, leading to cost reduction.
  • FIG. 12 shows a fourth embodiment.
  • An analog-to-digital converter (ADC) 1101 is added to the second embodiment of FIG. 10, and the flip-flop 503 is deleted.
  • ADC analog-to-digital converter
  • the decision feedback equalizer includes an ADC 1101, an adder 501, a determiner 502, a shift register 504, a tap coefficient multiplier 505, a tap coefficient multiplier 506, a tap coefficient multiplier 507, and a tap coefficient multiplier. 508, a tap coefficient multiplier 509, a tap coefficient calculator 510, a determination threshold calculator 511, and a threshold offset determiner 901.
  • the ADC 1101 samples and holds the input signal 521 at the timing of the edge of the clock 522, and converts the analog signal into a digital code.
  • the adder 501 adds the outputs of the tap coefficient multipliers 505, 506, 507, 508, and 509 to the ADC output signal 1102, and cancels the intersymbol interference component of the ADC output signal 1102.
  • the determiner 502 compares the output of the adder 501 with the result obtained by adding the threshold offset 902 to the determination threshold 523 in the threshold adder 701, and determines the logical value. For example, in the case of a PAM4 determiner, the input value is determined as 0, 1, 2, or 3.
  • the output of the decision unit 502 is outputted as a decision feedback equalizer output signal 524 which is the output of the decision equalizer, while being inputted to the tap coefficient multiplier 505 and the shift register 504.
  • the shift register 504 takes in the decision feedback equalizer output signal 524 and outputs data delayed in time for each cycle of the clock 522.
  • the signal delayed by one clock is input to the tap coefficient multiplier 506 of the second tap
  • the signal delayed by two clocks is input to the tap coefficient multiplier 507 of the third tap
  • the signal delayed by three clocks is the tap coefficient of the fourth tap.
  • a signal input to the multiplier 508 and delayed by 4 clocks is input to the tap coefficient multiplier 508 of the fifth tap.
  • the tap coefficient multipliers 505, 506, 507, 508, and 509 multiply the input data by the tap coefficients and output the results to the adder 501.
  • the tap coefficients of the tap coefficient multipliers 505, 506, 507, 508, and 509 are output from the adder 501 by the tap coefficient calculator 510, the determination threshold value 523 from the determination threshold calculator 511, and the determination feedback equalizer output signal 524, respectively. Calculated based on The determination threshold 523 is calculated by the determination threshold calculator 511 based on the output of the adder 501 and the determination feedback equalizer output signal 524.
  • the threshold offset determiner 901 receives the tap coefficient 525 and calculates the threshold offset 902 according to the internal function.
  • the ADC 1101 in the decision equalizer by having the ADC 1101 in the decision equalizer, everything after the ADC output can be handled as a digital signal, and the operation of the internal block can be easily changed by software. Thus, it is the structure which can improve versatility.
  • an electric signal transmission device that corrects a data error caused by data transition of a multilevel signal in a PAM (Pulse Amplitude Modulation) signal and expands the EYE width.
  • PAM Pulse Amplitude Modulation
  • the present invention is not limited to the above-described embodiment, and includes various modifications.
  • a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment.
  • It can be used for receivers for high-speed wired transmission and semiconductor integrated circuits that can be used for them.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The purpose of the invention is to reduce bit errors caused by circuit linearity and data pattern. An aspect of the invention is a decision feedback equalizer comprising: a first adder that adds a correction value to an input signal; a decision unit that decides a logic value from an output of the first adder according to a first decision threshold value; a flip-flop that samples and holds an output of the decision unit at the timing of a clock; a shift register that receives an output of the flip-flop and the clock and delays the output of the flip-flop in each clock period; a multiplier that multiplies the output of the flip-flop and an output of the shift register by a correction coefficient and outputs a correction value; a correction coefficient calculator that calculates, from the output of the first adder and the output of the flip-flop, the correction coefficient at each timing of the clock; a decision threshold value calculator that calculates, from the output of the first adder and the output of the flip-flop, a second decision threshold value at each timing of the clock; and a second adder that adds a threshold value offset to the second decision threshold value and outputs the first decision threshold value.

Description

判定帰還型等化器およびそれを用いた受信機Decision feedback equalizer and receiver using the same
　本発明は、高速有線伝送向け受信機およびそれに使用可能な半導体集積回路に関するもので、特に回路の線形性に対してエラー耐性を上げる技術に関する。 The present invention relates to a receiver for high-speed wired transmission and a semiconductor integrated circuit that can be used for the receiver, and more particularly to a technique for increasing error resistance with respect to circuit linearity.
　近年ビッグデータ活用に注目が集まっており、データセンタにおける通信量及びデータ処理量は増加傾向にある。それに対応して情報通信機器のデータ量の増加および処理能力の向上が進展している。その際に大規模データ処理のボトルネックとなる装置内外の通信速度も同様に向上しつつある。例えば装置外の通信ではチャネル当りの伝送速度は56Gbpsに向かって規格化されつつある。 In recent years, attention has been focused on the use of big data, and the amount of communication and data processing in data centers are increasing. Correspondingly, an increase in the amount of data and an improvement in processing capacity of information communication devices are progressing. At this time, the communication speed inside and outside the apparatus, which becomes a bottleneck for large-scale data processing, is also improving. For example, in communication outside the device, the transmission rate per channel is being standardized toward 56 Gbps.
　通信の高速化により、通信路の伝送損失は増加し、データの1UI（Unit Interval）幅も狭くなるため、従来のNRZ（Non Return to Zero）変調信号では通信が困難になると考えられている。このように時間方向の高速化に限界が見えてきており、チャネル当り伝送速度56Gbpsとなる世代では多値変調の1種であるPAM-4（Pulse Amplitude Modulation）を用いることが提案されている（非特許文献１参照）。 As the communication speed increases, the transmission loss of the communication path increases and the 1 UI (Unit Interval) width of the data also narrows. Therefore, it is considered that communication is difficult with the conventional NRZ (Non Return Return to Zero) modulation signal. In this way, there is a limit to speeding up in the time direction, and it has been proposed to use PAM-4 (Pulse Amplitude Modulation), which is a type of multi-level modulation, in the generation with a transmission rate of 56 Gbps per channel ( Non-patent document 1).
　多値変調であるPAM変調信号を用いた信号伝送においては、回路の線形性の影響により信号振幅によりゲインが異なるため、最小の電圧から最大の電圧に遷移するようなパターンではゲインが小さくなる。さらに、判定帰還型等化器を用いた場合は、前のデータでのエラーが次のデータに影響して等化不足が生じ、次のデータもエラーになるバーストエラーが起きる。 In signal transmission using a PAM modulation signal that is multi-level modulation, the gain varies depending on the signal amplitude due to the influence of the linearity of the circuit. Therefore, the gain becomes small in a pattern in which the minimum voltage is changed to the maximum voltage. Furthermore, when a decision feedback equalizer is used, an error in the previous data affects the next data, resulting in a lack of equalization, and a burst error in which the next data also becomes an error occurs.
　そこで、本発明では回路の線形性とデータパターン起因で生じるビットエラーを低減することを目的とする。 Accordingly, an object of the present invention is to reduce bit errors caused by circuit linearity and data patterns.
　本発明の一側面は、入力信号に補正値を加える第１の加算器を有し、第１の加算器の出力を第１の判定閾値に従って論理値に判定する判定器を有し、判定器の出力をクロックのタイミングでサンプルホールドするフリップフロップを有し、フリップフロップの出力とクロックを受け取りクロックの周期ごとにフリップフロップの出力を遅延させるシフトレジスタを有し、フリップフロップの出力とシフトレジスタの出力とに補正係数を掛けて補正値を出力する掛け算器を有し、第１の加算器の出力とフリップフロップの出力とからクロックのタイミングごとに補正係数を計算する補正係数計算機を有し、第１の加算器の出力とフリップフロップの出力とからクロックのタイミングごとに第２の判定閾値を計算する判定閾値計算機を有し、第２の判定閾値に閾値オフセットを加えて第１の判定閾値を出力する第２の加算器を有する判定帰還型等化器である。 One aspect of the present invention includes a first adder that adds a correction value to an input signal, a determiner that determines the output of the first adder as a logical value according to a first determination threshold, and a determiner A flip-flop that samples and holds the output of the flip-flop at the clock timing, and has a shift register that receives the output of the flip-flop and the clock and delays the output of the flip-flop every clock cycle. A multiplier that multiplies the output by a correction coefficient and outputs a correction value; a correction coefficient calculator that calculates a correction coefficient for each clock timing from the output of the first adder and the output of the flip-flop; A determination threshold calculator that calculates a second determination threshold for each clock timing from the output of the first adder and the output of the flip-flop; A decision feedback equalizer having a second adder for outputting a first determination threshold the threshold value offset added to the determination threshold.
　本発明の他の一側面は、受信信号を受け取り、波形等化および信号増幅を行なう線形等化器と、線形等化器の出力を入力信号とする上述の判定帰還型等化器と、を備える受信機である。 Another aspect of the present invention includes a linear equalizer that receives a received signal, performs waveform equalization and signal amplification, and the above-described decision feedback equalizer that uses an output of the linear equalizer as an input signal. It is a receiver equipped.
　回路の線形性とデータパターン起因で生じるビットエラーを低減することができる。 Bit errors caused by circuit linearity and data patterns can be reduced.
基板間を通信する電気信号伝送装置のブロック図。The block diagram of the electric signal transmission apparatus which communicates between board | substrates. 基板間を通信する際にデータレート変換機を用いた電気信号伝送装置のブロック図。The block diagram of the electric signal transmission apparatus which used the data rate converter when communicating between board | substrates. 信号処理用半導体集積回路の１レーンのブロック図。The block diagram of 1 lane of the semiconductor integrated circuit for signal processing. データレート変換用半導体集積回路のブロック図。The block diagram of the semiconductor integrated circuit for data rate conversion. 線形等化器の回路図。The circuit diagram of a linear equalizer. ５タップの判定帰還型等化器のブロック図。The block diagram of a 5-tap decision feedback equalizer. PAM4信号における回路の非線形性によるデータパターンへの影響を示す波形図。The wave form diagram which shows the influence on the data pattern by the nonlinearity of the circuit in a PAM4 signal. 第1の実施例に当たる判定帰還型等化器を示すブロック図。FIG. 3 is a block diagram showing a decision feedback equalizer according to the first embodiment. 実施例の効果を示すグラフ図。The graph which shows the effect of an Example. 第２の実施例に当たる判定帰還型等化器を示すブロック図。The block diagram which shows the decision feedback type equalizer which hits a 2nd Example. 第３の実施例に当たる判定帰還型等化器を示すブロック図。The block diagram which shows the decision feedback type equalizer which hits a 3rd Example. 第４の実施例に当たる判定帰還型等化器を示すブロック図。The block diagram which shows the decision feedback type equalizer which hits a 4th Example.
　以下、図面を参考にして詳細を述べる。ただし、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。本発明の思想ないし趣旨から逸脱しない範囲で、その具体的構成を変更し得ることは当業者であれば容易に理解される。 Details will be described below with reference to the drawings. However, the present invention is not construed as being limited to the description of the embodiments below. Those skilled in the art will readily understand that the specific configuration can be changed without departing from the spirit or the spirit of the present invention.
　以下に説明する発明の構成において、同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、重複する説明は省略することがある。 In the structure of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and redundant description may be omitted.
　同一あるいは同様な機能を有する要素が複数ある場合には、同一の符号に異なる添字を付して説明する場合がある。ただし、複数の要素を区別する必要がない場合には、添字を省略して説明する場合がある。 When there are a plurality of elements having the same or similar functions, there may be cases where the same reference numerals are attached with different subscripts. However, when there is no need to distinguish between a plurality of elements, the description may be omitted.
　本明細書等における「第１」、「第２」、「第３」などの表記は、構成要素を識別するために付するものであり、必ずしも、数、順序、もしくはその内容を限定するものではない。また、構成要素の識別のための番号は文脈毎に用いられ、一つの文脈で用いた番号が、他の文脈で必ずしも同一の構成を示すとは限らない。また、ある番号で識別された構成要素が、他の番号で識別された構成要素の機能を兼ねることを妨げるものではない。 Notations such as “first”, “second”, and “third” in this specification and the like are attached to identify the constituent elements, and do not necessarily limit the number, order, or contents thereof. is not. In addition, a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.
　図面等において示す各構成の位置、大きさ、形状、範囲などは、発明の理解を容易にするため、実際の位置、大きさ、形状、範囲などを表していない場合がある。このため、本発明は、必ずしも、図面等に開示された位置、大きさ、形状、範囲などに限定されない。 The position, size, shape, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, shape, range, etc. in order to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the position, size, shape, range, and the like disclosed in the drawings and the like.
　本明細書において単数形で表される構成要素は、特段文脈で明らかに示されない限り、複数形を含むものとする。 In this specification, a component expressed in the singular shall include the plural unless specifically indicated otherwise.
　以下で説明する実施例の代表例の概要は以下のような特徴を含む。一つの例は、PAM変調信号において、値の判定閾値の自動収束結果に対しオフセットを与えることにより、特定のデータ遷移パターンで線形性により振幅が小さくなってもエラーとならないように判定閾値を調整する手段を持つ受信機である。線形性の影響を大きく受けるのはデータ遷移が大きい、電圧が最小から最大またはその逆に遷移する時である。その際ゲインが他の条件より小さくなり、振幅が小さくなる。そのため、判定閾値より小さいまたは大きいように間違えてしまう。そこで、判定閾値自体にオフセットを加え、小さくすることによりこういったエラーを防ぐことが可能である。 The outline of the representative example of the embodiment described below includes the following features. One example is to adjust the decision threshold so that an error does not occur even if the amplitude decreases due to linearity in a specific data transition pattern by giving an offset to the result of automatic convergence of the decision threshold of the value in a PAM modulated signal It is a receiver with means to do. The linearity is greatly affected when the data transition is large and the voltage transitions from minimum to maximum or vice versa. At that time, the gain becomes smaller than other conditions, and the amplitude becomes smaller. Therefore, it is mistaken to be smaller or larger than the determination threshold. Therefore, it is possible to prevent such an error by adding an offset to the determination threshold value itself to make it smaller.
　図１に電気信号伝送装置の一例を示す。信号処理用半導体集積装置、例えば信号伝送用ASIC（Application Specific Integrated Circuit）１０２を搭載した基板１０１とデータレート変換用半導体集積装置、例えば信号伝送用ASIC１０７を搭載した基板１０６とが、コネクタ１０３、通信媒体１０４及びコネクタ１０５を介して接続され、信号伝送用ASIC１０２と信号伝送用ASIC１０７との間で信号を送受信する。通信媒体１０４は基板上の線路であったり、通信ケーブルであったりする。通信媒体１０４の信号本数は複数本あってもよい。 Fig. 1 shows an example of an electric signal transmission device. A signal processing semiconductor integrated device, for example, a substrate 101 on which a signal transmission ASIC (Application Specific Integrated Circuit) 102 is mounted and a data rate conversion semiconductor integrated device, for example, a substrate 106 on which a signal transmission ASIC 107 is mounted, are connected to a connector 103, communication A signal is transmitted and received between the signal transmission ASIC 102 and the signal transmission ASIC 107 by being connected via the medium 104 and the connector 105. The communication medium 104 may be a line on a substrate or a communication cable. There may be a plurality of communication media 104 signals.
　図２に電気信号伝送装置の別の例を示す。信号伝送用ASIC２０２とレート変換用ASIC２０３とを搭載した基板２０１と信号伝送用ASIC２０８を搭載した基板２０７とが，コネクタ２０４、通信媒体２０５、コネクタ２０６を介して接続される。 Fig. 2 shows another example of an electric signal transmission device. A substrate 201 on which a signal transmission ASIC 202 and a rate conversion ASIC 203 are mounted and a substrate 207 on which a signal transmission ASIC 208 is mounted are connected via a connector 204, a communication medium 205, and a connector 206.
　信号伝送用ASIC２０２の信号がレート変換ASIC２０３でデータレートを変更される。例えば、信号伝送用ASIC２０２が28Gbpsの信号を2本出し、レート変換用ASIC２０３が56Gbpsの信号1本に変換するというように信号1本当りのレート変換を行い、信号本数を変更する。 The signal rate of the signal transmission ASIC 202 is changed by the rate conversion ASIC 203. For example, the signal transmission ASIC 202 outputs two 28 Gbps signals, and the rate conversion ASIC 203 converts the signal into one 56 Gbps signal, thereby converting the number of signals.
　ASIC２０２から出力された信号はレート変換用ASIC２０３に入力され、データレートを変換されて出力される。レート変換用ASIC２０３の出力はコネクタ２０４、通信媒体２０５及びコネクタ２０６を通って、ASIC２０８に入力される。逆にASIC２０８の出力はコネクタ２０６、通信媒体２０５及びコネクタ２０４を通ってレート変換用ASIC２０３に入力される。前記入力された信号はレート変換用ASIC２０３でデータレートを変換され、レート変換用ASIC２０３の出力は信号伝送用ASIC２０２に入力される。 The signal output from the ASIC 202 is input to the rate conversion ASIC 203, and the data rate is converted and output. The output of the rate conversion ASIC 203 is input to the ASIC 208 through the connector 204, the communication medium 205, and the connector 206. Conversely, the output of the ASIC 208 is input to the rate conversion ASIC 203 through the connector 206, the communication medium 205, and the connector 204. The input signal is converted in data rate by the rate conversion ASIC 203, and the output of the rate conversion ASIC 203 is input to the signal transmission ASIC 202.
　図３に信号伝送用ASIC１０２、信号伝送用ASIC１０７、信号伝送用ASIC２０２、信号伝送用ASIC２０８のブロック図を示す。簡便のため、これらの信号伝送用ASICに共通する構成を説明する際には、信号伝送用ASIC１０２として引用することにする。 FIG. 3 is a block diagram of the signal transmission ASIC 102, the signal transmission ASIC 107, the signal transmission ASIC 202, and the signal transmission ASIC 208. For the sake of simplicity, when a configuration common to these signal transmission ASICs is described, it will be referred to as the signal transmission ASIC 102.
　信号伝送用ASIC１０２は、信号処理部３０１、送信部３０２、受信部３０３で構成される。信号伝送用ASIC１０２が複数レーンを持つ時は、送信部３０２、受信部３０３が複数個で構成される。図３の例では、送受信が可能な構成としているが、受信のみ、あるいは送信のみの構成としてもよい。 The signal transmission ASIC 102 includes a signal processing unit 301, a transmission unit 302, and a reception unit 303. When the signal transmission ASIC 102 has a plurality of lanes, a plurality of transmission units 302 and reception units 303 are configured. In the example of FIG. 3, the transmission / reception is possible. However, the reception only or the transmission only may be used.
　信号処理部３０１からの送信パラレルデータ信号３１１は送信部３０２内のMUX（Multiplexer）３０４に送られ、CDR（Clock and Data Recovery）３０８からの送信部クロック３１２を用いてパラレルシリアル変換される。パラレルシリアル変換された送信シリアルデータ信号３１３はFFE（Feed Forward Equalizer）３０５に送られ、FFE３０５は入力信号を波形等化し送信信号３１４を出力する。 The transmission parallel data signal 311 from the signal processing unit 301 is sent to a MUX (Multiplexer) 304 in the transmission unit 302, and parallel-serial conversion is performed using a transmission unit clock 312 from a CDR (Clock and Data Recovery) 308. The transmission serial data signal 313 subjected to the parallel-serial conversion is sent to an FFE (Feed Forward Equalizer) 305, and the FFE 305 equalizes the input signal and outputs a transmission signal 314.
　受信部３０３内の線形等化器３０６は通信路の損失を受けた受信信号３１５を受け取り、波形等化及び信号増幅を行う。線形等化器３０６は、通信路で減衰した高周波領域を補償するように動作する。線形等化器３０６により増幅された信号３１６は、判定帰還型等化器（DFE：Decision Feedback Equalizer）３０７に入力される。判定帰還型等化器３０７は、データの符号間干渉成分を打ち消すように動作するものである。判定帰還型等化器３０７のDFE出力３１７はCDR３０８に入力され、CDR３０８はDFE出力３１７の位相に対してクロック位相を同期させ、位相同期クロック３１８、送信部クロック３１２を出力する。また、CDR３０８はDFE出力３１７をシリアルパラレル変換し、パラレル化された受信パラレルデータ信号３１９は信号処理部３０１に入力される。 The linear equalizer 306 in the receiving unit 303 receives the received signal 315 that has received the loss of the communication path, and performs waveform equalization and signal amplification. The linear equalizer 306 operates to compensate for the high frequency region attenuated in the communication path. The signal 316 amplified by the linear equalizer 306 is input to a decision feedback equalizer (DFE: Decision Feedback Equalizer) 307. The decision feedback equalizer 307 operates so as to cancel the intersymbol interference component of data. The DFE output 317 of the decision feedback equalizer 307 is input to the CDR 308, and the CDR 308 synchronizes the clock phase with the phase of the DFE output 317 and outputs the phase synchronization clock 318 and the transmission unit clock 312. The CDR 308 serial-parallel converts the DFE output 317, and the parallel received parallel data signal 319 is input to the signal processing unit 301.
　図４にレート変換ASIC２０３のブロック図を示す。レート変換ASIC２０３はデータレートが遅い側の受信部４０１と送信部４０４、データレートが速い側の送信部４０３と受信部４０５、信号処理部４０２で構成される。図４ではデータレートを２倍に変換する例を示している。 FIG. 4 shows a block diagram of the rate conversion ASIC 203. The rate conversion ASIC 203 includes a receiving unit 401 and a transmitting unit 404 on the slow data rate side, a transmitting unit 403 and a receiving unit 405 on the fast data rate side, and a signal processing unit 402. FIG. 4 shows an example in which the data rate is doubled.
　低いデータレートから高いデータレートへの変換は下記の様に行われる。低速側上位ビット受信信号４２１が線形等化器４０６に、低速側下位ビット受信信号４２２が線形等化器４０７に入力され、それぞれ波形等化及び増幅される。線形等化器４０６は低速側上位ビット線形等化器出力信号４２３を判定帰還型等化器４０８に出力し、線形等化器４０７は低速側下位ビット線形等化器出力信号４２４を判定帰還型等化器４０９に出力する。判定帰還型等化器４０８はCDR４１０から受け取った低速側上位ビット位相同期クロック４２６に同期して低速側上位ビット線形等化器出力信号４２３の符号間干渉成分を打ち消し、判定した低速側上位ビット判定帰還型等化器出力信号（上位ビットデータ）４２５をCDR４１０に伝送する。判定帰還型等化器４０９はCDR４１０から受け取った低速側下位ビット位相同期クロック４２８に同期して低速側上位ビット線形等化器出力信号４２３の符号間干渉成分を打ち消し、判定した低速側下位ビット判定帰還型等化器出力信号（下位ビットデータ）４２７をCDR４１０に伝送する。CDR４１０は上位ビットデータ４２５と下位ビットデータ４２７を受け取り、データの位相にクロックの位相を同期させる。そして、上位ビットデータ４２５と下位ビットデータ４２７をシリアルパラレル変換し、低速側上位ビット受信パラレルデータ４２９と低速側下位ビット受信パラレルデータ４３０を信号処理部４０２に伝送する。 Conversion from a low data rate to a high data rate is performed as follows. The low-speed side upper bit received signal 421 is input to the linear equalizer 406, and the low-speed side lower bit received signal 422 is input to the linear equalizer 407, where waveform equalization and amplification are performed. The linear equalizer 406 outputs the low speed side upper bit linear equalizer output signal 423 to the decision feedback equalizer 408, and the linear equalizer 407 outputs the low speed side lower bit linear equalizer output signal 424 to the decision feedback type. Output to the equalizer 409. The decision feedback equalizer 408 cancels the intersymbol interference component of the low-speed high-order bit linear equalizer output signal 423 in synchronization with the low-speed high-order bit phase synchronization clock 426 received from the CDR 410, and determines the determined low-speed high-order bit. A feedback equalizer output signal (upper bit data) 425 is transmitted to the CDR 410. The decision feedback equalizer 409 cancels the intersymbol interference component of the low-speed upper bit linear equalizer output signal 423 in synchronization with the low-speed low-order bit phase synchronization clock 428 received from the CDR 410, and determines the determined low-speed low-order bit. A feedback equalizer output signal (lower bit data) 427 is transmitted to CDR 410. The CDR 410 receives the upper bit data 425 and the lower bit data 427, and synchronizes the clock phase with the data phase. Then, the upper bit data 425 and the lower bit data 427 are serial-parallel converted, and the low speed side upper bit reception parallel data 429 and the low speed side lower bit reception parallel data 430 are transmitted to the signal processing unit 402.
　信号処理部４０２は低速側上位ビット受信パラレルデータ４２９と低速側下位ビット受信パラレルデータ４３０をビットの位置を調整して高速側送信パラレルデータ４３１にまとめる。MUX４１１は高速側送信パラレルデータ４３１を受け取り、CDR４１５からの高速側送信部クロック４３２を使って高速側送信パラレルデータ４３１をパラレルシリアル変換し、高速側送信シリアルデータ４３３を出力する。FFE４１２は高速側送信シリアルデータ４３３を受け取り、波形等化して高速側送信信号４３４を出力する。 The signal processing unit 402 adjusts the bit positions of the low-speed side upper bit reception parallel data 429 and the low-speed side lower bit reception parallel data 430 and combines them into the high-speed side transmission parallel data 431. The MUX 411 receives the high-speed transmission parallel data 431, performs parallel-serial conversion on the high-speed transmission parallel data 431 using the high-speed transmission clock 432 from the CDR 415, and outputs the high-speed transmission serial data 433. The FFE 412 receives the high-speed transmission serial data 433, equalizes the waveform, and outputs a high-speed transmission signal 434.
　高いデータレートから低いデータレートへの変換は下記のように行われる。高速側受信信号４３５が線形等化器４１３に入力され、波形等化及び増幅される。線形等化器４１３の高速側線形等化器出力信号４３６は判定帰還型等化器４１４に入力され、判定帰還型等化器４１４はCDR４１５から受け取った高速側位相同期クロック４３８に同期して高速側線形等化器出力信号４３６の符号間干渉成分を打ち消し、判定した高速側判定帰還型等化器出力信号４３７をCDR４１５に伝送する。CDR４１５は高速側判定帰還型等化器出力信号４３７を受け取り、高速側判定帰還型等化器出力信号の位相にクロックの位相を同期させる。そして、高速側判定帰還型等化器出力信号４３７をシリアルパラレル変換し、高速側受信パラレルデータ４３９を信号処理部４０２に伝送する。 Conversion from a high data rate to a low data rate is performed as follows. The high-speed side received signal 435 is input to the linear equalizer 413, where the waveform is equalized and amplified. The high speed side linear equalizer output signal 436 of the linear equalizer 413 is input to the decision feedback equalizer 414, and the decision feedback equalizer 414 is synchronized with the high speed side phase synchronization clock 438 received from the CDR 415. The intersymbol interference component of the side linear equalizer output signal 436 is canceled, and the determined fast side decision feedback equalizer output signal 437 is transmitted to the CDR 415. The CDR 415 receives the high-speed decision feedback equalizer output signal 437 and synchronizes the clock phase with the phase of the high-speed decision feedback equalizer output signal. Then, the high-speed side decision feedback equalizer output signal 437 is serial-parallel converted, and the high-speed side reception parallel data 439 is transmitted to the signal processing unit 402.
　信号処理部４０２は高速側受信パラレルデータ４３９を低速側上位ビット送信パラレルデータ４４０、低速側下位ビット送信パラレルデータ４４１に分割し、それぞれMUX４１６とMUX４１７に伝送する。MUX４１６はCDR４１０から低速側送信部クロック４４２を受け取り、低速側送信部クロック４４２を使って低速側上位ビット送信パラレルデータ４４０をパラレルシリアル変換し、低速側上位ビット送信シリアルデータ信号４４３をFFE４１８に出力する。MUX４１７はCDR４１０から低速側送信部クロック４４２を受け取り、低速側送信部クロック４４２を使って低速側下位ビット送信パラレルデータ４４１をパラレルシリアル変換し、低速側下位ビット送信シリアルデータ信号４４４をFFE４１９に出力する。FFE４１８は低速側上位ビット送信シリアルデータ信号４４３を波形等化し、低速側上位ビット送信信号４４５を出力する。FFE４１９は低速側下位ビット送信シリアルデータ信号４４４を波形等化し、低速側下位ビット送信信号４４６を出力する。 The signal processing unit 402 divides the high-speed side reception parallel data 439 into the low-speed side upper bit transmission parallel data 440 and the low-speed side lower bit transmission parallel data 441 and transmits them to the MUX 416 and the MUX 417, respectively. The MUX 416 receives the low-speed side transmission unit clock 442 from the CDR 410, uses the low-speed side transmission unit clock 442 to perform parallel-serial conversion on the low-speed side upper bit transmission parallel data 440, and outputs the low-speed side upper bit transmission serial data signal 443 to the FFE 418. . The MUX 417 receives the low-speed side transmission unit clock 442 from the CDR 410, uses the low-speed side transmission unit clock 442 to perform parallel-serial conversion on the low-speed side low-order bit transmission parallel data 441, and outputs the low-speed side low-order bit transmission serial data signal 444 to the FFE 419. . The FFE 418 equalizes the waveform of the low-speed upper bit transmission serial data signal 443 and outputs the low-speed upper bit transmission signal 445. The FFE 419 equalizes the waveform of the low-speed low-order bit transmission serial data signal 444 and outputs a low-speed low-order bit transmission signal 446.
　図５に線形等化器３０６、４０６、４０７、４１３の一例を示す。簡便のため、これらの線形等化器に共通する構成を説明する際には、線形等化器３０６として引用することにする。 FIG. 5 shows an example of the linear equalizers 306, 406, 407, and 413. For the sake of simplicity, when describing a configuration common to these linear equalizers, the linear equalizer 306 will be cited.
　図５に示すように、本実施例では線形等化器３０６は差動増幅器の構成となっており、対となる信号増幅用トランジスタ１２０１、信号増幅用トランジスタ１２０２、負荷抵抗１２０７、１２０８及びディジェネレーション抵抗１２０３、ディジェネレーション容量１２０４、定電流源１２０５、定電流源１２０６で構成される。 As shown in FIG. 5, in this embodiment, the linear equalizer 306 has a differential amplifier configuration, and a pair of signal amplification transistor 1201, signal amplification transistor 1202, load resistors 1207, 1208, and degeneration. A resistor 1203, a degeneration capacitor 1204, a constant current source 1205, and a constant current source 1206 are included.
　差動構成であるため、負荷抵抗１２０７と負荷抵抗１２０８は同一サイズであり、トランジスタ１２０１とトランジスタ１２０２も同一サイズである。正側入力信号１２０９はトランジスタ１２０１に入力され増幅され、負側出力信号１２１１が出力される。同様に負側入力信号１２１０はトランジスタ１２０２に入力され増幅され、正側出力信号１２１２が出力される。 Because of the differential configuration, the load resistor 1207 and the load resistor 1208 have the same size, and the transistor 1201 and the transistor 1202 have the same size. The positive input signal 1209 is input to the transistor 1201 and amplified, and the negative output signal 1211 is output. Similarly, the negative input signal 1210 is input to the transistor 1202 and amplified, and the positive output signal 1212 is output.
　トランジスタ１２０１のソース１２１３とトランジスタ１２０２のソース１２１４の間は、ディジェネレーション抵抗１２０３とディジェネレーション容量１２０４とで接続されることにより、正側出力信号１２１２と負側出力信号１２１１との電圧差を正側入力信号１２０９と負側入力信号１２１０の電圧差で割った利得は、負荷抵抗１２０７と負荷抵抗１２０８の値をディジェネレーション抵抗１２０３とディジェネレーション容量１２０４との並列インピーダンスで割った値となる。そのため、線形等化器における利得の周波数特性はハイパスフィルタ特性となり、高周波が低周波よりゲインが高い周波数特性となる。そのため、高周波になるほど振幅が小さくなる信号に対して、高周波側の振幅を増幅して信号補正することができる。 The source 1213 of the transistor 1201 and the source 1214 of the transistor 1202 are connected by a degeneration resistor 1203 and a degeneration capacitor 1204 so that the voltage difference between the positive output signal 1212 and the negative output signal 1211 is positive. The gain divided by the voltage difference between the input signal 1209 and the negative input signal 1210 is a value obtained by dividing the values of the load resistor 1207 and the load resistor 1208 by the parallel impedance of the degeneration resistor 1203 and the degeneration capacitor 1204. Therefore, the frequency characteristic of the gain in the linear equalizer is a high-pass filter characteristic, and the high frequency has a higher gain than the low frequency. Therefore, it is possible to correct the signal by amplifying the amplitude on the high frequency side with respect to the signal whose amplitude decreases as the frequency increases.
　ところで、線形等化器３０６では、素子微細化等の影響により、入力信号が大きくなると利得が小さくなるという非線形特性が見られることがある。このため、多値の信号を扱う場合、データの遷移の状態によっては利得が変動する場合がある。例えば０，１，２，３の４値のシンボルを、振幅変調によりアナログ信号０，１，２，３ｍＶで伝送した場合、０から１への遷移では十分な利得が得られるが、０から３への遷移では十分な利得にならない場合がある。線形等化器３０６で不足等化や非線形性がある場合、シンボル間の遷移が大きいほど影響を受けやすく、シンボルの上下が潰れ気味となる。線形等化器３０６の出力を判定帰還型等化器を用いて多値判定を行なう場合、従来の判定帰還型等化器では前のデータのエラーを引きずるため、エラーが多い系では不足等化がさらに顕著となる。 By the way, in the linear equalizer 306, due to the effect of element miniaturization or the like, there may be a nonlinear characteristic that the gain decreases as the input signal increases. For this reason, when a multilevel signal is handled, the gain may vary depending on the state of data transition. For example, when a four-value symbol of 0, 1, 2, 3 is transmitted with an analog signal of 0, 1, 2, 3 mV by amplitude modulation, a sufficient gain is obtained at the transition from 0 to 1, but 0 to 3 There may be cases where the gain to the transition is not sufficient. When the linear equalizer 306 has insufficient equalization or non-linearity, the larger the transition between symbols, the more likely it is affected, and the upper and lower sides of the symbol are crushed. When multi-level determination is performed on the output of the linear equalizer 306 using a decision feedback equalizer, the conventional decision feedback equalizer drags an error in the previous data. Becomes even more prominent.
　図６に、比較例の判定帰還型等化器の構成を示す。判定帰還型等化器とは、判定を帰還ループに含む等化器を指す。判定帰還型等化器では、先行するロジック値を判定した後、その波形を遅延回路に通し、等化後の波形と理想波形との誤差が最小になるように最小２乗法などで最適化した係数を乗算して、判定した波形の直前の波形と加算することにより符号間干渉を低減する。判定帰還型等化器では、判定誤りの影響がループ内を巡って、等化状態に収束しない現象が起きうる。 FIG. 6 shows the configuration of the decision feedback equalizer of the comparative example. A decision feedback equalizer refers to an equalizer that includes a decision in a feedback loop. In the decision feedback equalizer, after determining the preceding logic value, the waveform is passed through a delay circuit and optimized by the least square method so that the error between the equalized waveform and the ideal waveform is minimized. Intersymbol interference is reduced by multiplying the coefficient and adding it to the waveform immediately before the determined waveform. In the decision feedback equalizer, a phenomenon in which the influence of the decision error does not converge to the equalized state may occur around the loop.
　ここでは５タップの４値信号での例を示しており、タップ数や多値信号は増えても減っても同様である。判定帰還型等化器３０７は、加算器５０１、判定器５０２、フリップフロップ５０３、シフトレジスタ（SR）５０４、タップ係数掛け算器５０５、タップ係数掛け算器５０６、タップ係数掛け算器５０７、タップ係数掛け算器５０８、タップ係数掛け算器５０９、タップ係数計算機（TAPC）５１０、判定閾値計算機（THC）５１１で構成される。タップ係数計算機５１０および判定閾値計算機５１１はデジタル構成で構成でき、例えばFPGA（Field Programmable Gate Array）やASICなどのハードウエアで実現できる。 Here, an example with a 4-value signal of 5 taps is shown, and the same is true whether the number of taps or the multi-value signal is increased or decreased. The decision feedback equalizer 307 includes an adder 501, a determiner 502, a flip-flop 503, a shift register (SR) 504, a tap coefficient multiplier 505, a tap coefficient multiplier 506, a tap coefficient multiplier 507, and a tap coefficient multiplier. 508, a tap coefficient multiplier 509, a tap coefficient calculator (TAPC) 510, and a determination threshold value calculator (THC) 511. The tap coefficient calculator 510 and the determination threshold calculator 511 can be configured in a digital configuration, and can be realized by hardware such as an FPGA (Field Programmable Gate Array) or an ASIC.
　加算器５０１は入力信号（IN）５２１にタップ係数掛け算器５０５、５０６、５０７、５０８、５０９の出力を加算し、入力信号５２１の符号間干渉成分を打ち消す。 The adder 501 adds the output of the tap coefficient multipliers 505, 506, 507, 508, and 509 to the input signal (IN) 521, and cancels the intersymbol interference component of the input signal 521.
　判定器５０２は加算器５０１の出力と判定閾値５２３を比較し、論理値を判定する。例えばPAM4用判定器であれば０、１、２、３のいずれかに入力値を判定する。判定器５０２の出力はフリップフロップ５０３でクロック（CLK）５２２のエッジタイミングでサンプルホールドされる。 The determiner 502 compares the output of the adder 501 with the determination threshold value 523 to determine a logical value. For example, in the case of a PAM4 determiner, the input value is determined as 0, 1, 2, or 3. The output of the determiner 502 is sampled and held by the flip-flop 503 at the edge timing of the clock (CLK) 522.
　フリップフロップ５０３の出力は判定等化器の出力である判定帰還型等化器出力信号５２４として出力される一方、タップ係数掛け算器５０５、シフトレジスタ５０４に入力される。 The output of the flip-flop 503 is output as a decision feedback equalizer output signal 524 which is an output of the decision equalizer, and is input to the tap coefficient multiplier 505 and the shift register 504.
　シフトレジスタ５０４は判定帰還型等化器出力信号５２４を取り込み、クロック５２２の周期ごとに時間を遅らせたデータを出力する。１クロック遅らせた信号は２タップ目のタップ係数掛け算器５０６に入力され、２クロック遅らせた信号は３タップ目のタップ係数掛け算器５０７に入力され、３クロック遅らせた信号は４タップ目のタップ係数掛け算器５０８に入力され、４クロック遅らせた信号は５タップ目のタップ係数掛け算器５０８に入力される。 The shift register 504 takes in the decision feedback equalizer output signal 524 and outputs data obtained by delaying the time for each cycle of the clock 522. The signal delayed by one clock is input to the tap coefficient multiplier 506 of the second tap, the signal delayed by two clocks is input to the tap coefficient multiplier 507 of the third tap, and the signal delayed by three clocks is the tap coefficient of the fourth tap. A signal input to the multiplier 508 and delayed by 4 clocks is input to the tap coefficient multiplier 508 of the fifth tap.
　タップ係数掛け算器５０５、５０６、５０７、５０８、５０９は、それぞれ入力されたデータにタップ係数を掛け、それらの結果を加算器５０１に出力する。タップ係数掛け算器５０５、５０６、５０７、５０８、５０９のそれぞれのタップ係数は、タップ係数計算機５１０で加算器５０１の出力と判定閾値計算機５１１の出力である判定閾値５２３及び判定帰還型等化器出力信号５２４を元に、クロック５２２のタイミングごとに計算される。判定閾値５２３は判定閾値計算機５１１において、加算器５０１出力と判定帰還型等化器出力信号５２４を元に、クロック５２２のタイミングごとに計算される。 The tap coefficient multipliers 505, 506, 507, 508, and 509 multiply the input data by the tap coefficients and output the results to the adder 501. The tap coefficients of the tap coefficient multipliers 505, 506, 507, 508, and 509 are the tap coefficient calculator 510 and the output of the adder 501 and the output of the determination threshold calculator 511, and the determination feedback type equalizer output. Based on the signal 524, it is calculated at each timing of the clock 522. The determination threshold value 523 is calculated at each timing of the clock 522 based on the output of the adder 501 and the determination feedback equalizer output signal 524 in the determination threshold calculator 511.
　先に述べたように、図６の判定帰還型等化器では、判定等化器の出力にタップ係数を掛けたものをフィードバックすることにより、線形等化器３０６で等化しきれなかった波形整形を行なうことを可能にしている。しかし、等化器出力にタップ係数を掛けたものをフィードバックしているため、一度出力にエラーがあると、後のデータにエラーの影響が伝播することになる。 As described above, in the decision feedback equalizer of FIG. 6, the waveform shaping that could not be equalized by the linear equalizer 306 by feeding back the output of the decision equalizer multiplied by the tap coefficient. It is possible to do. However, since the output of the equalizer multiplied by the tap coefficient is fed back, once there is an error in the output, the influence of the error propagates to the subsequent data.
　図７に回路の非線形性が影響する場合のPAM4変調信号のEYE波形を示す。図７では、”０”，”１”，”２”，”３”のシンボル間を遷移する信号を重ねて示している。このような信号は、線形等化器３０６、４０６、４０７、４１３の出力として得ることができる。これらの信号を、判定閾値６０２，６０３，６０４を用いて識別し、４値を得ることができる。判定閾値６０２は例えば＋ａＶ，判定閾値６０３は例えば－ａＶ，判定閾値６０４は例えば０Ｖである。例えば、入力信号が判定閾値６０２を超えれば”３”、判定閾値６０２と６０４の間なら”２”のように判定することができる。 Fig. 7 shows the EYE waveform of the PAM4 modulation signal when circuit nonlinearity is affected. In FIG. 7, signals that transition between “0”, “1”, “2”, and “3” symbols are superimposed. Such a signal can be obtained as the output of the linear equalizers 306, 406, 407, 413. These signals can be identified using determination threshold values 602, 603, and 604, and four values can be obtained. The determination threshold 602 is, for example, + aV, the determination threshold 603 is, for example, -aV, and the determination threshold 604 is, for example, 0V. For example, “3” can be determined when the input signal exceeds the determination threshold 602, and “2” can be determined between the determination thresholds 602 and 604.
　回路の非線形性があると、入力振幅の大きさによって利得が異なる。PAM4などの多値変調信号ではデータ遷移パターンにより図７のように信号振幅が小さくなり、EYE開口が狭くなる。特に０→３、３→０に遷移するデータパターン６０１では判定閾値６０２、判定閾値６０３との電圧差がなくなり、ノイズによりエラーを起こしやすくなる。このようにデータパターン依存でエラーが起こりやすくなってしまう。 If there is nonlinearity in the circuit, the gain varies depending on the input amplitude. In a multilevel modulation signal such as PAM4, the signal amplitude is reduced as shown in FIG. 7 due to the data transition pattern, and the EYE aperture is narrowed. In particular, in the data pattern 601 transitioning from 0 → 3, 3 → 0, there is no voltage difference between the determination threshold 602 and the determination threshold 603, and an error is likely to occur due to noise. In this way, errors tend to occur depending on the data pattern.
　しかし、図７を見てわかるように、判定閾値６０２の上側に対するマージン及び判定閾値６０３の下側に対するマージンは減っているが、判定閾値６０２の下側に対するマージン及び判定閾値６０３の上側に対するマージンは変化しない。そのため、判定閾値６０２と判定閾値６０３をマージンのあるほうに移動させることで、ノイズ耐性を高めることができると考えられる。典型例では、シンボルｘから最も離れたシンボルｙへ遷移する場合、シンボルｙを判定する判定閾値をシンボルｘに近づくように移動させることで、ノイズ耐性を高めることができると考えられる。 However, as can be seen from FIG. 7, the margin above the determination threshold 602 and the margin below the determination threshold 603 are reduced, but the margin below the determination threshold 602 and the margin above the determination threshold 603 are It does not change. For this reason, it is considered that noise tolerance can be increased by moving the determination threshold value 602 and the determination threshold value 603 toward the margin. In a typical example, when a transition is made from the symbol x to the furthest symbol y, it is considered that the noise tolerance can be increased by moving the determination threshold for determining the symbol y so as to approach the symbol x.
　なお、たとえば判定閾値６０２を下に移動させると、シンボル３をシンボル２と誤判定する可能性が減るが、シンボル２をシンボル３に誤判定する可能性が増えるので、判定閾値の移動量について配慮が必要となる。 For example, if the determination threshold value 602 is moved downward, the possibility of erroneous determination of symbol 3 as symbol 2 is reduced, but the possibility of erroneous determination of symbol 2 as symbol 3 is increased. Is required.
　以下、判定閾値を移動させることでノイズ耐性を高める構成を実現するための、第１の実施例の構成を示す。 Hereinafter, a configuration of the first embodiment for realizing a configuration in which noise tolerance is increased by moving the determination threshold will be described.
　図８に、判定閾値を移動させることでノイズ耐性を高める構成を実現する判定帰還型等化器３０７、４０８、４０９、４１４の一例を示す。簡便のため、これらの判定帰還型等化器に共通する構成を説明する際には、判定帰還型等化器３０７として引用することにする。 FIG. 8 shows an example of decision feedback equalizers 307, 408, 409, and 414 that realize a configuration in which noise tolerance is increased by moving the decision threshold. For the sake of simplicity, when a configuration common to these decision feedback equalizers is described, the decision feedback equalizer 307 is referred to.
　図８の判定帰還形等化器では、図６の構成に閾値加算器７０１を追加し、外部レジスタなどから閾値オフセット（OS）７０２を加えるように変更している。閾値加算器７０１は閾値オフセット７０２を判定閾値５２３に加え、判定器５０２の判定閾値を変更している。これにより、図７の判定閾値６０２と判定閾値６０３にオフセットが加わる。 In the decision feedback equalizer of FIG. 8, a threshold adder 701 is added to the configuration of FIG. 6, and a threshold offset (OS) 702 is added from an external register or the like. The threshold adder 701 adds the threshold offset 702 to the determination threshold 523 and changes the determination threshold of the determiner 502. Thereby, an offset is added to the determination threshold value 602 and the determination threshold value 603 of FIG.
　判定閾値６０２が＋ａＶ，判定閾値６０３が－ａＶ，判定閾値６０４が０Ｖである場合、オフセット（OS）が負の値であれば、判定閾値６０２が＋（ａ－OS）Ｖ，判定閾値６０３が－（ａ－OS）Ｖとなる。この結果、図７の矢印７００に示すように、判定閾値６０２は低くなり、判定閾値６０３は高くなり、回路の非線形性の影響を受けやすいデータパターン６０１に対してのマージンを増やすことができる。 When the determination threshold 602 is + aV, the determination threshold 603 is −aV, and the determination threshold 604 is 0V, if the offset (OS) is a negative value, the determination threshold 602 is + (a−OS) V and the determination threshold 603 is -(A-OS) V. As a result, as indicated by an arrow 700 in FIG. 7, the determination threshold 602 is lowered, the determination threshold 603 is increased, and the margin for the data pattern 601 that is easily affected by the nonlinearity of the circuit can be increased.
　図９に回路に非線形性がある条件で、閾値にオフセットを加えたときのBER（Bit Error Rate）のシミュレーション結果を示す。閾値に加えるオフセット量は最適な値がある。図９の例ではオフセットが－２０ｍＶであり、オフセットを加えないときに対して１桁程度BERが改善している。実施例１では、このようなシミュレーション結果や実験結果から、適切な閾値オフセット７０２を予め定めて、外部から判定帰還型等化器３０７に入力するように構成している。 Figure 9 shows the simulation result of BER (Bit シ ミ ュ レ ー シ ョ ン Error と き Rate) when an offset is added to the threshold under the condition that the circuit has nonlinearity. There is an optimum offset amount to be added to the threshold value. In the example of FIG. 9, the offset is −20 mV, and the BER is improved by about one digit compared to when no offset is added. In the first embodiment, an appropriate threshold value offset 702 is determined in advance from such simulation results and experimental results, and is input to the decision feedback equalizer 307 from the outside.
　図１０に第２の実施例を示す。第１の実施例では、予め定めた閾値オフセット７０２を判定帰還型等化器３０７に入力していた。一方、第２の実施例では、判定帰還型等化器３０７での信号補正量が大きいときに、閾値オフセットをかけるように自動調整を行なう。判定帰還型等化器３０７では、信号補正量が大きいときに判定誤りの影響が伝播しやすくエラーが生じやすい。このため、エラーが生じやすい状態を判定して、閾値オフセットをかける、あるいは、大きな閾値オフセットをかける。 FIG. 10 shows a second embodiment. In the first embodiment, a predetermined threshold offset 702 is input to the decision feedback equalizer 307. On the other hand, in the second embodiment, when the signal correction amount in the decision feedback equalizer 307 is large, automatic adjustment is performed so as to apply a threshold offset. In the decision feedback equalizer 307, when the signal correction amount is large, the influence of the decision error is easily propagated and an error is likely to occur. For this reason, an error-prone state is determined, and a threshold offset is applied or a large threshold offset is applied.
　このため、第２の実施例では判定帰還型等化器の１タップ目のタップ係数を元に、加える閾値オフセットを自動計算する。第１の実施例では固定値を与えていたのに対し、受けた損失に対して閾値オフセットを適応させ、条件に応じた閾値オフセットを与えることができる。第１の実施例では固定値しか与えられなかったため、最適値に対してマージンをとる必要があったが、第２の実施例では条件が変わっても最適な閾値オフセットを与えることができる。 Therefore, in the second embodiment, the threshold offset to be added is automatically calculated based on the tap coefficient of the first tap of the decision feedback equalizer. In the first embodiment, a fixed value is given. On the other hand, a threshold offset can be adapted to the received loss to give a threshold offset according to conditions. Since only a fixed value is given in the first embodiment, it is necessary to take a margin for the optimum value. However, in the second embodiment, an optimum threshold offset can be given even if the conditions change.
　判定帰還型等化器３０７のタップ係数計算機５１０で求めるタップ係数は、判定等化器の出力の振幅により絶対値の大小が決まる。閾値オフセットは振幅が大きいほど大きい値にするのが好ましいため、タップ係数により大小関係を判定できる。 The magnitude of the absolute value of the tap coefficient obtained by the tap coefficient calculator 510 of the decision feedback equalizer 307 is determined by the amplitude of the output of the decision equalizer. Since the threshold offset is preferably set to a larger value as the amplitude is larger, the magnitude relationship can be determined by the tap coefficient.
　さらに、判定帰還型等化器の１タップ目のタップ係数は、直前の信号に対する係数であり、１タップ目のタップ係数が大きいほど判定帰還型等化器による信号補正量が大きくなる。このため、１タップ目のタップ係数が大きいとき、前の判定結果にエラーがあった際に次の判定結果にエラーが起きる可能性が高くなる。 Furthermore, the tap coefficient of the first tap of the decision feedback equalizer is a coefficient for the immediately preceding signal, and the larger the tap coefficient of the first tap, the larger the signal correction amount by the decision feedback equalizer. For this reason, when the tap coefficient of the first tap is large, there is a high possibility that an error will occur in the next determination result when there is an error in the previous determination result.
　以上の理由により、タップ係数の絶対値に基づいて、閾値オフセットの有無あるいは大きさを定めることができる。特に、１タップ目のタップ係数に基づいて閾値オフセットを定めることにより、前記のようなエラーが起きやすい条件で閾値オフセットを加え、エラーの改善を図ることができる。 For the above reasons, the presence or absence of the threshold offset or the magnitude can be determined based on the absolute value of the tap coefficient. In particular, by setting the threshold offset based on the tap coefficient of the first tap, it is possible to improve the error by adding the threshold offset under the condition that the error is likely to occur.
　図１０のように、第２の実施例は閾値オフセットをタップ係数から判定する閾値オフセット判定機９０１を有する。タップ係数５２５の入力に対し、閾値オフセット判定機９０１は内部の関数に従って閾値オフセット９０２を出力する。閾値オフセット９０２は閾値加算器７０１において判定閾値５２３に加算され、加算結果は判定器５０２の判定閾値として使われる。 As shown in FIG. 10, the second embodiment includes a threshold offset determiner 901 that determines a threshold offset from a tap coefficient. In response to the input of the tap coefficient 525, the threshold offset determiner 901 outputs a threshold offset 902 according to an internal function. The threshold offset 902 is added to the determination threshold 523 in the threshold adder 701, and the addition result is used as the determination threshold of the determiner 502.
　閾値オフセット判定機９０１の内部関数は、一番簡単な例としてはタップ係数５２５の下位ビットを捨てる小数点以下切捨てが挙げられる。また、１次関数や２次関数などといった関数と小数点以下切捨てを組み合わせてもよい。また、タップ係数５２５の絶対値が、ある一定の値以上でないと閾値オフセットを加えない、あるいは出力しないようにすることもできる。また、タップ係数に応じて、閾値オフセット判定機９０１の出力に傾斜もつけられるようにする方法もある。 The simplest example of the internal function of the threshold offset determiner 901 is to truncate after the decimal point to discard the lower bits of the tap coefficient 525. Moreover, you may combine functions, such as a linear function and a quadratic function, and truncation after a decimal point. Further, it is possible to prevent the threshold offset from being added or output unless the absolute value of the tap coefficient 525 is a certain value or more. There is also a method in which the output of the threshold offset determiner 901 is also inclined according to the tap coefficient.
　図１１に第３の実施例を示す。第３の実施例では第２の実施例に対し、閾値オフセット判定機９０１へ関数選択信号（SL)１００１が入力されている。これにより、閾値オフセット判定機９０１の内部関数を、判定帰還型等化器外部のレジスタ等から選択可能としている。 FIG. 11 shows a third embodiment. In the third embodiment, a function selection signal (SL) 1001 is input to the threshold value offset determiner 901 compared to the second embodiment. As a result, the internal function of the threshold offset determiner 901 can be selected from a register or the like outside the decision feedback equalizer.
　閾値オフセット判定機９０１内のメモリに、選択可能な複数の関数を準備しておき、関数選択信号１００１を用いることにより、タップ係数から閾値オフセットを計算する式をLSI製造後に変更可能となる。これにより、設計段階で関数のパラメータに不具合があったとしても再設計することなく、評価を元に有効な関数を選ぶことができる。そのため、設計期間を短縮でき、コスト低減につながる。 By preparing a plurality of selectable functions in the memory in the threshold offset determiner 901 and using the function selection signal 1001, the formula for calculating the threshold offset from the tap coefficient can be changed after the LSI is manufactured. This makes it possible to select an effective function based on the evaluation without redesign even if there is a defect in the function parameters at the design stage. Therefore, the design period can be shortened, leading to cost reduction.
　図１２に第４の実施例を示す。図１０の第２の実施例に対しアナログデジタル変換機（ADC：Analog Digital Converter）１１０１が追加され、フリップフロップ５０３が削除されている。 FIG. 12 shows a fourth embodiment. An analog-to-digital converter (ADC) 1101 is added to the second embodiment of FIG. 10, and the flip-flop 503 is deleted.
　第４の実施例において判定帰還型等化器は、ADC１１０１、加算器５０１、判定器５０２、シフトレジスタ５０４、タップ係数掛け算器５０５、タップ係数掛け算器５０６、タップ係数掛け算器５０７、タップ係数掛け算器５０８、タップ係数掛け算器５０９、タップ係数計算機５１０、判定閾値計算機５１１、閾値オフセット判定機９０１で構成される。 In the fourth embodiment, the decision feedback equalizer includes an ADC 1101, an adder 501, a determiner 502, a shift register 504, a tap coefficient multiplier 505, a tap coefficient multiplier 506, a tap coefficient multiplier 507, and a tap coefficient multiplier. 508, a tap coefficient multiplier 509, a tap coefficient calculator 510, a determination threshold calculator 511, and a threshold offset determiner 901.
　ADC１１０１は入力信号５２１をクロック５２２のエッジのタイミングでサンプルホールドし、アナログ信号をデジタル符号に変換する。 The ADC 1101 samples and holds the input signal 521 at the timing of the edge of the clock 522, and converts the analog signal into a digital code.
　加算器５０１はADC出力信号１１０２にタップ係数掛け算器５０５、５０６、５０７、５０８、５０９の出力を加算し、ADC出力信号１１０２の符号間干渉成分を打ち消す。 The adder 501 adds the outputs of the tap coefficient multipliers 505, 506, 507, 508, and 509 to the ADC output signal 1102, and cancels the intersymbol interference component of the ADC output signal 1102.
　判定器５０２は加算器５０１の出力と判定閾値５２３に閾値オフセット９０２が閾値加算器７０１において加算された結果とを比較し、論理値を判定する。例えばPAM4用判定器であれば０、１、２、３のいずれかに入力値を判定する。 The determiner 502 compares the output of the adder 501 with the result obtained by adding the threshold offset 902 to the determination threshold 523 in the threshold adder 701, and determines the logical value. For example, in the case of a PAM4 determiner, the input value is determined as 0, 1, 2, or 3.
　判定器５０２の出力は判定等化器の出力である判定帰還型等化器出力信号５２４として出力される一方、タップ係数掛け算器５０５、シフトレジスタ５０４に入力される。シフトレジスタ５０４は判定帰還型等化器出力信号５２４を取り込み、クロック５２２の周期ごとに時間を遅らせたデータを出力する。１クロック遅らせた信号は２タップ目のタップ係数掛け算器５０６に入力され、２クロック遅らせた信号は３タップ目のタップ係数掛け算器５０７に入力され、３クロック遅らせた信号は４タップ目のタップ係数掛け算器５０８に入力され、４クロック遅らせた信号は５タップ目のタップ係数掛け算器５０８に入力される。 The output of the decision unit 502 is outputted as a decision feedback equalizer output signal 524 which is the output of the decision equalizer, while being inputted to the tap coefficient multiplier 505 and the shift register 504. The shift register 504 takes in the decision feedback equalizer output signal 524 and outputs data delayed in time for each cycle of the clock 522. The signal delayed by one clock is input to the tap coefficient multiplier 506 of the second tap, the signal delayed by two clocks is input to the tap coefficient multiplier 507 of the third tap, and the signal delayed by three clocks is the tap coefficient of the fourth tap. A signal input to the multiplier 508 and delayed by 4 clocks is input to the tap coefficient multiplier 508 of the fifth tap.
　タップ係数掛け算器５０５、５０６、５０７、５０８、５０９は、それぞれ入力されたデータにタップ係数を掛け、それらの結果を加算器５０１に出力する。タップ係数掛け算器５０５、５０６、５０７、５０８、５０９のそれぞれのタップ係数は、タップ係数計算機５１０で加算器５０１の出力と判定閾値計算機５１１からの判定閾値５２３及び判定帰還型等化器出力信号５２４を元に計算される。判定閾値５２３は判定閾値計算機５１１において、加算器５０１出力と判定帰還型等化器出力信号５２４を元に計算される。閾値オフセット判定機９０１はタップ係数５２５を入力され、閾値オフセット９０２を内部関数に従って計算する。 The tap coefficient multipliers 505, 506, 507, 508, and 509 multiply the input data by the tap coefficients and output the results to the adder 501. The tap coefficients of the tap coefficient multipliers 505, 506, 507, 508, and 509 are output from the adder 501 by the tap coefficient calculator 510, the determination threshold value 523 from the determination threshold calculator 511, and the determination feedback equalizer output signal 524, respectively. Calculated based on The determination threshold 523 is calculated by the determination threshold calculator 511 based on the output of the adder 501 and the determination feedback equalizer output signal 524. The threshold offset determiner 901 receives the tap coefficient 525 and calculates the threshold offset 902 according to the internal function.
　実施例４ではADC１１０１を判定等化器内に持つことにより、ADC出力の後をすべてデジタル信号で扱うことができ、内部ブロックの動作をソフトウェアで変更しやすくなる。このように、汎用性を高めることができる構成である。 In the fourth embodiment, by having the ADC 1101 in the decision equalizer, everything after the ADC output can be handled as a digital signal, and the operation of the internal block can be easily changed by software. Thus, it is the structure which can improve versatility.
　以上詳細に説明した実施例によれば、PAM（Pulse Amplitude Modulation）信号における多値信号のデータ遷移により生じるデータ誤りを補正して、EYE幅を拡大する電気信号伝送装置を提供することができる。 According to the embodiment described in detail above, it is possible to provide an electric signal transmission device that corrects a data error caused by data transition of a multilevel signal in a PAM (Pulse Amplitude Modulation) signal and expands the EYE width.
　本発明は上記した実施形態に限定されるものではなく、様々な変形例が含まれる。例えば、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることが可能である。また、各実施例の構成の一部について、他の実施例の構成の追加・削除・置換をすることが可能である。 The present invention is not limited to the above-described embodiment, and includes various modifications. For example, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace the configurations of other embodiments with respect to a part of the configurations of the embodiments.
　高速有線伝送向け受信機およびそれに使用可能な半導体集積回路に利用可能である。 It can be used for receivers for high-speed wired transmission and semiconductor integrated circuits that can be used for them.
１０２、１０７、２０２、２０８　信号伝送用ASIC
２０３　レート変換用ASIC
３０１、４０２　信号処理部
３０２　送信部
３０３　受信部
３０４、４１１、４１６、４１７　マルチプレクサ
３０５、４１２、４１８，４１９　フィードフォワード等化器
３０６、４０６、４０７、４１３　線形等化器
３０７，４０８，４０９，４１４　判定帰還型等化器
３０８、４１０、４１５　クロック及びデータ再生器
５０１　加算器
５０２　判定器
５０３　フリップフロップ
５０４　シフトレジスタ
５０５，５０６，５０７，５０８，５０９　タップ係数掛け算器
５１０　タップ係数計算機
５１１　判定閾値計算機 102, 107, 202, 208 ASIC for signal transmission
203 ASIC for rate conversion
301, 402 Signal processor 302 Transmitter 303 Receiver 304, 411, 416, 417 Multiplexer 305, 412, 418, 419 Feed forward equalizer 306, 406, 407, 413 Linear equalizer 307, 408, 409, 414 Decision feedback equalizers 308, 410, 415 Clock and data regenerator 501 Adder 502 Determinator 503 Flip-flop 504 Shift register 505, 506, 507, 508, 509 Tap coefficient multiplier 510 Tap coefficient calculator 511 Determination threshold calculator

Claims (15)

  1. 　入力信号に補正値を加える第１の加算器を有し、
    　前記第１の加算器の出力を第１の判定閾値に従って論理値に判定する判定器を有し、
    　前記判定器の出力をクロックのタイミングでサンプルホールドするフリップフロップを有し、
    　前記フリップフロップの出力と前記クロックを受け取り前記クロックの周期ごとに前記フリップフロップの出力を遅延させるシフトレジスタを有し、
    　前記フリップフロップの出力と前記シフトレジスタの出力とに補正係数を掛けて前記補正値を出力する掛け算器を有し、
    　前記第１の加算器の出力と前記フリップフロップの出力とから前記クロックのタイミングごとに前記補正係数を計算する補正係数計算機を有し、
    　前記第１の加算器の出力と前記フリップフロップの出力とから前記クロックのタイミングごとに第２の判定閾値を計算する判定閾値計算機を有し、
    　前記第２の判定閾値に閾値オフセットを加えて前記第１の判定閾値を出力する第２の加算器を有することを特徴とする判定帰還型等化器。     A first adder for adding a correction value to the input signal;
    A determinator for determining an output of the first adder to a logical value according to a first determination threshold;
    A flip-flop that samples and holds the output of the determination unit at a clock timing;
    A shift register that receives the output of the flip-flop and the clock and delays the output of the flip-flop every period of the clock;
    A multiplier for multiplying the output of the flip-flop and the output of the shift register by a correction coefficient and outputting the correction value;
    A correction coefficient calculator for calculating the correction coefficient for each timing of the clock from the output of the first adder and the output of the flip-flop;
    A determination threshold calculator for calculating a second determination threshold for each timing of the clock from the output of the first adder and the output of the flip-flop;
    A decision feedback equalizer comprising a second adder that adds a threshold offset to the second decision threshold and outputs the first decision threshold.
  2. 　前記補正係数を用いて前記閾値オフセットを計算する閾値オフセット判定機を有することを特徴とする、
    　請求項１記載の判定帰還型等化器。     A threshold offset determinator that calculates the threshold offset using the correction coefficient is provided.
    The decision feedback equalizer according to claim 1.
  3. 　前記閾値オフセット判定機は、内部関数に従って前記閾値オフセットを計算するものであり、複数の内部関数を内蔵するとともに選択信号の入力を受け付け、前記選択信号により閾値オフセットを計算するための内部関数を選択可能であることを特徴とする、
    　請求項２記載の判定帰還型等化器。     The threshold offset determiner calculates the threshold offset according to an internal function. The threshold offset determiner includes a plurality of internal functions, receives an input of a selection signal, and selects an internal function for calculating the threshold offset by the selection signal. Characterized by being possible,
    The decision feedback equalizer according to claim 2.
  4. 　前記入力信号を前記クロックのタイミングでサンプルホールドしデジタル信号に変換するアナログデジタル変換機を有し、
    　前記第１の加算器および前記判定器は、前記デジタル信号を処理することを特徴とする、
    　請求項１記載の判定帰還型等化器。     An analog-digital converter that samples and holds the input signal at the timing of the clock and converts it into a digital signal,
    The first adder and the determiner process the digital signal,
    The decision feedback equalizer according to claim 1.
  5. 　前記入力信号は、多値のシンボルを含む多値信号であることを特徴とする、
    　請求項１記載の判定帰還型等化器。     The input signal is a multilevel signal including multilevel symbols,
    The decision feedback equalizer according to claim 1.
  6. 　前記閾値オフセットは、前記入力信号がシンボルｘから最も離れたシンボルｙへ遷移する場合、シンボルｙを判定する前記第２の判定閾値をシンボルｘに近づくように移動させて前記第１の判定閾値とすることを特徴とする、
    　請求項５記載の判定帰還型等化器。     When the input signal transitions to the symbol y that is farthest from the symbol x, the threshold offset moves the second determination threshold for determining the symbol y so as to approach the symbol x and It is characterized by
    6. A decision feedback equalizer according to claim 5.
  7. 　前記掛け算器は、
    　前記フリップフロップの出力を入力とする第１の掛け算器と、前記シフトレジスタの出力を入力とする第２の掛け算器を備え、
    　前記補正係数計算機は、
    　前記第１の掛け算器に入力する第１の補正係数と、前記第２の掛け算器に入力する第２の補正係数を出力し、
    　前記閾値オフセット判定機は、
    　前記第１の補正係数を用いて前記閾値オフセットを計算する、
    　請求項２記載の判定帰還型等化器。     The multiplier is
    A first multiplier that receives the output of the flip-flop, and a second multiplier that receives the output of the shift register;
    The correction coefficient calculator is
    Outputting a first correction coefficient to be input to the first multiplier and a second correction coefficient to be input to the second multiplier;
    The threshold offset determiner is
    Calculating the threshold offset using the first correction factor;
    The decision feedback equalizer according to claim 2.
  8. 　前記閾値オフセット判定機は、前記補正係数の下位ビットを捨てる小数点以下切捨てを行なう、
    　請求項２記載の判定帰還型等化器。     The threshold offset determiner performs rounding down to the nearest decimal place to discard the lower bits of the correction coefficient.
    The decision feedback equalizer according to claim 2.
  9. 　前記閾値オフセット判定機は、前記補正係数の絶対値が所定値以上でないと閾値オフセットを出力しないようにする、
    　請求項２記載の判定帰還型等化器。     The threshold offset determiner does not output a threshold offset unless the absolute value of the correction coefficient is equal to or greater than a predetermined value;
    The decision feedback equalizer according to claim 2.
  10. 　受信信号を受け取り、波形等化および信号増幅を行なう線形等化器と、
    　前記線形等化器の出力を入力信号とする請求項１記載の判定帰還型等化器と、
    　を備える受信機。     A linear equalizer that receives a received signal and performs waveform equalization and signal amplification;
    The decision feedback equalizer according to claim 1, wherein an output of the linear equalizer is an input signal;
    Receiver with.
  11. 　前記受信信号は、多値のシンボルを含む多値信号である、
    　請求項１０記載の受信機。     The received signal is a multilevel signal including multilevel symbols.
    The receiver according to claim 10.
  12. 　前記線形等化器は、非線形特性を有する、
    　請求項１０記載の受信機。     The linear equalizer has non-linear characteristics;
    The receiver according to claim 10.
  13. 　前記線形等化器は、差動増幅器構成である、
    　請求項１０記載の受信機。     The linear equalizer is a differential amplifier configuration;
    The receiver according to claim 10.
  14. 　前記補正係数を用いて前記閾値オフセットを計算する閾値オフセット判定機を有することを特徴とする、
    　請求項１０記載の受信機。     A threshold offset determinator that calculates the threshold offset using the correction coefficient is provided.
    The receiver according to claim 10.
  15. 　前記閾値オフセット判定機は、前記フリップフロップの出力に掛けられる前記補正係数を用いて前記閾値オフセットを計算する、
    　請求項１４記載の受信機。     The threshold offset determiner calculates the threshold offset using the correction factor multiplied by the output of the flip-flop;
    The receiver according to claim 14.
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