KR101671627B1 - Method for graphene-assisted chemical etching of silicon - Google Patents

Method for graphene-assisted chemical etching of silicon Download PDF

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KR101671627B1
KR101671627B1 KR1020150063142A KR20150063142A KR101671627B1 KR 101671627 B1 KR101671627 B1 KR 101671627B1 KR 1020150063142 A KR1020150063142 A KR 1020150063142A KR 20150063142 A KR20150063142 A KR 20150063142A KR 101671627 B1 KR101671627 B1 KR 101671627B1
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graphene
silicon
nanostructure
layer
catalyst
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KR1020150063142A
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Korean (ko)
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최석호
김정길
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경희대학교 산학협력단
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Priority to PCT/KR2015/005501 priority patent/WO2016178452A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1606—Graphene

Abstract

Provided is a method for chemically etching silicon by graphene as a catalyst which uses graphene, not jewelry, as a catalyst to reduce economical costs and which does not use a strongly acid solution having high toxicity to be relatively safe.

Description

METHOD FOR GRAPHENE-ASSISTED CHEMICAL ETCHING OF SILICON BACKGROUND OF THE INVENTION < RTI ID = 0.0 > [0001] <

The present invention relates to a method of chemically etching silicon with graphene catalyst capable of producing a silicon nanostructure through a chemical etching method using a graphene nanostructure as a catalyst.

In recent years, metal-assisted chemical etching of semiconductors (MaCE) catalyzed by noble metals such as gold, silver, platinum, palladium, and copper has been used to fabricate semiconductor nanostructures.

In particular, metal-catalyzed chemical etching methods have produced remarkable results in the fabrication of silicon nanostructures such as silicon nanowires / nano holes and porous silicon.

Recent research has shown that nanostructures of structurally controlled silicon nanowires and gallium arsenide have been fabricated through metal-catalyzed chemical etching. Silicon nanowires and porous silicon fabricated through metal-catalyzed chemical etching have been successfully applied as base materials for advanced devices such as solar cells, photodetectors, and molecular sensors.

However, despite the above-mentioned excellent results, the metal-based chemical etching method requires only a precious metal as a catalyst, and the precious metal is not only economically expensive but also difficult to remove.

In addition, the conventional metal-based chemical etching method has a problem of using a highly toxic and strongly acidic solution such as aqua regia mixed with nitric acid and hydrochloric acid in order to remove the noble metal during the etching process.

 Recently, graphene has attracted much attention as a new material for the future due to its unique and excellent physical properties. Graffin not only has high electrical conductivity but also has high optical performance, so it can be used as a new material in next generation display fields such as flexible display and touch panel, energy business such as solar cell, smart window, RFID, etc. .

Also, graphene can be manufactured at low cost, and is made of only carbon, so that it can be easily removed through oxygen plasma treatment without using a toxic substance.

U.S. Published Patent Application No. 2012/0301953 (November 29, 2012), "graphene nanomesh and method of making the same" Korean Patent Laid-Open Publication No. 2013-0050167 (2013.05.15), "Method for manufacturing graphene nano-mesh, graphene nano-mesh, and electronic device using graphene nano-

Zhipeng Huang, Nadine Geyer, Peter Werner, Johannes de Boor, and Ulrich Gosele, Adv. Mater. 2011, 23, 285-308

The present invention provides a method for producing various semiconductor nanostructures through chemical etching of silicon with graphene as a catalyst.

The present invention also provides a method of chemically etching a semiconductor using graphene as a catalyst, which can reduce an economical cost burden by using graphen instead of a noble metal as a catalyst.

It is another object of the present invention to provide a method of chemically etching a semiconductor using graphene as a catalyst capable of removing a catalyst through an oxygen plasma treatment without using a strongly acidic solution having high toxicity during the etching process.

A method of chemically etching silicon with graphene according to an embodiment includes: stacking a large area graphene layer on a silicon layer; Forming a nanotemplate on the stacked graphene layer and forming a graphene nanostructure using the formed nanotemplate as a pattern mask; And forming a silicon nanostructure through Graphene-assisted chemical etching of the silicon layer using the formed graphene nanostructure as a catalyst.

In the step of forming the graphene nanostructure, the graphene nanostructure may be formed by performing an oxygen plasma treatment on the formed nanotemplate and etching the exposed graphene layer through the nanotemplate.

In the step of forming the silicon nanostructure, the silicon nanostructure may be formed by removing the nanotemplate, etching the silicon layer in an etch solution environment using the formed graphene nanostructure as a catalyst.

The step of forming the graphene nanostructure comprises: forming an ordered nanosphere array on the stacked graphene layer using nanosphere lithography; Performing oxygen plasma treatment on the formed nanospher array to form a graphene nanodos by etching the exposed graphene layer through the nanosphere array; And removing the nanosphere array.

The step of forming the silicon nanostructure may be performed by etching the silicon layer using the formed graphene nanodata as a catalyst in an etching solution environment containing hydrofluoric acid (HF) and hydrogen peroxide (H 2 O 2 ) .

The step of forming the graphene nanostructure comprises: preparing an AAO membrane; Depositing a metal thin film on the prepared anodized aluminum membrane; Transferring the patterned metal thin film formed by selectively removing the anodized aluminum membrane onto the stacked graphene layer; Performing an oxygen plasma treatment on the transferred patterned metal thin film to form a graphene mesh by etching the exposed graphene layer through the patterned metal thin film; And selectively removing the patterned metal foil.

In the step of forming the silicon nanostructure, the silicon nanostructure may be formed by etching the silicon layer using the formed graphene mesh as a catalyst in an etching solution environment containing hydrofluoric acid and hydrogen peroxide.

The silicon nanostructure may be any one of a silicon nanowire, a silicon cone array, a silicon hole array, and a porous silicon.

According to the present invention, various semiconductor nanostructures can be prepared through chemical etching of silicon with graphene as a catalyst.

Further, according to the present invention, it is possible to reduce the economical cost burden by using graphene rather than a noble metal as a catalyst.

In addition, according to the present invention, it is possible to provide a method of chemically etching a semiconductor using graphene as a catalyst capable of removing a catalyst through an oxygen plasma treatment without using a strongly acidic solution having high toxicity during the etching process.

1 is a flowchart illustrating a method of chemically etching silicon using graphene as a catalyst according to an embodiment of the present invention.
FIGS. 2A to 2D illustrate a process of manufacturing a graphene nanostructure using nano-sprite lithography according to an embodiment of the present invention and a method of chemically etching silicon using the graphene nanostructure as a catalyst. FIG.
FIGS. 3A through 3F illustrate a process of manufacturing a graphene nanostructure using an anodized aluminum membrane according to another embodiment of the present invention, and a method of chemically etching silicon using the graphene nanostructure as a catalyst. FIG.
FIGS. 4A to 4C illustrate examples of a silicon nano structure fabricated through a chemical etching process using a graphene catalyst according to an embodiment of the present invention.
5A and 5B are scanning electron microscopy (SEM) images before the treatment of an oxygen plasma for manufacturing a graphene nanostructure according to an embodiment of the present invention.
6A and 6B are SEM (scanning electron microscopy) images of a graphene nanostructure fabricated according to an embodiment of the present invention.
7A to 7C are SEM images of a silicon nanostructure fabricated by a chemical etching method using silicon as a catalyst according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and accompanying drawings, but the present invention is not limited to or limited by the embodiments.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, when a device is referred to as "directly on" or "directly above ", it does not intervene another device or layer in the middle.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figure, an element described as " below or beneath "of another element may be placed" above "another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, in which case spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terminology used herein is a term used for appropriately expressing an embodiment of the present invention, which may vary depending on the user, the intent of the operator, or the practice of the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

1 is a flowchart illustrating a method of chemically etching silicon using graphene as a catalyst according to an embodiment of the present invention.

Referring to FIG. 1, a method of chemically etching silicon with graphene according to an embodiment of the present invention includes stacking a graphene layer on a silicon layer in a large area in step 110.

Step 110 may be a step of growing the graphene using chemical vapor deposition (CVD) and transferring the graphene grown on the large area onto the silicon substrate.

In step 120, a nanotemplate is formed on the stacked graphene layer, and a graphene nanostructure is formed using the formed nanotemplate as a pattern mask.

For example, step 120 may be a step of forming a graphene nanostructure by performing an oxygen plasma treatment on the formed nanotemplate to etch the exposed graphene layer through the nanotemplate.

According to an embodiment, step 120 includes forming an ordered nanospheres array fabricated using nanosphere lithography on a graphene layer, performing an oxygen plasma treatment on the formed nanospher array, Etching the exposed graphene layer, and then removing the nanosphere array to form the graphene nanostructure.

In this case, the formed graphene nanostructure may be graphene nanodots.

Also, according to another embodiment, step 120 may include depositing a metal thin film on an anodized aluminum oxide (AAO), selectively removing an anodized aluminum membrane, depositing a patterned metal After the thin film is transferred onto the stacked graphene layer, oxygen plasma treatment is performed to etch the exposed graphene layer through the patterned metal thin film, and then the patterned metal thin film is selectively removed to remove the graphene nanostructure To form a second layer.

In this case, the formed graphene nanostructure may be a graphene mesh.

The silicon nanostructure is formed by Graphene-assisted chemical etching of the silicon layer using the graphene nanostructure formed in Step 130 as a catalyst.

Step 130 can remove the nanotemplate, form a silicon nanostructure using the formed graphene nanostructure as a catalyst, and etch the silicon layer in an etch solution environment.

The silicon nanostructure may be any one of a silicon nanowire, a silicon cone array, a silicon hole array, and a porous silicon.

FIGS. 2A to 2D illustrate a process of manufacturing a graphene nanostructure using nano-sprite lithography according to an embodiment of the present invention and a method of chemically etching silicon using the graphene nanostructure as a catalyst. FIG.

Referring to FIG. 2A, in a method of chemically etching silicon using graphene as a catalyst according to an embodiment of the present invention, a graphene layer 220 is stacked on a silicon layer 210 in a large area.

The graphene layer 220 can be grown using chemical vapor deposition (CVD), and the graphene layer 220 grown to a large area can be transferred onto the silicon layer 210.

To explain this more specifically, In the production of graphene by chemical vapor deposition, copper (or nickel) to be used as a catalyst layer is deposited on a substrate and reacted with a mixed gas of methane and hydrogen at a high temperature to allow an appropriate amount of carbon to be dissolved or adsorbed in the catalyst layer, The carbon atoms contained in the catalyst layer are crystallized on the surface to form a graphene crystal structure on the metal.

Thereafter, the catalyst layer is removed from the synthesized graphene thin film to separate graphene from the substrate.

Thereafter, PMMA mixed with poly (methyl methacrylate) and benzene was spin-coated on the synthesized graphene. PMMA was coated on the graphene by using a solution of ammonium persulfate (PMMA) The graphene can be gripped and fixed when it is removed.

Thereafter, the copper foil is removed from the ammonium persulfate solution, the ammonium persulfate solution remaining on the graphene is washed with DI water, and the washed graphene is transferred onto the silicon layer 210 to form a graphene layer 220 may be formed.

Next, the bonding force between the silicon layer 210 and the graphene layer 220 can be increased through heat treatment after transferring the graphene layer 220 to the silicon layer 210. After the heat treatment, acetone is used to remove the PMMA present on the graphene, and the PMMA residue remaining on the graphene surface may be removed by heat treatment with a rapid thermal processor to finally form the graphene layer 220.

Referring to FIG. 2B, a method of chemically etching silicon with graphene as a catalyst according to an embodiment of the present invention includes the steps of: (a) forming a silicon layer 210 on a graphene layer 220 by using nano- ordered nanosphere array 230 is formed.

For example, polystyrene beads (PS beads) having a diameter of 100 to 1000 nm are sprayed on a water layer to form a nanosphere array using nano-sphere lithography, and sodium dodecyl sulfate (NaDS) Is sprayed on the water.

The polystyrene beads are bonded to each other with a structure having a hexagonal arrangement, and the polystyrene bead array 230 can be manufactured.

The polystyrene bead array 230 manufactured as described above is transferred onto the graphene layer 220 as shown in FIG.

Referring to FIGS. 2c and 2d, a method of chemically etching silicon with graphene as a catalyst according to an embodiment of the present invention includes the steps of: performing oxygen plasma treatment on a formed nano-sphere array 230; The exposed graphene layer 220 is etched and the nano-sphere array 230 is removed to form a graphene nanodos 310 graphene nanostructure.

More specifically, as shown in FIG. 2C, when the nano-sphere array 230 is subjected to the oxygen plasma treatment, the diameter of the nano-spheres of the nano-sphere array is reduced, and at the same time, the exposed graphene layer 220 is removed.

Then, as shown in FIG. 2D, the nano-sphere array 230 is removed to form a graphene nanodot 310 in the form of a graphen nanodot 310. For example, when the nanosphere array 230 is a polystyrene bead array, it may be treated with acetone to selectively remove polystyrene to form a graphene nanodot 310.

Thereafter, the silicon nanostructure can be fabricated through Graphene-assisted chemical etching of the silicon layer 210 using the formed graphene nanostructure (graphen nanodot 310) as a catalyst.

FIGS. 3A through 3F illustrate a process of manufacturing a graphene nanostructure using an anodized aluminum membrane according to another embodiment of the present invention, and a method of chemically etching silicon using the graphene nanostructure as a catalyst. FIG.

3A and 3B, a method of chemically etching silicon using graphene as a catalyst according to another embodiment of the present invention includes preparing an anodized aluminum membrane (AAO membrane) 240, preparing an anodized aluminum membrane 240 The metal thin film 250 is deposited.

Referring to FIGS. 3c and 3d, a method of chemically etching silicon using graphene as a catalyst according to another embodiment of the present invention includes selectively removing an anodized aluminum membrane 240, The thin film 250 may be transferred onto the stacked graphene layer 220 on the silicon layer 210.

For example, a gold thin film may be deposited to a thickness of 50 nm on the surface of the aluminum membrane 240 having a hexagonal channel, and the aluminum membrane 240 may be selectively removed by floating on a solution such as KOH or NaOH. The gold thin film 250 having the same hole arrangement shape as that of the gold thin film 240 can be manufactured. Then, the fabricated gold thin film 250 is transferred onto the graphene layer 220.

Further, a process of forming the graphene layer 220 stacked on the silicon layer 210 is the same as that described above with reference to FIG. 2A, and a detailed description thereof will be omitted.

Referring to FIGS. 3E and 3F, a method of chemically etching silicon with graphene as a catalyst according to another embodiment of the present invention includes performing oxygen plasma treatment on a patterned metal thin film 250 transferred as shown in FIG. 3E The patterned metal foil 250 is selectively removed after the exposed graphene layer 220 is etched through the patterned metal foil 250. As shown in FIG. 3F, a graphene mesh , 320 can be formed.

Thereafter, the silicon nanostructure can be formed by Graphene-assisted chemical etching of the silicon layer 210 using the formed graphene nanostructure, the graphene mesh 320, as a catalyst.

Hereinafter, a silicon nanostructure fabricated through a chemical etching process using a graphene nanostructure as a catalyst will be described with reference to FIGS. 4A to 4C.

FIGS. 4A to 4C illustrate examples of a silicon nano structure fabricated through a chemical etching process using a graphene catalyst according to an embodiment of the present invention.

Referring to FIGS. 4A to 4C, a silicon nanowire, a silicon cone arrays, a silicon hole array, and a silicon nitride film are formed through a chemical etching process of a graphene-based silicon according to an embodiment of the present invention Si hole arrays) and porous silicon (Porous Si).

According to the embodiment, when the graphene mesh 320 formed on the n-type silicon layer 210 of FIG. 3F is put in a mixed etching solution of hydrofluoric acid and hydrogen peroxide having a volume ratio of 10: 0.5 at 50 degrees or more, The portion covered by pin mesh 320 is etched and the remaining silicon in the hole of graphene mesh 320 can be fabricated to have the appearance of a nanowire or cone array as shown in FIG.

According to another embodiment, when the graphene nanodot 310 formed on the n-type silicon layer 210 of FIG. 2D is placed in a mixed etching solution of hydrofluoric acid and hydrogen peroxide for several tens minutes, graphene nanodot 310 And selectively etched to form a silicon hole array as shown in FIG. 4B.

According to another embodiment, when the graphene mesh 320 formed on the n-type silicon layer 210 of FIG. 3F is placed in a mixed etching solution of hydrofluoric acid and hydrogen peroxide solution having a volume ratio of 1: 1 for several minutes, So that the porous silicon as shown in Fig. 4C can be manufactured.

The etching time in the mixed etching solution of hydrofluoric acid and hydrogen peroxide for preparing the silicon nanostructure may be 30 minutes or more and the degree of etching of the silicon layer 210 is increased as the etching time is increased, Conical arrays, and silicon hole arrays with deeper holes.

5A and 5B are scanning electron microscopy (SEM) images before the treatment of an oxygen plasma for manufacturing a graphene nanostructure according to an embodiment of the present invention.

5A is a scanning electron microscope image of a polystyrene bead array transferred onto a graphene layer as shown in FIG. 2B. Referring to FIG. 5A, a polystyrene bead array is transferred onto a graphene layer in the form of a hexagonal array .

FIG. 5B is a TEM image of a gold (Au) thin film having a hole arrangement obtained from anodic aluminum oxide (AAO) as shown in FIG. 3 transferred onto a graphene layer. Referring to FIG. 5B, It can be confirmed that the gold thin film as the thin film has a hexagonal array of holes and is well transferred onto the graphene layer.

6A and 6B are SEM (scanning electron microscopy) images of a graphene nanostructure fabricated according to an embodiment of the present invention.

6A is a scanning electron microscope image of graphene nanodot on a silicon layer after treating the polystyrene bead array transferred on the graphene layer of FIG. 5A with oxygen plasma at 50 W for 1 minute and selectively removing polystyrene with acetone As a result, it can be confirmed that graphene nanodots are well formed on the silicon layer.

FIG. 6B is a view illustrating a process of treating the gold thin film transferred on the graphene layer in FIG. 5B by treating oxygen plasma at 50 W for 1 minute, selectively removing the gold thin film using a tape, As an electron microscope image, it can be seen that the graphene mesh is well formed on the silicon layer.

7A to 7C are SEM images of a silicon nanostructure fabricated by a chemical etching method using silicon as a catalyst according to an embodiment of the present invention.

FIG. 7A is a scanning electron microscope image of a silicon pillars having a diameter of about 50 nm. It can be seen that the arrangement of pillars formed on the surface of a flat silicon layer can be clearly distinguished, and the surface is rather smooth and rather rough .

FIG. 7B is a scanning electron microscope image for a silicon hole array with shallow hole arrays, FIG. 7C is a scanning electron microscope image for porous silicon having a size of less than a few nm formed on the surface of a silicon layer, According to the chemical etching method of silicon with graphene as a catalyst, various types of silicon nanostructures can be manufactured according to the etching process conditions.

As described above, the method of chemical etching of silicon using graphene according to an embodiment of the present invention can chemically etch not only silicon but also various semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP).

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (8)

Stacking a large area graphene layer on the silicon layer;
Forming a nanotemplate on the stacked graphene layer and forming a graphene nanostructure using the formed nanotemplate as a pattern mask; And
And forming a silicon nanostructure by Graphene-assisted chemical etching of the silicon layer using the formed graphene nanostructure as a catalyst,
Silicon nanowires, silicon cone arrays, and silicon hole arrays (silicon nanowires) are formed based on the chemical etching treatment conditions in a mixed etching solution environment containing hydrofluoric acid (HF) and hydrogen peroxide (H 2 O 2 ) Si hole arrays) and porous silicon (Porous Si).
A method of chemical etching of silicon with graphene as a catalyst.
The method according to claim 1,
The step of forming the graphene nanostructure comprises:
Wherein the graphene nanostructure is formed by performing an oxygen plasma treatment on the formed nanotemplate to etch the exposed graphene layer through the nanotemplate to form the graphene nanostructure.
The method according to claim 1,
The step of forming the silicon nanostructure comprises:
The method according to claim 1, wherein the nano template is removed, and then the formed graphene nanostructure is used as a catalyst and the silicon layer is etched in an etching solution environment to form the silicon nanostructure. .
The method according to claim 1,
The step of forming the graphene nanostructure comprises:
Forming an ordered nanosphere array on the stacked graphene layer using nanosphere lithography;
Performing oxygen plasma treatment on the formed nanospher array to form a graphene nanodos by etching the exposed graphene layer through the nanosphere array; And
Removing the nanosphere array
The method of chemical etching of silicon according to claim 1, wherein the graphene is a catalyst.
5. The method of claim 4,
The step of forming the silicon nanostructure comprises:
Wherein the silicon nanostructure is formed by etching the silicon layer using the formed graphene nanodata as a catalyst in the mixed etching solution environment containing hydrofluoric acid (HF) and hydrogen peroxide (H 2 O 2 ) As a catalyst.
The method according to claim 1,
The step of forming the graphene nanostructure comprises:
Preparing an anodized aluminum membrane (AAO membrane);
Depositing a metal thin film on the prepared anodized aluminum membrane;
Transferring the patterned metal thin film formed by selectively removing the anodized aluminum membrane onto the stacked graphene layer;
Performing an oxygen plasma treatment on the transferred patterned metal thin film to form a graphene mesh by etching the exposed graphene layer through the patterned metal thin film; And
Selectively removing the patterned metal foil
The method of chemical etching of silicon according to claim 1, wherein the graphene is a catalyst.
The method according to claim 6,
The step of forming the silicon nanostructure comprises:
Wherein the silicon nano structure is formed by etching the silicon layer using the formed graphene mesh as a catalyst in the mixed etching solution environment including hydrofluoric acid and hydrogen peroxide. delete
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