KR101581225B1 - Surface mountable integrated circuit packaging scheme - Google Patents

Surface mountable integrated circuit packaging scheme Download PDF

Info

Publication number
KR101581225B1
KR101581225B1 KR1020080110344A KR20080110344A KR101581225B1 KR 101581225 B1 KR101581225 B1 KR 101581225B1 KR 1020080110344 A KR1020080110344 A KR 1020080110344A KR 20080110344 A KR20080110344 A KR 20080110344A KR 101581225 B1 KR101581225 B1 KR 101581225B1
Authority
KR
South Korea
Prior art keywords
layers
substrate
mmic
pcb
millimeter wave
Prior art date
Application number
KR1020080110344A
Other languages
Korean (ko)
Other versions
KR20100051270A (en
Inventor
친흐 후이 도안
모하메드 에샤드 알리
Original Assignee
시빔, 인코퍼레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시빔, 인코퍼레이티드 filed Critical 시빔, 인코퍼레이티드
Priority to KR1020080110344A priority Critical patent/KR101581225B1/en
Publication of KR20100051270A publication Critical patent/KR20100051270A/en
Application granted granted Critical
Publication of KR101581225B1 publication Critical patent/KR101581225B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

An integrated circuit (IC) package is disclosed. The IC package includes a substrate having an uppermost layer, an intermediate layer, and a bottom layer; An array of millimeter wave antennas embedded in a top layer of the substrate; And a monolithic microwave integrated circuit (MMIC) mounted on the bottom layer of the substrate. In one embodiment, a second level interconnect for surface mount on a printed circuit board (PCB) is provided on the bottom layer of the substrate.

Figure R1020080110344

Description

[0001] SURFACE MOUNTABLE INTEGRATED CIRCUIT PACKAGING SCHEME [0002]

One embodiment of the present invention relates to integrated circuit packages, and more particularly to millimeter wave integrated circuit packages.

Millimeter wave systems that perform beamforming and steering typically include many antenna elements, integrated circuits, and interconnects. Such systems are the basis of a viable mechanism for providing short-range wireless connectivity at high data rates for consumer applications. In order to achieve performance and cost objectives, a common challenge is to develop an integrated platform package that is compatible with mass production and assembly processes.

Such an integrated package accommodates various functions as the level of integration increases. These functions include the provision of low loss, resonant millimeter wave signal paths, the integration of multilayer antenna elements and their internal network, local oscillator (LO), intermediate frequency (IF) distribution and passive circuits, Lt; / RTI >

A common scenario where a millimeter wave antenna is integrated with an integrated circuit (IC) is that both the antenna and the IC are located in the top layer of the substrate to ensure acceptable performance. This approach has problems when there are many antenna elements that need to be individually driven by separate RF ports located in more than one IC. First, routing congestion will limit the number of elements.

Moreover, the package is as large as the ICs, and the antennas must be positioned on the same surface with sufficient clearance. As the size of the package increases, the cost increases and, in some cases, the substrate may be too large to manufacture. Finally, heat removal from the ICs is difficult.

According to one embodiment, an integrated circuit (IC) package is disclosed. The IC package includes a substrate having an uppermost layer, an intermediate layer, and a bottom layer; An array of millimeter wave antennas embedded in one layer of the substrate (e.g., top layer); And a monolithic microwave integrated circuit (MMIC) mounted on another different layer of the substrate (e.g., the bottom layer).

According to another embodiment, a system is disclosed. The system includes a substrate having an uppermost layer, an intermediate layer and a bottom layer, an array of millimeter wave antennas embedded in one layer (e.g., top layer) of the substrate, and a monolithic microwave integrated circuit (MMIC) mounted on another layer ). ≪ / RTI > A printed circuit board (PCB) is mounted on the second layer of the substrate.

The invention will be best understood by reference to the following detailed description and the accompanying drawings which are used to illustrate embodiments of the invention.

A surface mountable packaging means for the integration of radiation and integrated circuit elements of a millimeter wave module is described. According to one embodiment, antennas are formed on the top layers of the substrate. A monolithic microwave integrated circuit (MMIC) and a ball grid array (BGA) are attached to the bottom side of the substrate.

A method for solving or alleviating most of the above problems is to use a double-sided package in which the antennas are located at the top and the ICs are located at the bottom of the package substrate. Accordingly, a mechanism for implementing a dual-side packaging that enables higher-level integration of millimeter-wave functionalities with proper performance is described.

In the following detailed description, numerous specific details are set forth. However, it will be apparent to those of ordinary skill in the art that the embodiments of the present invention can be practiced without these specific details. In other instances, well-known structures, devices, and techniques are not described in detail in order not to obscure the understanding of the present invention. Therefore, the detailed description is to be considered as illustrative rather than restrictive.

As used herein, "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

FIG. 1 illustrates one embodiment of a dual-sided surface mount millimeter wave integration system 100. The system 100 includes a multi-layer substrate 160 mounted on a printed circuit board (PCB) 105. Substrate 160 includes dielectric layers and metal layers located at the interface of the two dielectric layers. As described in the present invention, the reference to the term "layer " refers to a" metal layer "itself. In one embodiment, the substrate 160 is a high temperature co-fired ceramics (HTCC), although other substrate types may be used, such as, for example, a layer-based or build- Or low temperature co-fired ceramic (LTCC) alumina. Also, in one embodiment, the substrate 160 does not include cavities or special features, such as sidewall metallization.

In one embodiment, an antenna array 170 is embedded at the top of the substrate. In one embodiment, the antenna array 170 has metal patterns on multiple layers. In one embodiment, the top two layers are used for the antenna array 170. The antenna array 170 supplies and their distribution are accomplished using several inner layers of the substrate 160. At the bottom of the substrate 160, one or more MMICs 145 are flip-chip mounted to the substrate 160. In alternative embodiments, for example, a face-up (with the bottom side of the chip bonded to the substrate) with wire-bonds as interconnects between the chip and the substrate is mounted Are used, in which case the chip is placed face-up in the cavity to shorten the critical wire-bond length for millimeter wave operation. If a cavity is not desired in the package substrate, the chip can be thinly lapped. However, too thin a chip can cause handling and assembly problems.

Transmission lines 165 and ground planes 168 are included within the substrate 160. Transmission lines 165 transmit millimeter wave signals between the antenna of antenna array 170 and one or more MMICs 145.

According to one embodiment, each antenna array 170 element has a millimeter wave port corresponding to one of the MMICs 145. The flip-chip bump 147 couples the corresponding antenna array 170 element to the MMIC 145 via an under-fill 149. Thus, the millimeter wave signals initiated by the MMICs 145 travel to the middle layer of the substrate 160 and are distributed to the respective antenna supply points 165 and are progressively coupled to the antennas of the antenna array 170.

Other analog signals (e.g., LO and IF signals, bias and control signals) are routed through the analog signal routing 162 using a portion of the bottom layers of the substrate 160. Ball grid array (BGA) balls 150 are attached to the bottom of the substrate 160 to allow the package to be surface mounted on the PCB 105. In one embodiment, the size of the BGA balls 150 is selected to ensure that the combined height of the flip-chip mounted MMIC die 145 is less than the BGA ball 150 height.

In a further embodiment, during the surface mount operation, when the BGA balls 150 are reflowed, the die 145 acts as a hard-stop and prevents the BGA balls 150 from being completely collapsed. In one embodiment, a thermal compliant pad is disposed under the die to insure a low thermal resistance contact to the PCB 105. A solderable pad 130 is disposed on the PCB 105 below the die 145 and the backside of the die 145 is metallized with the metal component 140. In another embodiment, Thus, the back side of the die 145 may be soldered during surface mounting to ensure good thermal connection of the die 145 to the PCB 105.

According to one embodiment, the system 100 includes a multi-layer substrate 160 configuration for integration of the antenna array 170 on the top surface and the MMICs 145 on the bottom surface; The configuration of the bottom surface of the substrate 160 for surface mount assembly; And a configuration for mounting the package on the PCB 105.

Multi-layer board configuration

Figure 2 shows a cross-sectional view of one embodiment of a substrate 160. The layers are divided into three groups, the top layer 210 separated by the ground planes 168, the middle layer 220 and the bottom layer 230 based on the main functions being embedded. In one embodiment, top layers 210 are allocated for planar antenna elements. Multilayers are often required to implement techniques such as patch lamination to improve the performance of the antenna. It is noted that in alternate embodiments, a single layer may be used for planar antenna elements. Dielectric layer thicknesses can be determined by antenna design considerations. The top ground plane 168 isolates the antenna layers 210 from the rest of the package to provide immunity from electromagnetic interference.

Intermediate layers 220 are used to distribute millimeter wave signals to the antennas. In one embodiment, the antenna elements do not share supply lines, and the number of millimeter wave supply lines is equal to the number of elements of the antenna array. In one embodiment, one or more layers are used to efficiently distribute a large number of supply lines in a compact manner. The ground planes 168 provide shielding from the circuitry on the other layers. According to one embodiment, metallization other than signal lines is kept minimally on these layers for a homogeneous electromagnetic environment. In one embodiment, the keepout region from the signal trace is a design parameter that depends on factors such as the trace-width and substrate layer thickness, and so on. In other embodiments, other factors may affect such design parameters. In order to improve the transmission of a single TEM mode, strip lines with ground through fencing may be used for the signal lines, and the term " fencing " refers to a via via a certain distance on two sides of the signal trace, Quot; The distance between traces and ground vias and the spacing between vias are design parameters.

The bottom layers 230 are used for DC control and low frequency analog signals. In one embodiment, the highly integrated MMIC 145 requires multiple DC and control lines with LO and IF signal lines. Two or more layers may be used to achieve this and to calibrate the bottom layer 230 concentrated on the die 145 and the BGA 150. [ In one embodiment, the package is intended for surface mount applications, and the layers accordingly represent the electrical characteristics of the PCB under the package, which was not previously known. Thus, since there is no clearly defined electromagnetic boundary, the millimeter wave signal routing should be minimal on the bottom layers.

As described above, the millimeter wave signal distribution is maintained in the intermediate layers 220 that are shielded by the ground planes 168. In addition, multiple layers are added on top and bottom to accommodate different functions. This results in a relatively thick substrate 160 of a size of millimeter wave length. Thus, millimeter wave signals must travel a significant distance vertically as they progress from one layer to another. In one embodiment, a simple via transition, or a conventional quasi-coaxial via transition, can be used to suppress resonances, higher-order modes, and reflections that are present at long vertical interconnects Not enough.

Thus, in one embodiment, the corrected vertical interconnection means is implemented as a solution to this vertical interconnection problem. In the vertical interconnection, the millimeter wave signal is routed downward to the flip chip pads 208 on the corrected vertical interconnect 215, which is the inner metal layer of the substrate.

In a further embodiment, the correction structure is integrated into the layer transition structure. In such an embodiment, the arrangement, size and shape of the correction structure are determined through a modeling process. In a further embodiment, the modeling process may be performed using a three-dimensional (3D) electromagnetic tool (e.g., an HFSS of Ansoft Corporation) and a circuit simulator (e.g., Advanced Design System (ADS) from Agilent Technologies, Inc.) Optimization method.

According to one embodiment, the calibrated vertical interconnects are located at or close to all of the millimeter wave ports of the MMIC on the bottom. In other embodiments, similar vertical interconnections are used in the antenna-feed network of the supply means, where the millimeter wave signals must be routed from the middle layers to the top layers.

Substrate floor configuration

According to one embodiment, the bottom surface of the substrate 160 is configured as a second level interconnecting side of the package and the MMIC 145. The one or more MMICs 145 are flip-chip mounted to the substrate 160 using standard flip-chip assembly techniques. As described above, other mounting techniques may be used. Due to their low parasitics, the flip-chip interconnects can provide adequate performance at millimeter wave frequencies. In a further embodiment, the die 145 is mounted in the cavity to achieve a reduced wire-bond length for high frequency operation. Another advantage of the flip-chip mounting in its configuration is that the back side of the die 145 is exposed and available for efficient heat removal.

As a second level interconnect, a BGA type interface is used in which balls 150 are disposed around the perimeter of the substrate 160 in one or more rows. In one embodiment, all millimeter wave processing, such as frequency conversion, multiplexing, and phase-shifting, is implemented in the MMIC 145 and allows millimeter signals to be completely contained within the package except for radiation through the antennas. In this case, only low frequency IF, LO and reference signals are provided from the sources external to the package.

In such a scenario, the second level interconnect has moderate performance at low frequencies, thereby mitigating its performance specifications. As a result, other types of interconnects may be implemented. Figure 3 illustrates one embodiment of a system 100 in which the lid 300 couples the substrate 160 to the PCB 105, rather than the BGA balls 150.

Package Mount Configuration

In one embodiment, the flip-chip mounted die 145 and BGA balls 150 are on the surface mounting side of the package, and the package is queued to be attached to the PCB 105. There are several ways in which the package can be attached to the PCB 105. As shown in FIG. 1, the metallized backside 140 of the die 145 is bonded to the solderable mounting pad 130 on the PCB 105 during a surface mount operation. The size of the gap between the die and the mounting pad must be considered. For good solder connection in the BGA, the solder balls 150 need to collapse sufficiently during reflow. Because the die 145 acts as a hard stop against the PCB 105, too small a gap prevents the solder balls 150 from forming a good connection.

In another embodiment, the package is attached to the PCB 105 while the die 145 is not engaged with the PCB 105 during surface mounting. FIG. 4 illustrates a system 100 of such an embodiment. As shown in FIG. 4, it is important to prevent the BGA solder ball 150 from collapsing to a level at which the die 145 can contact the PCB 105. In one embodiment, this is accomplished by using some smaller non-reflowable balls or solid core BGA balls, and the size of the balls should be such that there is a gap between the die and the PCB.

As a third attachment method, the PCB 105 includes a through cutout that is larger than the size of the die 145. FIG. 5 illustrates a system 100 of one such embodiment. As shown in Fig. 5, the cutout 505 is located on the right under the die. During surface mounting, when the BGA balls 150 are collapsed, the die 145 slips into the cutout. This configuration allows the use of smaller BGA balls 150 because no gap is required between the die 145 and the PCB 105. The back side of the die 145 is exposed through the cutout 505 and thermal connection can be achieved using, for example, a heat-sink.

In another embodiment, the backside of the die 145 is not metallized for thermal connection. In such an embodiment, the thin metal paddle 510 may be bonded to the backside using a thermal adhesive, and then the metal paddle 510 may be attached to the PCB 105 to form a low resistance interface.

The system described above describes a means for forming a highly integrated millimeter wave package based on a thick multilayer substrate wherein the antennas are integrated in the top layers of the substrate and the BGA and MMIC for surface mounting are attached to the bottom. The means overcome the difficulties of making such unconventional packaging and can be implemented using mass production processes.

In the foregoing description of exemplary embodiments of the present invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or detailed description thereof, in order to streamline the specification to aid in understanding one or more of the various inventive features Points must be recognized. However, such a description should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, there are evolving ideas in fewer than all features of the single disclosed embodiment. Accordingly, the claims following the detailed description are to be construed as being included expressly in this detailed description, and each claim is based on itself as an individual embodiment of the present invention.

The foregoing detailed description is directed to specific embodiments. It will be apparent to those of ordinary skill in the art that modifications may be made to the embodiments described above while retaining all of the advantages or advantages. It is therefore the object of the appended claims to cover all such variations and modifications as are within the spirit and scope of the invention.

Figure 1 illustrates one embodiment of a dual-sided surface mounted integrated millimeter wave package.

Figure 2 shows one embodiment of a substrate.

Figure 3 illustrates another embodiment of a dual-sided surface mount millimeter wave integrated package.

Figure 4 illustrates another embodiment of a dual-sided surface mounted millimeter wave integrated package.

Figure 5 illustrates another embodiment of a dual-sided surface mounted millimeter wave integrated package.

Claims (12)

As an integrated circuit (IC) package, A substrate having a first, second and third set of at least one layer, And an array of millimeter-wave antennas embedded in the first set of layers of the substrate, wherein the array of millimeter- First antennas embedded in a first one of the first set of layers; And And second antennas embedded in a second one of the first set of layers; A monolithic microwave integrated circuit (MMIC) mounted on one of the layers of the third set of the substrate, the first surface of the MMIC being bonded to the substrate; Antenna feed points embedded in one or more of the layers of the second set of layers, each of the antenna feed points being coupled to a corresponding one of the millimeter wave antennas; An interconnect for communicating signals from the MMIC to the antenna feed points; A thermal compliant pad mounted on a second surface of the MMIC opposite the first surface of the MMIC, the thermal specification pad comprising a metal component for mounting to a printed circuit board (PCB) Providing a thermal connection between the PCBs; And Leads mounted on the third set of layers for mounting the substrate to a printed circuit board (PCB) ≪ / RTI > delete delete delete delete As an integrated circuit (IC) package, A substrate having a first, second and third set of at least one layer, And an array of millimeter wave antennas embedded in the first set of layers of the substrate, the array of millimeter wave antennas comprising: First antennas embedded in a first one of the first set of layers; And And second antennas embedded in a second one of the first set of layers; A monolithic microwave integrated circuit (MMIC) mounted on one of the layers of the third set of the substrate, the first surface of the MMIC being bonded to the substrate; Antenna feed points embedded in one or more layers of the second set of layers of the substrate; An interconnect for communicating a signal from the MMIC to the supply points; And A thermal compliant pad mounted on a second surface of the MMIC die opposite the first surface of the MMIC, the thermal specification pad comprising a metal component for mounting to a printed circuit board (PCB) Providing a thermal connection between the PCBs; ≪ / RTI > delete delete As a millimeter wave device, An integrated circuit (IC) package, comprising: A substrate having a first, second and third set of at least one layer, And an array of millimeter wave antennas embedded in the first set of layers of the substrate, the array of millimeter wave antennas comprising: First antennas embedded in a first one of the first set of layers; And And second antennas embedded in a second one of the first set of layers; A monolithic microwave integrated circuit (MMIC) mounted on one of the layers of the third set of layers, the first surface of the MMIC being bonded to the substrate; A printed circuit board (PCB) mounted on the third set of layers of the substrate using leads mounted on at least one layer of the third set of layers to mount the substrate to a printed circuit board (PCB); And A thermal compliant pad mounted on a second surface of the MMIC opposite the first surface of the MMIC, the thermal specification pad comprising a metal component for mounting to the printed circuit board (PCB) And a thermal connection between the PCB and the PCB. / RTI > 10. The method of claim 9, Wherein the MMIC comprises at least one port corresponding to an antenna of the array. 11. The method of claim 10, Wherein the package further comprises antenna feed points embedded in at least one of the layers of the second set of layers of the substrate. 12. The method of claim 11, Further comprising an interconnect for transferring a signal from the MMIC to the supply points.
KR1020080110344A 2008-11-07 2008-11-07 Surface mountable integrated circuit packaging scheme KR101581225B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080110344A KR101581225B1 (en) 2008-11-07 2008-11-07 Surface mountable integrated circuit packaging scheme

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080110344A KR101581225B1 (en) 2008-11-07 2008-11-07 Surface mountable integrated circuit packaging scheme

Publications (2)

Publication Number Publication Date
KR20100051270A KR20100051270A (en) 2010-05-17
KR101581225B1 true KR101581225B1 (en) 2015-12-30

Family

ID=42277064

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080110344A KR101581225B1 (en) 2008-11-07 2008-11-07 Surface mountable integrated circuit packaging scheme

Country Status (1)

Country Link
KR (1) KR101581225B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10905037B2 (en) 2017-12-15 2021-01-26 Samsung Electronics Co., Ltd. Electronic device having interference shielding structure
KR102305663B1 (en) 2020-09-04 2021-09-28 주식회사 넥스웨이브 Antenna package using trench structure and inspection method thereof
US11183753B2 (en) 2019-01-24 2021-11-23 Samsung Electronics Co., Ltd. Antenna module having plurality of printed circuit boards laminated therein, and electronic device comprising same
KR20240052373A (en) 2022-10-14 2024-04-23 주식회사 넥스웨이브 Antenna module

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107394366A (en) * 2017-07-28 2017-11-24 深圳市深大唯同科技有限公司 A kind of extensive mimo antenna structure and manufacturing process
WO2019059904A1 (en) * 2017-09-20 2019-03-28 Intel Corporation Leadframe in packages of integrated circuits
KR102499038B1 (en) * 2018-12-06 2023-02-13 삼성전자주식회사 Antenna module
US11791535B2 (en) 2020-09-28 2023-10-17 Samsung Electronics Co., Ltd. Non-galvanic interconnect for planar RF devices
CN116895614B (en) * 2023-07-25 2024-03-29 华南理工大学 Millimeter wave system packaging structure integrated by three-dimensional isomerism

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250913A (en) * 1995-03-15 1996-09-27 Honda Motor Co Ltd Mmic package assembly
KR0146063B1 (en) * 1995-03-28 1998-08-01 문정환 Semiconductor package and the manufacture method
JP3858801B2 (en) * 2002-10-10 2006-12-20 株式会社日立製作所 In-vehicle millimeter-wave radar device, millimeter-wave radar module, and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10905037B2 (en) 2017-12-15 2021-01-26 Samsung Electronics Co., Ltd. Electronic device having interference shielding structure
US11183753B2 (en) 2019-01-24 2021-11-23 Samsung Electronics Co., Ltd. Antenna module having plurality of printed circuit boards laminated therein, and electronic device comprising same
KR102305663B1 (en) 2020-09-04 2021-09-28 주식회사 넥스웨이브 Antenna package using trench structure and inspection method thereof
KR20240052373A (en) 2022-10-14 2024-04-23 주식회사 넥스웨이브 Antenna module

Also Published As

Publication number Publication date
KR20100051270A (en) 2010-05-17

Similar Documents

Publication Publication Date Title
US7675465B2 (en) Surface mountable integrated circuit packaging scheme
KR101581225B1 (en) Surface mountable integrated circuit packaging scheme
EP3828928B1 (en) Embedded multi-die interconnect bridge with improved power delivery
US9153863B2 (en) Low temperature co-fired ceramic (LTCC) system in a package (SiP) configurations for microwave/millimeter wave packaging applications
KR101397748B1 (en) Radio frequency(rf) integated circuit(ic) packages with integrated aperture-coupled patch antenna(s)
US9196951B2 (en) Millimeter-wave radio frequency integrated circuit packages with integrated antennas
US8648454B2 (en) Wafer-scale package structures with integrated antennas
TWI506863B (en) Radio frequency (rf) integrated circuit (ic) packages having characteristics suitable for mass production
KR100723635B1 (en) The planar transmission line to waveguide transition
US8525313B2 (en) Chip assembly with frequency extending device
CN110572926B (en) RF functionality and electromagnetic radiation shielding in a component carrier
US9728481B2 (en) System with a high power chip and a low power chip having low interconnect parasitics
US20030151133A1 (en) RF transition for an area array package
US11328987B2 (en) Waver-level packaging based module and method for producing the same
KR101702717B1 (en) System and method for a millimeter wave circuit board
EP2178119B1 (en) Surface mountable integrated circuit package
JP2010098274A (en) Packaging mechanism of surface-mountable integrated circuit
CN112864133A (en) Microelectronic package with substrate integration feature
EP3547363B1 (en) Electronic assembly and electronic system with impedance matched interconnect structures
CN112864147B (en) Three-dimensional multi-chip packaging structure capable of being combined
EP2469592A1 (en) Integrated circuit chip package device
JP2015026873A (en) Surface mountable integrated circuit packaging scheme
JP5762452B2 (en) Surface mountable integrated circuit packaging mechanism
US11430752B1 (en) Low cost millimiter wave integrated LTCC package
CN116884968A (en) Three-dimensional integrated packaging structure of antenna and multichannel radio frequency chip

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20180928

Year of fee payment: 4