KR101556337B1 - Semiconductor device, semiconductor light emitting device and manufacturing method thereof - Google Patents

Semiconductor device, semiconductor light emitting device and manufacturing method thereof Download PDF

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KR101556337B1
KR101556337B1 KR1020140087343A KR20140087343A KR101556337B1 KR 101556337 B1 KR101556337 B1 KR 101556337B1 KR 1020140087343 A KR1020140087343 A KR 1020140087343A KR 20140087343 A KR20140087343 A KR 20140087343A KR 101556337 B1 KR101556337 B1 KR 101556337B1
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layer
spin
dielectric layer
channel
electrode
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KR1020140087343A
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Korean (ko)
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김삼동
고필석
박경석
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동국대학교 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Led Devices (AREA)

Abstract

Provided are a semiconductor device, a semiconductor light emitting device, and a manufacturing method thereof. The semiconductor device according to an aspect of the present invention includes: a substrate; a buffer layer formed on the substrate; a stacked structure body formed on the buffer layer; and a spin-on dielectric layer for covering at least a part of the buffer layer and the stacked structure body. According to the present invention, an electrical property can be improved due to enable to prevent a defect occurrence between an active area and a dielectric layer by forming the dielectric layer for defining the active area using a spin-coating process, a yield can be improved due to reduce the process time, and manufacturing cost can be reduced due to have a benefit in a large area manufacturing process without requiring expensive equipment.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device, a semiconductor light emitting device, and a method of manufacturing the same. BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

TECHNICAL FIELD The present invention relates to a semiconductor device, a semiconductor light emitting device, and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device including a spin-on dielectric layer, a semiconductor light emitting device, and a method of manufacturing the same.

Semiconductor devices, such as power semiconductor devices and semiconductor light emitting devices, interfere with current leakage between adjacent devices and current leakage on the side of an active region through a dielectric layer that defines an active region of each device to prevent electrical characteristics from degrading have.

Generally, the dielectric layer is formed through a plasma enhanced chemical vapor deposition (PECVD) process or an atomic layer deposition (ALD) process.

However, when a PECVD process or the like is used, plasma damage is caused at the interface between the active region and the dielectric layer, thereby deteriorating the electrical characteristics of the semiconductor device. In the case of using the ALD process, There is a problem that the manufacturing cost is increased and the deposition time of the material is delayed and the yield is decreased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which uses a spin coating process in place of a PECVD process and an ALD process in forming a dielectric layer defining an active region, A semiconductor light emitting device, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate; A buffer layer formed on the substrate; A laminated structure formed on the buffer layer; And a spin-on dielectric layer covering at least a part of the upper surface of the buffer layer and at least a part of the side surface of the layer structure.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: sequentially forming a buffer layer and a laminate on a substrate; Forming a plurality of trenches which define a laminated structure in which a part of the upper surface of the buffer layer is exposed and an upper surface and a side surface of the buffer layer are exposed; And forming a spin-on dielectric layer covering at least a part of the upper surface of the buffer layer and at least a part of the side surface of the laminated structure within the plurality of trenches.

According to another aspect of the present invention, there is provided a semiconductor light emitting device comprising: a substrate; A first conductivity type semiconductor layer formed on the substrate and having a first portion and a second portion having a width smaller than the first portion in a direction parallel to the substrate; An active layer formed on the second portion; A second conductive semiconductor layer formed on the active layer; And a spin-on dielectric layer covering the first side of the first portion and the first side of the second portion extending in a direction parallel to the substrate from the first side of the second portion.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor light emitting device, comprising: sequentially forming a preliminary first conductivity type semiconductor layer, a preliminary active layer, and a preliminary second conductivity type semiconductor layer on a substrate; And a second portion having a width smaller than that of the first portion in a direction parallel to the first portion and the substrate, wherein the first portion is formed by removing a portion of the preliminary first conductivity type semiconductor layer, the preliminary active layer, Forming first and second trenches defining an active layer on the second portion and a second conductive type semiconductor layer on the active layer; And a spin-on dielectric layer covering the first side of the first portion and the first side of the second portion extending in a direction parallel to the substrate from the first side of the second portion within the first trench Step.

A semiconductor device, a semiconductor light emitting device and a manufacturing method thereof according to the technical idea of the present invention are characterized in that a dielectric layer defining an active region of each device is formed by using a spin coating process so that there is no defect between the active region and the dielectric layer, It is possible to prevent deterioration of the characteristics, to shorten the process time and to improve the yield, and to eliminate the need for expensive equipment, which is advantageous for the large-scale manufacturing process, and the manufacturing cost can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.
1 is a cross-sectional view showing a partial structure of a semiconductor device according to an embodiment of the present invention.
2A to 2H are cross-sectional views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a partial structure of a semiconductor light emitting device according to an embodiment of the present invention. Referring to FIG.
4A to 4H are cross-sectional views illustrating a method of manufacturing a semiconductor light emitting device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and a duplicate description thereof will be omitted.

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

Although the terms first, second, etc. are used herein to describe various elements, regions, layers, regions and / or elements, these elements, components, regions, layers, regions and / It should not be limited by. These terms do not imply any particular order, top, bottom, or top row, and are used only to distinguish one member, region, region, or element from another member, region, region, or element. Thus, a first member, region, region, or element described below may refer to a second member, region, region, or element without departing from the teachings of the present invention. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs, including technical terms and scientific terms. In addition, commonly used, predefined terms are to be interpreted as having a meaning consistent with what they mean in the context of the relevant art, and unless otherwise expressly defined, have an overly formal meaning It will be understood that it will not be interpreted.

If certain embodiments are otherwise feasible, the particular process sequence may be performed differently from the sequence described. For example, two processes that are described in succession may be performed substantially concurrently, or may be performed in the reverse order to that described.

In the accompanying drawings, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein, but should include variations in shape resulting from, for example, manufacturing processes.

1 is a cross-sectional view showing a partial structure of a semiconductor device 10 according to an embodiment of the present invention.

1, a semiconductor device 10 includes a substrate 110, a buffer layer 120, a laminate structure 130, a spin-on dielectric layer 140, first to third electrodes 151 , 153, 155, and a passivation layer 160.

The substrate 110 may comprise an insulating material. The insulating material may be, for example, SiC, Al 2 O 3 , Si, or the like. The substrate 110 may have high resistivity and may be doped with an n-type or p-type dopant.

A buffer layer 120 is formed on the substrate 110. The buffer layer 120 is dislocated due to a sudden change in lattice size between materials constituting the channel layer 131 and the substrate 110 of the laminated structure 130 formed on the buffer layer 120. [ And prevent the occurrence of defects in the temperature change due to the difference in the thermal expansion coefficient, it can serve to buffer the difference of the lattice size and the thermal expansion coefficient therebetween. The buffer layer 120 may include a compound semiconductor material such as GaN, AlN, AlGaN, or the like, but may have a single-layer or multi-layer structure.

A laminated structure 130 is formed on the buffer layer 120. The stacked structure 130 may function as an active region of the semiconductor device 10 and may have a structure in which a channel layer 131, a channel supply layer 133, and a capping layer 135 are sequentially stacked.

The channel layer 131 is formed on the buffer layer 12 and may provide a channel between the first and second electrodes 151 and 153. In detail, the channel layer 131 has a channel between the first and second electrodes 151 and 153 through a channel region CR formed adjacent to the interface between the channel layer 131 and the channel supply layer 133 . The channel region CR may comprise a channel carrier controlled by a bias voltage applied to the third electrode 155. For example, the channel region CR may be a two-dimensional electgron gas (hereinafter referred to as " 2-dimensional electron gas ") caused by a difference in characteristics such as electrical polarization between the channel layer 131 and the channel supply layer 133, DEG) as the channel carriers. However, the technical idea of the present invention is not limited thereto, and the channel region CR may include a 2-dimensional hole gas (hereinafter, 2-DHG) as the channel carrier.

The channel layer 131 may include at least one of compound semiconductor materials such as GaN, InGaN, AlGaN, AlN, InN, GaAs, GaP, AlAs, AlSb, AlP, GaSb, InSb, ZnO, However, the technical idea of the present invention is not limited thereto, but may include other materials as long as 2-DEG and 2-DHG can be formed therein. Further, the channel layer 131 may be an undoped semiconductor layer, but in some cases, it may be doped with the n-type or the p-type dopant.

The channel supply layer 133 may be formed on the channel layer 131. The channel supply layer 133 may include a semiconductor material having at least one of a polarization property, an energy band gap, and a lattice constant different from that of the channel layer 131. For example, the channel supply layer 131 may be made of a compound semiconductor material containing at least one selected from among nitrides including at least one of Al, Ga, In, and B, and may have a single layer or a multi-layer structure. In detail, the channel supply layer 131 is made of a compound semiconductor material containing at least one of various materials composed of AlGaN, AlInN, InGaN, AlN, AlInGaN and the like, and may have a single layer or a multilayer structure. The channel supply layer 133 may be an undoped semiconductor layer, but in some cases it may be doped with the n-type or the p-type dopant.

Meanwhile, the channel supply layer 133 may include first to third electrodes 151, 153, and 155 in a subsequent process of forming the first to third electrodes 151, 153, and 155 on the capping layer 135 And may serve as a barrier to prevent diffusion of metal atoms into the channel layer 131.

The capping layer 135 may be formed on the channel supply layer 133. The capping layer 135 may serve to protect the underlying channel layer 131 and the channel supply layer 133 from damage during subsequent wet processes, such as wet scrubbing or wet etching processes. The capping layer 135 may include at least one of various compound semiconductor materials, for example, GaN, InGaN, AlGaN, and the like.

A spin-on dielectric layer 140 is formed on the buffer layer 130 so as to be in contact with the side surface of the layered structure 130. The spin-on dielectric layer 140 can electrically isolate the laminate structure 130 functioning as an active region in the production of the semiconductor element 10 from a laminate structure (not shown) of other neighboring semiconductor elements, 130 can be prevented from leaking from the side surface 130S.

The spin-on dielectric layer 140 may cover at least a part of the side surface 130S of the laminate structure 130. As shown in FIG. 1, the spin-on dielectric layer 140 may completely cover the side surfaces of the channel layer 131 and the channel supply layer 133, but may cover a part of the side surface of the capping layer 135. The spin-on dielectric layer 140 may completely cover the side surfaces of the channel layer 131, the channel supply layer 133, and the capping layer 135, The side surface of the channel supply layer 133 may be entirely covered, but the side surface of the channel supply layer 133 may be partially covered. The spin-on dielectric layer 140 is formed on the upper surface 120T of the buffer layer 120 with respect to the upper surface 120T in order to effectively block current leakage from the side surface 130 of the laminated structure 130 130 of the channel region CR.

The spin-on dielectric layer 140 may have a predetermined thickness in a direction parallel to the substrate 110 so as to cover at least a part of the upper surface 120T of the buffer layer 120. [ 1, the spin-on dielectric layer 140 is formed on the upper surface 120T of the buffer layer 120 protruding from the side surface 130S of the laminated structure 130 along a direction parallel to the substrate 110. [ You can cover the whole thing. In another embodiment, the spin-on dielectric layer 140 may cover only a portion of the top surface 120T of the buffer layer 120 that protrudes from the side surface 130S of the laminate structure 130 along a direction parallel to the substrate 110. [

The spin-on dielectric layer 140 may comprise a spin-on dielectric such as, for example, perhydropolysilazane or benzocyclobutene.

On the laminated structure 130, first and second electrodes 151 and 153 are formed to be spaced apart from each other. The first and second electrodes 151 and 153 can respectively contact the capping layer 135 of the multilayer structure 130 and function as a source or a drain electrode of the semiconductor element 10. On the other hand, the lower surfaces of the first and second electrodes 151 and 153 may be in contact with the upper surface 140T of the spin-on dielectric layer 140. The first and second electrodes 151 and 153 may include at least one of various metal materials including, for example, Ti, Al, Ni, Au, and the like.

A third electrode 155 is formed between the first and second electrodes 151 and 153 on the laminated structure 130. The third electrode 155 may function as a gate electrode of the semiconductor element 10. [ The third electrode 155 may include at least one of various metal materials including, for example, TiN, Ta, TaN, Pd, W, Ni, Au,

Depending on the voltage applied to the first to third electrodes 151, 153 and 155, the semiconductor element 10 may be driven by a normally on element or a normally off element. Here, the normally-on element means an element having an open channel state so that a current can flow in a state in which no voltage is applied, and the normally off element is a closed channel state in which no current flows when no voltage is applied Device.

A passivation layer 160 is formed on the capping layer 135 above the stacked structure 30 exposed between the first to third electrodes 151, 153 and 155. The passivation layer 160 serves to protect the multilayer structure 130 from subsequent processes or external contamination, and may be formed of an insulating material such as SiO, SiN, or the like.

2A to 2H are cross-sectional views illustrating a method of fabricating the semiconductor device 10 according to an embodiment of the present invention. In FIGS. 2A to 2H, the same reference numerals as in FIG. 1 denote the same members, and a duplicate description will be omitted for the sake of simplicity.

2A, a buffer layer 120 is formed on a substrate 110, a preliminary channel layer 131p, a preliminary channel supply layer 133p, and a preliminary capping layer 135p are sequentially stacked to form a stack 130p ).

The buffer layer 120, the preliminary channel layer 131p, the preliminary channel supply layer 133p and the preliminary capping layer 135p can be formed by, for example, a metal organic chemical vapor deposition process, a vapor phase epitaxy process, a liquid phase epitaxy process, a molecular beam epitaxy process, and a hydride vapor phase epitaxy process.

Referring to FIG. 2B, a part of the stacked body 130p is removed to form a plurality of trenches T11 which expose a part of the upper surface of the buffer layer 120 and define the stacked structure 130. FIG.

Although not shown, first, a photoresist layer covering the upper surface of the layered product 130p is formed. Then, a predetermined pattern for defining the laminated structure 130, which is an active region of the semiconductor element 10, is formed through a lithography process. Subsequently, the laminate 130p in the region other than the pattern or the pattern region is removed through an etching process such as inductively coupled plasma-reactive ion etching (ICP-RIE) The trench T11 can be formed.

Referring to FIG. 2C, a preliminary spin-on dielectric layer 140p covering the top surface 130T of the laminate structure 130 and filling a plurality of trenches T11 is formed.

The preliminary spin-on dielectric layer 140p can be formed by spin-coating a spin-on dielectric, such as perhydropolysilazane, over the entire surface of the substrate 110. [ Here, the spin coating process can be performed under process conditions of room temperature and normal pressure.

Referring to FIG. 2D, heat is applied to cure the preliminary spin-on dielectric layer 140p.

For example, the preliminary spin-on dielectric layer 140p is first baked at a temperature of about 180 DEG C for about 3 minutes in a hot plate, and baked at a temperature of about 400 DEG C for about 10 minutes in the hot plate And the preliminary spin-on dielectric layer 140p can be cured.

Through this curing process, the density of the spin-on dielectrics constituting the preliminary spin-on dielectric layer 140p is increased to convert the spin-on dielectric into SiO2 material.

Referring to FIG. 2E, a spin-on dielectric layer 140 is formed by removing a portion of the preliminary spin-on dielectric layer 140p that is cured to expose the top surface 130T of the stacked structure 130, that is, the capping layer 135. FIG.

The cured spare spin-on dielectric layer 140p may be partially removed to expose a portion of the side of the capping layer 135 and cover the sides of the channel layer 131 and the channel supply layer 133 no. 1, the cured preliminary spin-on dielectric layer 140p is formed such that the upper surface 140T of the spin-on dielectric layer 140 overlaps the upper surface 120T of the buffer layer 120 with respect to the laminate structure 130 (See FIG. 1) formed in the channel region CR (see FIG. 1).

The cured spin-on dielectric layer 140p may be partially removed, for example, through a wet etch process. In detail, the cured spin-on dielectric layer 140p can be removed through a wet etching process using a buffered oxide etchant (BOE) solution. Or the cured spin-on dielectric layer 140p may be partially removed, for example, through a chemical mechanical polishing process.

Thus, the semiconductor device 10 can be subjected to a spin coating process instead of the PECVD process or the ALD process in forming an active region, for example, a predetermined insulating layer defining the laminated structure 130, for example, a spin-on dielectric layer 140 . Accordingly, the semiconductor device 10 can fundamentally block the defects on the side of the active region by PECVD, thereby improving the electrical characteristics. Therefore, the semiconductor device 10 can be fabricated quickly and cost-effectively without using ALD requiring high- It is possible to reduce the manufacturing cost and improve the yield.

Referring to FIG. 2F, the upper surface 130T of the laminated structure 130, that is, the upper surface of the capping layer 135 and the upper surface 140T of the spin-on dielectric layer 140 are spaced apart from each other on the laminated structure 130, The first and second electrodes 151 and 153 are formed.

For example, after forming a metal material layer (not shown) such as Ti, Al, Ni covering the upper surface 130T of the laminated structure 130 and the upper surface 140T of the spin-on dielectric layer 140, The first and second electrodes 151 and 153 may be formed by removing a portion of the metal material layer. Although not shown, ohmic contact between the first and second electrodes 151 and 153 and the stacked structure 130 is achieved through annealing after the first and second electrodes 151 and 153 are formed. Can be formed.

Referring to FIG. 2G, a third electrode 153 is formed on the stacked structure 130 exposed between the first and second electrodes 151 and 153.

A metal material layer (not shown), such as TiN, Ta, and W, covering the upper surface 130T of the multilayer structure 130, the spin-on dielectric layer 140, and the first and second electrodes 151 and 153, And the third electrode 155 may be formed by removing a portion of the metal material layer through a lift-off process. Here, a Schottky junction may be formed between the third electrode 155 and the stacked structure 130.

Referring to FIG. 2H, a passivation layer 160 is formed to cover the upper surface 130T of the multilayer structure 130 exposed between the first, second, third, and fourth electrodes 151, 153 and 155.

An insulating material layer (not shown) covering the upper surface 130T of the multilayer structure 130, the spin-on dielectric layer 140, and the first to third electrodes 151, 153, 155 through a chemical vapor deposition process, A part of the insulating material layer is removed such that the upper surfaces of the first to third electrodes 151, 153 and 155 are at least partially exposed through an ICP-RIE process or an ashing process A passivation layer 160 may be formed.

3 is a cross-sectional view showing a partial structure of a semiconductor light emitting device 20 according to an embodiment of the present invention.

3, the semiconductor light emitting device 20 includes a substrate 210, a light emitting stack 220, a spin-on dielectric layer 230, a metal layer 240, and first and second electrodes 251 and 253 can do.

Substrate 210 is a growth substrate for the light emitting laminated body 220, insulating, semiconductor material having conductivity, such as sapphire, diamond, MgAl 2 O 4, MgO, LiAlO 2, LiGaO 2, GaN, Si, diamond And a semiconductor material comprising a combination thereof.

3, when the substrate 210 includes a material different from that of the light emitting stack 220, it is preferable that the material of the substrate 210 and the light emitting stack 220 is an abrupt The lattice size change between the substrate 210 and the luminescent stack 220 is changed in order to prevent defects such as dislocations from occurring due to a change in lattice size and to prevent warping at a temperature change due to a difference in thermal expansion coefficient. And a buffer layer (not shown) functioning to buffer the difference in thermal expansion coefficient may be interposed.

On the substrate 210, a light emitting stack 220 is formed. The light emitting stack 220 is formed by sequentially stacking the first conductivity type semiconductor layer 221, the active layer 223 and the second conductivity type semiconductor layer 225, and a part of the first conductivity type semiconductor layer 221 And may have an exposed mesa structure.

The first conductive semiconductor layer 221 may be formed on the substrate 210. The first conductive semiconductor layer 221 may include a semiconductor material such as GaN, AlInGaN, AlGaInP, AlGaAs, or the like, and may be doped with an n-type dopant. However, when the second conductivity type semiconductor layer 225 is doped with the n-type dopant, the first conductivity type semiconductor layer 221 may be doped with a p-type dopant. Although the first conductive semiconductor layer 221 is shown as a single layer in FIG. 3, the first conductive semiconductor layer 221 may have a multi-layer structure having different compositions and thicknesses as needed.

The first conductive semiconductor layer 221 includes a first portion 221a contacting the substrate 210 and a second portion 221b having a smaller width than the first portion 221a in a direction parallel to the substrate 210 . Accordingly, the first portion 221a may protrude in a direction parallel to the substrate 210 from both sides of the second portion 221b. On the upper surfaces 221aT1 and 221aT2 of the first portion 221a extending in parallel to the substrate 210 from both sides of the second portion 221b are formed spin-on dielectric layers 230, One electrode 251 may be formed.

Although not shown in FIG. 3, the first conductive semiconductor layer 221 may have a carrier injection layer capable of improving the injection efficiency of electrons or holes, and may have various superlattices have.

The active layer 223 may be formed on the second portion 221b of the first conductive type semiconductor layer 221. [ The active layer 223 can emit light by recombining electrons and holes. The active layer 223 may have a multi quantum well structure in which a quantum well layer and a quantum barrier layer are alternately stacked, for example, a GaN / InGaN structure in a nitride semiconductor. However, the present invention is not limited thereto. The active layer 223 may have a single quantum well structure.

The second conductive semiconductor layer 225 may be formed on the active layer 223. The second conductivity type semiconductor layer 225 may include a semiconductor material such as GaN, AlInGaN, AlGaInP, AlGaAs, or the like as the first conductivity type semiconductor layer 221. The second conductive semiconductor layer 225 may be doped with a p-type dopant. However, when the first conductivity type semiconductor layer 221 is doped with the p-type dopant, the second conductivity type semiconductor layer 225 may be doped with an n-type dopant. 3, the second conductive semiconductor layer 225 is formed as a single layer. However, the second conductive semiconductor layer 225 may have a multi-layer structure having different compositions and thicknesses as needed.

Although not shown in FIG. 3, the second conductivity type semiconductor layer 225 may include a carrier injection layer, which can improve the injection efficiency of electrons or holes, like the first conductivity type semiconductor layer 221, Various types of superlattice structures may be provided.

A spin-on dielectric layer 230 is formed on the first conductive semiconductor layer 221 of the light emitting stack 220 so as to be in contact with one side of the light emitting stack 220. The spin-on dielectric layer 230 can electrically isolate the light-emitting stack 220 functioning as an active region in the production of the semiconductor light-emitting device 20 from a light-emitting stack (not shown) of another neighboring semiconductor light-emitting device The current leakage generated from one side of the light emitting stacked body 220 can be blocked.

The spin-on dielectric layer 230 includes a first portion 221b1 extending in a direction parallel to the substrate 210 from the first side 221bS1 of the first portion 221b of the first conductivity type semiconductor layer 221, 221a1 of the first portion 221a and the first side 221bS1 of the second portion 221b of the first portion 221a. The spin-on dielectric layer 230 includes an active layer 223 extending in a direction perpendicular to the substrate 210 and coplanar with the first side 221bS1 of the second portion 221b, (Not shown).

The spin-on dielectric layer 230 may comprise a spin-on dielectric such as, for example, perhydropolysilazane or benzocyclobutene.

A metal layer 240, which is a light-transmitting layer, is formed on the light emitting stack 220. The metal layer 240 may provide a shortened current path between the first electrode 251 and the second electrode 253 when a predetermined voltage is applied to the first electrode 251 and the second electrode 253. The metal layer 240 may comprise a metallic material such as Pt. 1, one side of the metal layer 240 is formed to be covered with the spin-on dielectric layer 230, but the present invention is not limited thereto, and the metal layer 240 may be formed to cover the upper surface of the spin- .

The first electrode 251 is formed on the side of the light emitting stack 220 contacting the spin-on dielectric layer 230 on the first conductive semiconductor layer 221 of the light emitting stack 220. The first electrode 251 is formed on the second upper surface 221aT2 of the first portion 221a extending in the direction parallel to the substrate 210 from the second side 221bS2 of the second portion 221b Respectively. A second electrode 253 is formed on the metal layer 240.

The first and second electrodes 251 and 253 may include a single metal material such as Ag, Al, Ni, Cr, Pd and Cu, or an alloy material thereof. The first and second electrodes 251 and 253 may include transparent conductive oxides such as TCO, ITO, AZO, IZO, and the like. The first and second electrodes 251 and 253 may have a single layer or a multilayer structure.

3, an ohmic contact layer may be interposed between the metal layer 240 and the second electrode 253 to form an ohmic contact.

4A to 4H are cross-sectional views illustrating a method of fabricating the semiconductor light emitting device 20 according to one embodiment of the present invention. 4A to 4H, the same reference numerals as in FIG. 3 denote the same members, and redundant description is omitted here for the sake of simplicity.

Referring to FIG. 4A, a substrate 210, a preliminary first conductivity type semiconductor layer 221p, a preliminary active layer 223p, and a preliminary second conductivity type semiconductor layer 225p are sequentially formed.

The substrate 210, the preliminary first conductivity type semiconductor layer 221p, the preliminary active layer 223p and the preliminary second conductivity type semiconductor layer 225p may be formed by, for example, a metal organic chemical vapor deposition , A vapor phase epitaxy process, a liquid phase epitaxy process, a molecular beam epitaxy process, or a hydride vapor phase epitaxy process can do.

Although not shown in FIG. 4, a buffer layer (not shown) is formed on the substrate 210 before the preliminary first conductivity type semiconductor layer 221p is formed, and then a preliminary first conductivity type semiconductor layer The preliminary active layer 223p, and the preliminary second conductivity type semiconductor layer 225p may be sequentially formed.

Referring to FIG. 4B, a part of the preliminary first conductivity type semiconductor layer 221p, the preliminary active layer 223p, and the preliminary second conductivity type semiconductor layer 225p is etched to form a first conductivity type semiconductor layer The first and second trenches T21 and T22 defining the light emitting stack 220 composed of the first conductive semiconductor layer 221, the active layer 223 and the second conductive semiconductor layer 225 are formed.

The first conductivity type semiconductor layer 221 has a first portion 221a and a second portion 221b having a smaller width than the first portion 221a in a direction parallel to the substrate 210, The first and second top surfaces 221aT1 and 221aT2 of the first portion 221a and the first and second sides 221bS1 and 221bS2 of the second portion 221b are exposed so that the preliminary first conductivity type semiconductor layer 221p The preliminary active layer 223p and the preliminary second conductivity type semiconductor layer 225p are partially removed along the direction perpendicular to the substrate 210 to form the first and second trenches T21 and T22.

Although not shown, first, a photoresist layer covering the upper surface of the preliminary second conductivity type semiconductor layer 225 is formed. Then, a predetermined pattern for defining the light emitting stack 220 is formed through a lithography process. Next, a region of the first conductive type semiconductor layer 221p in the region other than the pattern or in the pattern region through an inductively coupled plasma-reactive ion etching (ICP-RIE) The preliminary active layer 223p and the preliminary second conductivity type semiconductor layer 225p may be removed to form the first and second trenches T21 and T22.

Referring to FIG. 4C, a preliminary spin-on dielectric layer 230p covering the top surface of the second conductive type semiconductor layer 225 and filling the first and second trenches T21 and T22 is formed.

The preliminary spin-on dielectric layer 230p may be formed by spin-coating a spin-on dielectric, such as perhydropolysilazane, over the top surface of the substrate 210, for example. Here, the spin coating process can be performed under process conditions of room temperature and normal pressure.

Referring to FIG. 4D, heat is applied to cure the preliminary spin-on dielectric layer 230p.

For example, the preliminary spin-on dielectric layer 230p is first baked at a temperature of about 180 DEG C for about 3 minutes on a hot plate, and baked at a temperature of about 400 DEG C for about 10 minutes, , So that the preliminary spin-on dielectric layer 230p can be cured.

Through this curing process, the density of spin-on dielectrics constituting the preliminary spin-on dielectric layer 230p is increased and the spin-on dielectric can be converted into SiO2 material.

Referring to FIG. 4E, the upper surface of the second conductive semiconductor layer 225 and the second upper surface 221aT2 of the first portion 221a and the second surface 221b of the second portion 221b in the second trench T22 A part of the preliminary spin-on dielectric layer 230p hardened to expose the spin-on dielectric layer 221bS2 is removed to form a spin-on dielectric layer 230. [ The spin-on dielectric layer 230 is formed on the first upper surface 221aT1 of the first portion 221a and the first upper surface 221aT2 of the second portion 221b of the first portion 221a as the hardened spin-on dielectric layer 230p in the first trench T21 is not removed. The side surfaces of the active layer 223 and the second conductivity type semiconductor layer 225 which are flush with the first side 221bS1 and the first side 221bS1 of the second portion 221b can be covered.

The cured spin-on dielectric layer 230p may be partially removed, for example, through a wet etch process. Specifically, the cured spin-on dielectric layer 230p may be removed through a wet etch process using a buffered oxide etchant (BOE) solution.

4E, the upper surface of the spin-on dielectric layer 230 is positioned higher than the upper surface of the light emitting stack 220 with respect to the upper surface of the substrate 210, but the present invention is not limited thereto. The upper surface of the spin-on dielectric layer 230 may be positioned at the same or lower than the upper surface of the light emitting stack 220 with respect to the upper surface of the substrate 210.

As described above, the spin-on dielectric layer 230 covering one side of the light emitting stack 220 as the active region is formed by a spin coating process, not by the PECVD process or the ALD process. Accordingly, the semiconductor light emitting device 20 can prevent the occurrence of defects on the side of the light emitting stack 220, improve the electrical characteristics, and can be manufactured quickly at a low cost, thereby reducing the manufacturing cost and improving the yield, It is particularly advantageous for large-scale.

Referring to FIG. 4F, a metal layer 240 covering the upper surface of the light emitting stack 220 is formed.

For example, a metal material layer such as Pt is formed on the entire upper surface of the substrate 210 through an E-beam evaporation process, and then a second conductive semiconductor layer (not shown) is formed through an etching process, an etch- The metal layer 240 may be formed by removing the metal layer other than the metal layer on the upper surface.

In another embodiment, the metal material layer on top of the spin-on dielectric layer 230 upon removal of the metal material layer, such that the metal layer 240 covers the top surface of the spin-on dielectric layer 230 with the top surface of the luminescent stack 220, May not be removed.

Referring to FIG. 4G, the first electrode 251 is formed on the second top surface 221aT2 of the first portion 221a of the first conductivity type semiconductor layer 221 in the second trench T22.

For example, in order to form the first electrode 251, a metal material layer (not shown) such as Ti or Al covering the upper surface of the substrate 210 is formed and then a part of the metal material layer is removed through a lift- So that the first electrode 251 can be formed.

Referring to FIG. 4H, a second electrode 253 is formed on the metal layer 240.

For example, in order to form the second electrode 253, a metal material layer such as Ni or Au is formed on the substrate 210 in the same manner as in the formation of the first electrode 251, The second electrode 253 may be formed by removing a part of the metal material layer. Though not shown, the contact resistance between the first and second electrodes 251 and 253 and the light emitting stack 220 can be lowered through annealing.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

10: Semiconductor device
20: Semiconductor light emitting element

Claims (20)

Board;
A buffer layer formed on the substrate;
A laminated structure formed on the buffer layer;
A spin-on dielectric layer covering at least a portion of the upper surface of the buffer layer and at least a portion of the side surface of the stacked structure;
First and second electrodes spaced apart from each other on the stacked structure and covering at least a part of the upper surface of the spin-on dielectric layer;
A third electrode formed between the first and second electrodes on the laminated structure; And
A passivation layer covering the upper surface of the laminated structure between the first electrode and the third electrode and between the second electrode and the third electrode;
≪ / RTI >
The method according to claim 1,
Wherein the laminated structure includes a channel layer, a channel supply layer, and a capping layer sequentially formed on the buffer layer,
And the upper surface of the spin-on dielectric layer is located higher than a channel region formed adjacent to the interface between the channel layer and the channel supply layer with respect to the upper surface of the buffer layer.
3. The method of claim 2,
Wherein at least one of the channel layer, the channel supply layer, and the capping layer comprises a compound semiconductor material,
Wherein the channel region comprises a two-dimensional electron gas as a channel carrier.
The method according to claim 1,
Wherein the spin-on dielectric layer comprises perhydropolysilazane or benzocyclobutene.
delete Sequentially forming a buffer layer and a laminate on a substrate;
Forming a plurality of trenches which define a laminated structure in which a part of the upper surface of the buffer layer is exposed and an upper surface and a side surface of the buffer layer are exposed;
Forming a spin-on dielectric layer covering at least a part of the upper surface of the buffer layer and at least a part of the side surface of the laminated structure within the plurality of trenches;
Forming first to third electrodes spaced apart from each other on the stacked structure; And
Forming a passivation layer between the first electrode and the third electrode to cover the upper surface of the laminated structure,
Wherein forming the first to third electrodes comprises:
And the first and second electrodes are formed such that the first and second electrodes cover at least a part of the upper surface of the spin-on dielectric layer.
The method according to claim 6,
The step of forming the spin-
Forming a preliminary spin-on dielectric layer covering the top surface of the laminated structure and filling the plurality of trenches;
Applying heat to cure the preliminary spin on dielectric layer; And
Forming a spin-on dielectric layer by removing a portion of the cured preliminary spin-on dielectric layer to expose an upper surface of the laminate structure;
Wherein the semiconductor device is a semiconductor device.
8. The method of claim 7,
The step of removing a portion of the cured pre-spin on dielectric layer to form the spin-
And a portion of the cured preliminary spin-on dielectric layer is removed so that the upper surface of the spin-on dielectric layer is located higher than the channel region formed in the laminate structure with respect to the upper surface of the buffer layer
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081333A (en) 2005-09-16 2007-03-29 Showa Denko Kk Nitride-based semiconductor light-emitting element and manufacturing method thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081333A (en) 2005-09-16 2007-03-29 Showa Denko Kk Nitride-based semiconductor light-emitting element and manufacturing method thereof

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