KR101154562B1 - The solder, the semiconductor package and the method for manufacturing the same - Google Patents

The solder, the semiconductor package and the method for manufacturing the same Download PDF

Info

Publication number
KR101154562B1
KR101154562B1 KR1020100084592A KR20100084592A KR101154562B1 KR 101154562 B1 KR101154562 B1 KR 101154562B1 KR 1020100084592 A KR1020100084592 A KR 1020100084592A KR 20100084592 A KR20100084592 A KR 20100084592A KR 101154562 B1 KR101154562 B1 KR 101154562B1
Authority
KR
South Korea
Prior art keywords
alloy layer
layer
solder
lead
copper
Prior art date
Application number
KR1020100084592A
Other languages
Korean (ko)
Other versions
KR20120020765A (en
Inventor
임설희
김애림
박창화
Original Assignee
엘지이노텍 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지이노텍 주식회사 filed Critical 엘지이노텍 주식회사
Priority to KR1020100084592A priority Critical patent/KR101154562B1/en
Publication of KR20120020765A publication Critical patent/KR20120020765A/en
Application granted granted Critical
Publication of KR101154562B1 publication Critical patent/KR101154562B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Abstract

The present invention discloses a lead-free solder consisting of an alloy having a composition comprising up to 3.0 weight percent silver, 0.5 to 1 weight percent copper, and excess tin. Therefore, for the surface treatment of forming an electroless nickel alloy layer, a palladium alloy layer, and a gold alloy layer on a copper pad, the thickness of the metal bonding layer can be reduced by changing the composition of the solder, and cracks are formed in the solder rather than in the metal bonding layer. In order to prevent separation of the solder and the substrate.

Description

The solder, the semiconductor package and the method for manufacturing the same

The present invention relates to a solder, a semiconductor package comprising the same, and a manufacturing method thereof.

The circuit board includes a circuit pattern on an electrically insulating substrate, and is a substrate for mounting electronic components or the like.

1 is a cross-sectional view of a conventional printed circuit board.

Referring to FIG. 1, a pad 3 is formed on the insulating layer 1 of the printed circuit board 10 by being connected to the circuit pattern 2. The pad 3 may have various shapes according to the type of the component mounted or connected thereto.

The pad 3 may be exposed by the opening 5 of the solder resist 4 and adhered to the solder balls 6 to mount the device, and may be wire bonded.

The pad 3 is generally formed simultaneously with the circuit pattern 2 by patterning a copper foil layer formed on the insulating layer 1.

Meanwhile, various surface treatment methods have been proposed to prevent oxidation and corrosion of the pad 3.

The embodiment proposes a solder of a new semiconductor package.

The embodiment provides a semiconductor package and a method for manufacturing the same, including a solder having a strong adhesion with a new surface treatment layer.

The example proposes a lead-free solder consisting of an alloy having a composition comprising up to 3.0 wt% silver, 0.5 to 1 wt% copper, and excess tin.

On the other hand, the semiconductor package according to the embodiment is a printed circuit board including a pad and a circuit pattern, a metal layer including at least one layer on the pad, is attached on the metal layer, silver 3.0 wt% or less, copper 0.5 to 1 wt% or less And a lead-free solder made of an alloy having a composition including excess tin, and at least one semiconductor device mounted on the printed circuit board through the lead-free solder.

Meanwhile, the method of manufacturing a semiconductor package according to the embodiment may include preparing an insulating plate on which a circuit pattern and a pad are formed, and non-plating an alloy containing nickel on the circuit pattern or the pad to form the first metal layer. Step, non-plating an alloy containing palladium on the first metal layer to form a second metal layer, Non-plating an alloy containing gold on the second metal layer to form a third metal layer, Forming a lead-free solder comprising 3.0 wt% or less of silver, 0.5 to 1 wt% of copper, and excess tin on the metal layer, and reflowing and bonding the lead-free solder to the semiconductor device.

According to the present invention, with respect to the surface treatment of forming the electroless nickel alloy layer-palladium alloy layer-gold alloy layer on a copper pad, the thickness of the metal bonding layer can be reduced by changing the composition of the solder, and the cracks are formed in the metal bonding layer. It can occur in the solder and prevent separation of the solder and the substrate.

1 is a cross-sectional view of a conventional printed circuit board.
2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.
3 through 10 are cross-sectional views illustrating a method for manufacturing the semiconductor package of FIG. 2.
FIG. 11 is a cross-sectional view illustrating the metal bonding layer formed in FIG. 10.
12a and 12b are cross-sectional views showing a metal bonding layer of the control group for the present invention.
FIG. 13 is a graph illustrating drop characteristics according to the composition of solder in the printed circuit board of FIG. 2.
14 is a photograph of a metal bonding layer according to each composition of FIG. 13.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise.

In order to clearly illustrate the present invention in the drawings, thicknesses are enlarged in order to clearly illustrate various layers and regions, and parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification .

Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. On the contrary, when a part is "just above" another part, there is no other part in the middle.

The present invention provides a composition of a solder having excellent adhesion to a surface treatment for forming a non-electrolytic nickel alloy layer-palladium alloy layer-gold alloy layer on a copper base layer with respect to a circuit pattern.

Hereinafter, a semiconductor package according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2 to 10.

2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 2, the semiconductor package according to the embodiment of the present invention may include an insulating plate 110, a base pad 120 connected to a circuit pattern 125 formed on the insulating plate 110, and the circuit pattern ( The printed circuit board 100 including the solder resist 140 covering the 125, the semiconductor device 200, and the base pad 120 of the printed circuit board 100 and the solder bonding the semiconductor device 200 to each other ( 170).

The insulating plate 110 may be a supporting substrate of a semiconductor package in which a single circuit pattern is formed, but may mean an insulating layer region in which one circuit pattern (not shown) is formed among semiconductor packages having a plurality of stacked structures. have.

When the insulating plate 110 means one insulating layer among a plurality of stacked structures, a plurality of circuit patterns (not shown) may be continuously formed on the upper or lower portion of the insulating plate 110.

The insulation plate 110 may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate, or a glass fiber impregnated substrate. When the insulation plate 110 includes a polymer resin, the insulation plate 110 may include an epoxy-based insulation resin. It may alternatively include polyimide resin.

A plurality of base pads 120 connected to the plurality of circuit patterns 125 are formed on the insulating plate 110. The base pad 120 refers to a base pad 120 to which the solder 170 is attached as a bump for mounting the semiconductor device 200 to be mounted.

The circuit pattern 125 and the base pad 120 may be formed of a conductive material, and may be formed by simultaneously patterning a copper foil layer formed on the insulating plate 110. Therefore, the circuit pattern 125 and the base pad 120 may be formed of an alloy including copper, and roughness may be formed on a surface thereof.

The first metal layer 130 is formed on the top and side surfaces of the circuit pattern 125 and the base pad 120.

The first metal layer 130 is a nickel alloy layer containing nickel (Ni), and roughness is formed on a surface thereof.

The first metal layer 130 may be formed of only nickel, or may include nickel, and may be formed of an alloy with P (phosphorus), B (boron), W (tungsten), or Co (cobalt), 1 to 10 μm. Has a thickness of.

A solder resist 140 is formed on the insulating plate 110 to cover the circuit pattern 125.

The solder resist 140 protects the surface of the insulating plate 110 and is formed on the front surface of the insulating plate 110, and the upper surface of the base pad 120 stacked structure to be exposed, that is, the first metal layer 130. It has an opening 145 to open it.

The second metal layer 150 extending to the side surface of the opening 145 is formed on the first metal layer 130.

The second metal layer 150 may be formed of an alloy containing palladium. The second metal layer 150 may have a thickness of 0.03 to 0.15 μm, and may form an alloy with P (phosphorus), B (boron), W (tungsten), or Co (cobalt).

The third metal layer 160 is formed on the second metal layer 150.

In this case, the third metal layer 160 is an alloy layer containing gold (Au), and forms a thin film having a thin thickness of 0.03 to 0.15 μm.

Solder 170 is formed on the third metal layer 160 on the exposed base pad 120 and attached to the semiconductor device 200.

As such, the semiconductor package which performs the surface treatment (ENEPIG: elctroless Ni, elctroless Pd, inversion Au) in which the nickel alloy layer-palladium alloy layer-gold alloy layer is stacked on the base pad 120 has the surface treatment and adhesive property. Improved solder 170.

Solder 170 of the present invention is a lead-free solder, made of an alloy containing silver (Ag) 3.0% by weight or less, copper (Cu) 0.05 to 1% by weight and extra tin (Sn).

Silver (Ag) constituting the lead-free solder 170 is used for the purpose of increasing the resistance and strength of the thermal stress of the solder 170 to be formed and at the same time increase the ductility.

Copper (Cu) constituting the lead-free solder 170 serves to improve the tensile strength of the solder 170 to be formed to impart resistance to the mechanical impact. Tin (Sn) constituting the lead-free solder 170 lowers the melting point of the bonded base material, and is an element having a great influence on the manufacturing cost of the alloy. If the content is too high or too small, the melting point of the solder 170 is increased. Its quality deteriorates during reflow and adversely affects the durability of parts.

Preferably, the solder 170 may comprise 3.0 weight percent silver, 0.5 weight percent copper and extra tin.

The lead-free solder 170 made of an alloy having the above-described composition improves the surface treatment, adhesion, and mechanical properties of the electroless nickel alloy layer-palladium alloy layer-gold alloy layer on the base pad 120 of the copper base, which will be described later. Do it.

Lead-free solder 170 made of an alloy having the above-described composition is processed in the form of bars, spheres, pastes can be used for semiconductor package and electronic device manufacturers.

Hereinafter, a method of manufacturing the semiconductor package of FIG. 2 will be described with reference to FIGS. 3 to 10.

First, as shown in FIG. 3, the insulating plate 110 is prepared, and a conductive layer (not shown) is stacked on the insulating plate 110. When the insulating plate 110 is an insulating layer, the insulating layer and the conductive layer are laminated. The structure may be a conventional copper clad laminate (CCL).

The conductive layer is etched to form the base pad 120 and the circuit pattern 125.

Next, non-plating is performed on the patterned base pad 120 and the circuit pattern 125 to form the first plating layer 135 of FIG. 4.

The first plating layer 135 may be formed of an alloy of nickel (Ni) and phosphorus (P), and the first plating layer 135 may include 3 to 10 w% of phosphorus (P).

Next, as shown in FIG. 5, the first plating layer 135 is etched to cover the circuit pattern 125 or the base pad 120 to form the first metal layer 130, and the first on the base pad 120 is formed. The solder resist 140 of FIG. 6 is formed to have an opening 145 that opens the first metal layer 130.

Next, as shown in FIG. 7, a mask 180 is formed on the solder resist 140 on which the first metal layer 130 is exposed.

The mask 180 may include a window 185 that opens the opening 145 of the solder resist 140, and may be formed of a photoresist or a dry film.

In this case, the width of the window 185 may be larger than the width of the opening 145 of the solder resist 140.

The second metal layer 160 is formed by performing non-plating on the first metal layer 130 exposed by the window 185.

In this case, before forming the second metal layer 160, a desmear process may be performed to provide roughness to a part of the side surface and the upper surface of the opening 145 of the solder resist 140.

The second metal layer 160 may be formed of an alloy containing palladium. The second metal layer 160 has a thickness of 0.03 to 0.15 μm, and may form an alloy with P (phosphorus), B (boron), W (tungsten), or Co (cobalt).

Next, as shown in FIG. 8, the third metal layer 170 is formed by performing non-plating on the second metal layer 160 exposed through the window 185.

In this case, before forming the third metal layer 170, roughness may be applied to the side surface of the opening 145 of the solder resist 140 and the top surface of the second metal layer 160.

The third metal layer 170 is an alloy layer containing gold (Au), and forms a thin film having a thin thickness of 0.03 to 0.15 μm with non-plating.

Next, a lead-free solder paste 175 made of an alloy containing silver (Ag) 3.0 wt% or less, copper (Cu) 0.05 to 1 wt%, and excess tin (Sn) is prepared.

The lead-free solder paste 175 is coated on the third metal layer 160 in the window 185 as shown in FIG. 9, and then reflow heat treatment is performed to form the solder 170 of FIG. 10.

Finally, the mask 180 may be removed and attached to the semiconductor device 200 to complete the semiconductor package of FIG. 3.

In the above description, the solder 170 is used in the form of a paste. Alternatively, the solder 170 may be implemented in the form of a bar or a ring.

A spherical solder 170 may be formed by the reflow, and an intermetallic contact (IMC) may be formed by diffusion of the lower base pad 120.

Hereinafter, the formation of the metal bonding layer by reflow of the present invention and the control will be described with reference to FIGS. 11 to 12B.

FIG. 11 is a cross-sectional view illustrating the metal bonding layer generated in FIG. 10, and FIGS. 12A and 12B are cross-sectional views illustrating the metal bonding layer of the control group of the present invention.

As shown in FIG. 11, when a nickel alloy layer-palladium alloy layer-gold alloy layer is formed on the base pad 120 of copper of FIG. 10 and reflowed with the lead-free solder 170, the palladium alloy layer on the nickel alloy layer The gold alloy layer is melted and mixed with the solder paste 175 to have no layered structure.

Therefore, the nickel alloy layer 130a and the metal bonding layer 150a are formed between the copper base pad 120 and the solder 170.

At this time, the nickel alloy layer 130a does not diffuse, maintains a layered structure, and the copper on the nickel alloy layer 130a is thermally diffused to the solder side so that the metal-bonded layer 150a of the copper-tin alloy is deposited on the nickel alloy layer 130a. ).

This metal junction forms a Cu 6 Sn 5 layer or a Cu 3 Sn 4 layer.

FIG. 12A illustrates a control (ENIG: ellectroless Ni, immersion Au) of the present invention, in which an electroless nickel alloy layer-gold alloy layer is formed on a copper base pad 220 and reflowed with solder. In FIG. 12A, the gold alloy layer is melted with the solder during reflow to have no layered structure, the nickel alloy layer 230a is partially retained, and the lower copper is diffused together with nickel to form (Ni, Cu) 3 Sn 4 . A metal bonding layer 270 having a composition is formed.

In this case, the metal bonding layer 270 is formed to be thicker with respect to the metal bonding layer 150a of FIG. 11, and the thickness of the nickel alloy layer 230a is also about 2.5 times thicker.

FIG. 12B is another control (OSP: organic solderability preservative) of the present invention, which is OSP-treated on a copper base pad 320 and then reflowed with solder, and has a Cu 6 Sn 5 layer and a Cu 3 layer on the copper base pad 320. It can be seen that the metal bonding layer 250a of the Sn layer is formed thick, and the void 350a is formed between the metal bonding layer 350a and the copper base pad 320.

Hereinafter, the drop impact test conducted on the semiconductor package of FIG. 11 will be described with reference to FIGS. 13 and 14.

Experimental Example 1

A flexible solder (Sn-Pb) containing tin and lead is applied to a substrate including a copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer, and the nickel alloy layer has a thickness of 3 μm and a palladium thickness of 0.03 μm, A semiconductor package in which the thickness of the gold alloy layer was 0.03 μm was prepared.

 Experimental Example 2

A flexible solder (Sn-Pb) containing tin and lead is applied to a substrate including a copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer, and the nickel alloy layer has a thickness of 6 μm and a palladium thickness of 0.1 μm. A semiconductor package was prepared when the thickness of the alloy layer was 0.1 μm.

Experimental Example 3

A flexible solder (Sn-Pb) containing tin and lead is applied to a substrate including a copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer, and the nickel alloy layer has a thickness of 7 μm and a palladium thickness of 0.03 μm, A semiconductor package in which the thickness of the gold alloy layer was 0.03 μm was prepared.

Experimental Example 4

The thickness of the nickel alloy layer was applied to a substrate including a copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer by a lead-free solder (SAC305) containing 3% by weight of silver, 0.5% by weight of copper, and excess tin. The semiconductor package was produced when 3 micrometers, a palladium thickness is 0.03 micrometer, and a gold alloy layer thickness is 0.03 micrometer.

Experimental Example 5

The thickness of the nickel alloy layer was applied to a substrate including a copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer by a lead-free solder (SAC305) containing 3% by weight of silver, 0.5% by weight of copper, and excess tin. 6 micrometers, the palladium thickness is 0.1 micrometer, and the gold alloy layer thickness is 0.1 micrometer, The semiconductor package was produced.

Experimental Example 6

The thickness of the nickel alloy layer was applied to a substrate including a copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer by a lead-free solder (SAC305) containing 3% by weight of silver, 0.5% by weight of copper, and excess tin. The semiconductor package was produced when the thickness was 7 μm, the palladium thickness was 0.03 μm, and the gold alloy layer thickness was 0.03 μm.

Experimental Example 7

The thickness of the nickel alloy layer is applied to a substrate including a copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer by a lead-free solder (SAC302) containing 3% by weight of silver, 0.2% by weight of copper, and excess tin. The semiconductor package was produced when 3 micrometers, a palladium thickness is 0.03 micrometer, and a gold alloy layer thickness is 0.03 micrometer.

Experimental Example 8

The thickness of the nickel alloy layer is applied to a substrate including a copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer by a lead-free solder (SAC302) containing 3% by weight of silver, 0.2% by weight of copper, and excess tin. 6 micrometers, the palladium thickness is 0.1 micrometer, and the gold alloy layer thickness is 0.1 micrometer, The semiconductor package was produced.

Experimental Example 9

The thickness of the nickel alloy layer is applied to a substrate including a copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer by a lead-free solder (SAC302) containing 3% by weight of silver, 0.2% by weight of copper, and excess tin. The semiconductor package was produced when the thickness was 7 μm, the palladium thickness was 0.03 μm, and the gold alloy layer thickness was 0.03 μm.

Experimental Example 10

The lead-free solder (SAC1205) containing 1.2% by weight of silver, 0.5% by weight of copper, and extra tin was applied to the substrate including the copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer, and the thickness of the nickel alloy layer The semiconductor package was produced when 3 micrometers, a palladium thickness is 0.03 micrometer, and a gold alloy layer thickness is 0.03 micrometer.

Experimental Example 11

The lead-free solder (SAC1205) containing 1.2% by weight of silver, 0.5% by weight of copper, and extra tin was applied to the substrate including the copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer, and the thickness of the nickel alloy layer 6 micrometers, the palladium thickness is 0.1 micrometer, and the gold alloy layer thickness is 0.1 micrometer, The semiconductor package was produced.

Experimental Example 12

The lead-free solder (SAC1205) containing 1.2% by weight of silver, 0.5% by weight of copper, and extra tin was applied to the substrate including the copper base pad-nickel alloy layer-palladium alloy layer-gold alloy layer, and the thickness of the nickel alloy layer The semiconductor package was produced when the thickness was 7 μm, the palladium thickness was 0.03 μm, and the gold alloy layer thickness was 0.03 μm.

Experiment result

FIG. 13 is a graph showing drop impact characteristics according to solder composition in the printed circuit board of FIG. 2, and FIG. 14 is a photograph of metal bonding layers according to experimental examples.

The drop impact test was repeatedly performed to determine whether the semiconductor packages of Experimental Examples 1 to 12 were defective due to the impact generated by dropping the semiconductor packages toward the ground, specifically, cracks in the solder or metal bonding layer. The number of drops to be determined is shown in FIG.

As described above, the nickel alloy layer-palladium alloy layer-gold alloy layer formed on the copper base pad has a solder composition of SAC305, that is, 3 wt% silver, 0.5 wt% copper and extra tin regardless of the thickness of each layer. The eggplants were found to have the highest resistance to impact.

These values were observed higher than when the flexible solders of Experimental Examples 1 to 3 were formed, and as shown in FIGS. 12A and 12B, they showed higher suitability than nickel-gold plating or OSP treatment.

Referring to FIG. 14, in the surface treatment of the nickel alloy layer-palladium alloy layer-gold alloy layer, it can be seen that cracks are observed in the solder together with the case where the solder composition is SAC305.

Therefore, when cracks are generated in the metal bonding layer, such as SAC302, it is very vulnerable to dropping impact and the solder and the pad are separated. In the case of SAC1205, cracks are irregularly formed according to the thickness of the surface treatment layer, so that the reliability is high. It can be seen that it is not secured.

In the above experiments, when the surface treatment of the nickel alloy layer-palladium alloy layer-gold alloy layer is formed on the copper base pad as in the embodiment of the present invention, the solder is less than 3% by weight of silver, 0.5% by weight of copper and extra tin. In the case of the composition, it can be seen that the rigidity is the most excellent.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Printed Circuit Board 100
Insulation Plate 110
Circuit pattern 125
Pad 120

Claims (11)

delete delete delete A printed circuit board comprising a pad and a circuit pattern,
Nickel alloy layer containing nickel on the pad,
A solder resist exposing the nickel alloy layer on an upper surface of the pad;
A palladium alloy layer formed on the exposed nickel alloy layer and extending to an upper surface of the solder resist;
A gold alloy layer formed on the palladium alloy layer and including gold,
A lead-free solder adhered to the gold alloy layer, the lead-free solder consisting of an alloy having a composition including not more than 3.0 wt% silver, 0.5-1 wt% copper, and excess tin, and
At least one semiconductor device mounted on the printed circuit board through the lead-free solder
Semiconductor package comprising a.
delete The method of claim 4, wherein
The nickel alloy layer is 1 to 10 μm,
The palladium alloy layer is 0.03 to 0.15μm, and
The gold alloy layer has a thickness that satisfies 0.03 to 0.15μm. The method of claim 4, wherein
The nickel alloy layer, the palladium alloy layer and the gold alloy layer is formed by a non-plating semiconductor package. The method of claim 4, wherein
The lead-free solder comprises 3.0 wt% silver, 0.5 wt% copper and extra tin. Preparing an insulating plate on which circuit patterns and pads are formed,
Non-plating an alloy containing nickel on the circuit pattern or pad to form a first metal layer,
Forming a solder resist exposing the top surface of the first metal layer,
Non-plating an alloy including palladium on the exposed first metal layer and on the solder resist to form a second metal layer,
Non-plating an alloy containing gold on the second metal layer to form a third metal layer,
Forming a lead-free solder comprising less than or equal to 3.0 wt% silver, 0.5 to 1 wt% copper and excess tin on the third metal layer, and
Reflowing the lead-free solder to bond the semiconductor device
Method of manufacturing a semiconductor package comprising a. 10. The method of claim 9,
The first to third metal layers are formed of an alloy with P (phosphorus), B (boron), W (tungsten) or Co (cobalt). 10. The method of claim 9,
Wherein the lead-free solder comprises 3.0 weight percent silver, 0.5 weight percent copper and excess tin.
KR1020100084592A 2010-08-31 2010-08-31 The solder, the semiconductor package and the method for manufacturing the same KR101154562B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100084592A KR101154562B1 (en) 2010-08-31 2010-08-31 The solder, the semiconductor package and the method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100084592A KR101154562B1 (en) 2010-08-31 2010-08-31 The solder, the semiconductor package and the method for manufacturing the same

Publications (2)

Publication Number Publication Date
KR20120020765A KR20120020765A (en) 2012-03-08
KR101154562B1 true KR101154562B1 (en) 2012-06-08

Family

ID=46129301

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100084592A KR101154562B1 (en) 2010-08-31 2010-08-31 The solder, the semiconductor package and the method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR101154562B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102106076B1 (en) * 2012-11-30 2020-04-29 삼성전자주식회사 Power Semiconductor Device

Also Published As

Publication number Publication date
KR20120020765A (en) 2012-03-08

Similar Documents

Publication Publication Date Title
KR101317019B1 (en) Soldering method and related device for improved resistance to brittle fracture
CN106165554B (en) Printed circuit board, package substrate and manufacturing method thereof
US8022530B2 (en) Package substrate having electrically connecting structure
US9883586B2 (en) Wiring substrate for bonding using solder having a low melting point and method for manufacturing same
US8368234B2 (en) Semiconductor device, production method for the same, and substrate
WO2005117112A1 (en) Lead frame for semiconductor device
KR101897013B1 (en) The printed circuit board and the method for manufacturing the same
KR101103302B1 (en) Printed circuit board and method for manufacturing same
KR101154562B1 (en) The solder, the semiconductor package and the method for manufacturing the same
KR20120012348A (en) The printed circuit board and the method for manufacturing the same
JP4940662B2 (en) Solder bump, method of forming solder bump, and semiconductor device
KR100348126B1 (en) Semiconductor device and outer connecting terminal structured body, and method of manufacturing the semiconductor device
KR101926565B1 (en) The printed circuit board and the method for manufacturing the same
KR101836218B1 (en) The printed circuit board and the method for manufacturing the same
JP5311656B2 (en) Wiring board
US20120280023A1 (en) Soldering method and related device for improved resistance to brittle fracture
KR101241681B1 (en) The coating solution, the printed circuit board and the method for manufacturing the same
KR101125463B1 (en) The printed circuit board and the method for manufacturing the same
CN110634752A (en) Printed circuit board, package substrate including the same, and method of manufacturing the same
US20120118621A1 (en) Printed circuit board and method for manufacturing the same
KR101241639B1 (en) The printed circuit board and the method for manufacturing the same
KR101154783B1 (en) The printed circuit board and the method for manufacturing the same
KR20120012347A (en) The printed circuit board and the method for manufacturing the same
KR101514529B1 (en) Printed circuit board and manufacturing method thereof
KR20120020764A (en) The printed circuit board and the method for manufacturing the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20150506

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20160504

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20170512

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20180509

Year of fee payment: 7

FPAY Annual fee payment

Payment date: 20190514

Year of fee payment: 8