KR101147267B1

KR101147267B1 - Thin Film Transistor Substrate of Horizontal Electronic Fileld and Method of Fabricating the same

Info

Publication number: KR101147267B1
Application number: KR20050121234A
Authority: KR
Inventors: 서영일
Original assignee: 엘지디스플레이 주식회사
Priority date: 2005-12-10
Filing date: 2005-12-10
Publication date: 2012-05-18
Also published as: KR20070061618A

Abstract

The present invention relates to a horizontal field type thin film transistor substrate capable of applying a uniform horizontal electric field to the pixel region and a method of manufacturing the same.

Horizontal field-type thin film transistor substrate according to the present invention comprises a gate line and a common line formed on the lower substrate in parallel; A data line defining a pixel region by crossing the gate line with the gate insulating layer interposed therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A protective film formed on the gate insulating film and covering the thin film transistor; A common electrode connected to the common line through a contact hole passing through the passivation layer and the gate insulating layer; And a pixel electrode connected to the thin film transistor through a contact hole penetrating through the protective film and generating a horizontal electric field together with the common electrode, wherein the common electrode and the pixel electrode are formed in a three-dimensional structure having a predetermined height on the protective film. do.

Description

Thin Film Transistor Substrate of Horizontal Electronic Fileld and Method of Fabricating the same

1 is a plan view illustrating a thin film transistor substrate of a conventional horizontal field application liquid crystal display panel.

FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate taken along line II ′ in FIG. 1.

3 is a diagram showing a horizontal electric field between a pixel electrode and a common electrode constituting a conventional thin film transistor substrate.

4 is a plan view illustrating a horizontal field thin film transistor substrate according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the thin film transistor substrate taken along the line II-II ′ in FIG. 4.

6 illustrates first and second horizontal electric fields formed by a pixel electrode and a common electrode;

7A and 7B are a plan view and a cross-sectional view of a thin film transistor substrate having a first conductive pattern according to the present invention.

8A and 8B are a plan view and a cross-sectional view of a thin film transistor substrate on which a second conductive pattern is formed according to the present invention.

9A to 9E are manufacturing process diagrams of a thin film transistor substrate having a second conductive pattern according to the present invention.

10A and 10B are a plan view and a cross-sectional view of a thin film transistor substrate having a protective film according to the present invention.

11A and 11B are a plan view and a cross-sectional view of a thin film transistor substrate having a third conductive pattern according to the present invention.

12A to 12D are manufacturing process diagrams of a thin film transistor substrate having a third conductive pattern according to the invention.

100: lower substrate 110: gate line

111 gate electrode 120 common line

130: gate insulating film 140: data line

141: source electrode 142: drain electrode

143: active layer 144: ohmic contact layer

150: thin film transistor 160: protective film

161: first contact hole 162: second contact hole

170: pixel electrode 170a: horizontal portion

170b: finger portion 180: common electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal field type thin film transistor substrate and a method of manufacturing the same, and more particularly, to a horizontal field type thin film transistor substrate capable of generating a uniform horizontal electric field in a pixel region and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal display devices are classified into vertical electric field types and horizontal electric field types according to the direction of the electric field for driving the liquid crystal.

In the vertical field type liquid crystal display, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate face each other to drive the liquid crystal of TN (Twisted Nemastic) mode by a vertical electric field formed therebetween. Such a vertical field type liquid crystal display device has a large aperture ratio, but has a narrow viewing angle of about 90 degrees.

In a horizontal field type liquid crystal display, a liquid crystal in an in-plane switch (hereinafter referred to as IPS) mode is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. Such a horizontal field application liquid crystal display device has an advantage that a viewing angle is about 160 degrees. Hereinafter, the horizontal field type liquid crystal display device will be described in detail.

The horizontal field type liquid crystal display device includes a thin film transistor substrate (lower substrate) and a color filter substrate (upper substrate) bonded to each other, a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal space provided by the spacer. It has a liquid crystal.

The thin film transistor substrate is composed of a plurality of signal lines and a thin film transistor for forming a horizontal electric field on a pixel-by-pixel basis, and an alignment film coated thereon for liquid crystal alignment. The color filter substrate is composed of a color filter for color implementation and a black matrix for light leakage prevention, and an alignment film coated thereon for liquid crystal alignment.

FIG. 1 is a plan view illustrating a thin film transistor array substrate of a conventional horizontal field application liquid crystal display panel, and FIG. 2 is a cross-sectional view illustrating a thin film transistor array substrate taken along line II ′ in FIG. 1.

1 and 2, a conventional thin film transistor substrate includes a gate line 2 and a data line 4 intersecting on a lower substrate 45, and a thin film transistor 6 formed at each intersection thereof. And a pixel electrode 14 and a common electrode 18 formed to form a horizontal electric field in the pixel region 5 provided in the intersection structure, and a common line 16 to which the common electrodes 18 are commonly connected.

The gate line 2 transfers a gate signal supplied from a gate driver (not shown) connected to the gate pad to the gate electrode 8 constituting the thin film transistor 6.

The data line 4 transfers a data signal supplied from a data driver (not shown) connected to the data pad to the pixel electrode 14 through the drain electrode 12 constituting the thin film transistor 6. .

In this case, the gate line 2 and the data line 4 are formed in an intersecting structure to define the pixel region 5.

The common line 16 is formed in parallel with the gate line 2 with the pixel region 5 therebetween, and supplies a reference voltage for driving the liquid crystal to the common electrode 18.

The thin film transistor 6 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 14 in response to the gate signal of the gate line 2.

To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode connected to the pixel electrode 14. 12). In addition, the thin film transistor 6 includes a semiconductor layer including an active layer 48 overlapping with the gate electrode 8 and the gate insulating layer 46 therebetween to form a channel between the source electrode 10 and the drain electrode 12. The pattern 49 is further provided.

In this case, the semiconductor pattern 49 further includes an ohmic contact layer 50 positioned on the active layer 48 to make ohmic contact with the data line 4, the source electrode 10, and the drain electrode 12.

The pixel electrode 14 is connected to the drain electrode 12 of the thin film transistor 6 through the contact hole 17 and is formed in the pixel region 5. In particular, the pixel electrode 14 is connected to the drain electrode 12 and has a horizontal portion 14a formed in parallel with the adjacent gate line 2, a second horizontal portion 14b formed to overlap the common line 16, and A finger portion 14c is formed between the first and second horizontal portions 14a and 14b to be parallel to the common electrode 18.

The common electrode 18 is connected to the common line 16 to be formed of the same metal as the gate line 2 and the gate electrode 8 in the pixel region 5. In particular, the common electrode 18 is formed in the pixel region 5 in parallel with the finger portion 14c of the pixel electrode 14.

Accordingly, a horizontal electric field is formed between the pixel electrode 14 supplied with the pixel signal through the thin film transistor 6 and the common electrode 18 supplied with the reference voltage through the common line 16. In particular, a horizontal electric field is formed between the finger portion 14c of the pixel electrode 14 and the common electrode 18.

The horizontal electric field causes liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate to rotate by dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region 5 is changed, thereby realizing an image.

In this case, in the conventional thin film transistor substrate, the finger 14c and the common electrode 18 of the pixel electrode 14 having a planar structure having a height of about 300A ° to 400A ° are formed with the gate insulating film and the protective film interposed therebetween. As shown in FIG. 3, only a parabolic horizontal electric field is applied to the pixel region 5 from the upper surface of the finger portion 14c of the pixel electrode 14 to the upper surface of the common electrode 18.

Therefore, in the conventional thin film transistor substrate, a horizontal electric field is not applied to the horizontal area A (hereinafter, referred to as an "field non-application area") between the finger 14c of the pixel electrode 14 and the common electrode 18. As a result, the liquid crystal molecules do not rotate in the pixel region, thereby decreasing the transmittance and contrast ratio, and deteriorating the image quality due to blackening and black spots during long-term driving at high temperatures.

In addition, in the case of a conventional thin film transistor substrate, a parabolic horizontal electric field penetrates the gate insulating film 46 and the passivation film 52 and is formed on the upper surface of the finger portion 14c of the pixel electrode 14 and the upper surface of the common electrode 18. As a result, the horizontal electric field penetrates through the gate insulating film 46 and the passivation film 52, thereby weakening the electric field strength applied to the pixel region 5.

In order to solve the above problems, an object of the present invention is to form a pixel electrode and a common electrode in parallel on the protective film in a three-dimensional shape, a horizontal field type thin film transistor substrate that can apply a uniform horizontal electric field to the pixel region and It is to provide a manufacturing method.

In order to achieve the above object, the thin film transistor substrate according to the present invention, the gate line and the common line formed on the glass substrate in parallel; A data line defining a pixel region by crossing the gate line with the gate insulating layer interposed therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A protective film formed on the gate insulating film and covering the thin film transistor; A common electrode connected to the common line through a contact hole passing through the passivation layer and the gate insulating layer; And a pixel electrode connected to the thin film transistor through a contact hole penetrating through the protective film and generating a horizontal electric field together with the common electrode, wherein the common electrode and the pixel electrode are formed in a three-dimensional structure having a predetermined height on the protective film. do.

Here, the common electrode and the pixel electrode of the thin film transistor substrate according to the present invention are characterized in that they are formed in parallel to each other in a three-dimensional structure having a height of 1000A ° to 5000A ° on the protective film.

In addition, the pixel electrode of the thin film transistor substrate according to the present invention includes a horizontal portion connected to the thin film transistor and formed in parallel with the gate line; And a finger part connected to the horizontal part and forming a horizontal electric field together with the common electrode, wherein the finger part is formed in parallel with the common electrode on the passivation layer.

In addition, the finger and the common electrode constituting the pixel electrode of the thin film transistor substrate according to the present invention are formed in parallel to each other in a three-dimensional structure having a predetermined height on the protective film, the parabolic shape extending from the upper surface to the upper surface A first horizontal electric field and a second horizontal electric field having a straight line extending from each side to a side are formed.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to the present invention comprises the steps of: forming a gate line and a common line in parallel on the substrate; Forming a data line; Forming a thin film transistor at an intersection of the gate line and the data line; Forming a protective film formed on the gate insulating film to cover the thin film transistor; Forming a common electrode having a three-dimensional structure connected to the common line through a contact hole passing through the passivation layer and the gate insulating layer; And forming a three-dimensional pixel electrode connected to the thin film transistor through a contact hole passing through the passivation layer and forming a horizontal electric field together with the common electrode.

In order to achieve the above object, the method for manufacturing a thin film transistor substrate according to the present invention includes a gate line, a gate electrode connected to the gate line, and a common line formed in parallel with the gate line and the pixel region interposed thereon. Forming a first conductive pattern; Forming a gate insulating film on the substrate on which the first conductive pattern is formed; Forming a semiconductor layer on the gate insulating layer to form a channel and a second conductive pattern including a data line, a source electrode connected to the data line, and a drain electrode facing each other with the source electrode and the channel interposed therebetween; Forming a protective film on the gate insulating film on which the second conductive pattern and the semiconductor layer are formed; And a three-dimensional pixel electrode composed of a horizontal portion parallel to the gate line and a finger portion connected to the horizontal portion on the passivation layer, and a three-dimensional common electrode connected to the common line and forming a horizontal electric field with the finger portion of the pixel electrode. And forming a third conductive pattern.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First, the structure and operation of the horizontal field type thin film transistor substrate according to the present invention will be described with reference to FIGS. 4 and 5.

4 is a plan view illustrating a thin film transistor substrate of a horizontal field type liquid crystal display panel according to the present invention, and FIG. 5 is a cross-sectional view illustrating a thin film transistor substrate taken along line II-II ′ of FIG. 4.

4 and 5, the thin film transistor substrate according to the present invention includes a gate line 110 formed on the lower substrate 100, a common line 120 formed in parallel with the gate line 110, and a gate insulating film. A data line 140 crossing the gate line 110 and the common line 120 with the 130 interposed therebetween, and the thin film transistor 150 formed at each intersection of the gate line 110 and the data line 140. In order to cover the thin film transistor 150, a horizontal electric field is formed in the passivation layer 160 formed on the gate insulating layer 130 and the pixel region 171 provided in a cross structure of the gate line 110 and the data line 140. The formed pixel electrode 170 and the common electrode 180 are provided.

Here, the gate line 110 transmits a gate signal supplied from a gate driver (not shown) connected to the gate pad to the gate electrode 111 constituting the thin film transistor 150.

The common line 120 is formed in parallel with the gate line 110 with the pixel region 171 therebetween and supplies a reference voltage for driving the liquid crystal to the common electrode 180. In this case, the common line 120 is formed for each pixel region 171 parallel to the gate line 110 and passes through the second contact hole 162 passing through the gate insulating layer 130 and the passivation layer 160. 180).

The data line 140 connects a data signal supplied from a data driver (not shown) connected to the data pad with the on / off of the gate electrode 111 to form the thin film transistor 150 and the drain. It serves to transfer to the electrode 142.

In this case, the data line 140 is formed to cross the gate line 110 with the gate insulating layer 130 interposed therebetween to define the pixel region 171 where the pixel electrode 170 is located. Here, the data line 140 is also formed to cross the common line 120 with the gate insulating layer 130 interposed therebetween.

The thin film transistor 150 keeps the pixel signal of the data line 140 charged and maintained in the pixel electrode 170 in response to the gate signal of the gate line 110. To this end, the thin film transistor 150 may include a gate electrode 111 connected to the gate line 110, a source electrode 141 connected to the data line 140, and a first contact hole in the pixel electrode 170. A drain electrode 142 connected through 161 is provided.

In addition, the thin film transistor 150 includes an active layer 143 and an active layer that overlap with the gate electrode 110 and the gate insulating layer 130 therebetween to form a channel between the source electrode 141 and the drain electrode 142. An ohmic contact layer 144 for ohmic contact with the data line 140, the source electrode 141, and the drain electrode 142 is disposed on the 143.

The passivation layer 160 is formed on the gate insulating layer 130 to form moisture or scratches in the active layer 143 and the pixel region 171 which form a channel of the thin film transistor 150 during a subsequent process. Serves to prevent the occurrence of. The protective layer 160 may be formed of an inorganic insulating material such as silicon nitride, or an organic insulating material such as acryl-based organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), and the like. It is deposited on the gate insulating film 130 by PECVD under the process conditions of.

In addition, the passivation layer 160 includes first and second contact holes 161 and 162 formed through a photolithography process using a photoresist pattern, where the first contact hole 161 penetrates the passivation layer 160. The drain electrode 142 and the pixel electrode 170 of the thin film transistor 150 are connected to each other, and the second contact hole 162 passes through the passivation layer 160 and the gate insulating layer 130 to form a common line on the lower substrate 100. The 120 and the common electrode 180 are connected.

The pixel electrode 170 is connected to the drain electrode 142 of the thin film transistor 150 through the first contact hole 161 passing through the passivation layer 160 and is formed in the pixel region 171. In this case, the pixel electrode 170 is formed on the lower substrate 100 to be parallel to the gate line 110, and is connected to the horizontal part 170a to be parallel to the common electrode 180. A finger portion 170b for generating a horizontal electric field is provided.

The common electrode 180 is connected to the common line 120 of the lower substrate 100 through the second contact hole 162 penetrating through the passivation layer 160 and the gate insulating layer 130 to provide a reference voltage for driving the liquid crystal. do. In this case, the common electrode 180 is formed of the same transparent conductive material as that of the finger portion 170b of the pixel electrode 170, and has a three-dimensional structure having a predetermined height on the passivation layer 160 in parallel with the finger portion 170b. Is formed.

As described above, the thin film transistor substrate according to the present invention may include a pixel electrode 170 to which a pixel signal is supplied through the thin film transistor, more specifically, a finger 170b and a common line 120 of the pixel electrode 170. A horizontal electric field is formed between the common electrodes 180 to which the reference voltage is supplied.

In this case, the finger portion 170b and the common electrode 180 of the pixel electrode 170 are formed in parallel with each other in a three-dimensional structure having a height of about 1000 A ° to 5000 A ° on the passivation layer 160, thereby being shown in FIG. 6. As described above, the horizontal electric field formed by the finger portion 170b and the common electrode 180 of the pixel electrode 17 is not only a parabolic first horizontal electric field extending from the upper surface to the upper surface, but also from each side to the side. A subsequent straight second horizontal electric field is formed.

Accordingly, a sufficient horizontal electric field is applied to the region where the conventional horizontal electric field is not applied due to the second horizontal electric field extending to the side of the finger portion 170b and the common electrode 180 of the pixel electrode 170, thereby providing a liquid crystal molecule. The horizontal electric field is uniformly applied to the oriented pixel region to improve the transmittance and contrast ratio.

In addition, since the finger portion 170b and the common electrode 180 of the pixel electrode 170 are formed on the passivation layer 160, the horizontal electric field is not weakened by the passivation layer 160 and the gate insulating layer 130. Accordingly, a strong horizontal electric field is applied to the pixel region 171 to drive at a low voltage.

Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention will be described with reference to the accompanying drawings.

First, a process of forming the first conductive pattern of the thin film transistor substrate according to the present invention will be described with reference to FIGS. 7A and 7B. 7A and 7B are a plan view and a cross-sectional view illustrating a method of manufacturing a first conductive pattern of a thin film transistor substrate according to the present invention.

7A and 7B, a first conductive pattern including a gate line 110, a gate electrode 111, and a common electrode is formed on the lower substrate 100.

In detail, the gate metal layer is formed on the lower substrate 100 through a deposition method such as stuttering. Here, the gate metal layer is formed in at least one layer structure including aluminum (Al) -based metal, copper (Cu), chromium (Cr), molybdenum and the like. For example, the gate metal layer is formed in a two-layer structure in which aluminum / neodium (AlNd) and molybdenum (Mo) are sequentially stacked.

Subsequently, the gate metal layer is patterned on the lower substrate 100 by patterning the gate metal layer through a photolithography process and an etching process using a mask, thereby including a gate line 110, a gate electrode 111, and a common line 120. 1 A conductive pattern is finally formed.

After the first conductive pattern is formed on the lower substrate 100 as described above, as shown in FIGS. 8A and 8B, the second conductive pattern and the second conductive pattern are formed on the gate insulating layer 120 using the second mask process. A semiconductor pattern is formed. 8A and 8B are plan and cross-sectional views illustrating a method of manufacturing a second conductive pattern and a semiconductor pattern of a thin film transistor substrate according to the present invention.

8A and 8B, the gate insulating layer 130 is coated on the lower substrate 100 on which the first conductive pattern is formed. A semiconductor pattern including an active layer 143 and an ohmic contact layer 144 on the gate insulating layer 130 using a second mask process; A second conductive pattern including the data line 140, the source electrode 141, and the drain electrode 142 is formed.

In detail, as illustrated in FIG. 9A, the first semiconductor layer 143 ′, the second semiconductor layer 144 ′, and the source / drain are deposited on the gate insulating layer 130 by a deposition method such as PECVD or sputtering. The metal layer 140 'is sequentially formed.

Here, amorphous silicon without impurities are used as the first semiconductor layer 143 ′, and amorphous silicon doped with N type or P type impurities is used as the second semiconductor layer 144 ′. The source / drain metal layer 140 ′ is made of a metal such as molybdenum (Mo), copper (Cu), or the like.

Subsequently, as shown in FIG. 9B, after forming the photoresist on the source / drain metal layer 130 ′, the second masks 200 are aligned at predetermined intervals. Here, the second mask 200 includes a mask substrate 210 made of a transparent material, an exposure part 210 formed in an exposure area of the mask substrate, a blocking part 220 and a mask formed in a blocking area of the mask substrate 210. The diffraction exposure part 230 (or semi-transmissive part) formed in the partial exposure area | region of the board | substrate 210 is provided.

The photoresist is exposed and developed by using the second mask 200 to have a step in the blocking region and the partial exposure region corresponding to the blocking portion 220 and the diffraction exposure portion 230 of the second mask 200. The photoresist pattern 240 is formed. That is, the photoresist pattern 240 having the partial exposure region has a second height h2 that is lower than the photoresist pattern 240 having the first height h1 formed in the blocking region.

As the source / drain metal layer 140 ′ is patterned by a wet etching process using the photoresist pattern 240 as a mask, as illustrated in FIG. 9C, a source connected to the data line 140 and the data line 140. A second conductive pattern including a drain electrode 142 facing the source electrode 141 with the electrode 141 and the channel interposed therebetween is formed.

The source / drain metal layer 140 ′, the first semiconductor layer 143 ′, and the second semiconductor layer 144 ′ formed on the channel are sequentially etched using the photoresist pattern 240 as a mask, FIG. 9D. As shown in FIG. 2, a semiconductor layer including a source electrode 141 and a drain electrode 142 facing each other with a channel interposed therebetween, an active layer 143 forming the channel, and an ohmic contact layer 144 is formed.

Subsequently, by removing the photoresist pattern 240 remaining in the second conductive pattern through the strip process, as shown in FIG. 9E, the data line 140 and the data line 140 are formed on the gate insulating layer 120. The active layer 143 and the ohmic contact layer 144 forming the channel and the second semiconductor pattern including the connected source electrode 141 and the drain electrode 142 facing each other with the channel interposed between the source electrode 141 and the source electrode 141 are formed. A semiconductor layer is formed.

After the second conductive pattern and the semiconductor layer are formed on the gate insulating layer 130 as described above, as shown in FIGS. 10A and 10B, the first and second contact holes 161 and 162 are formed on the gate insulating layer 130. A protective film 160 including the () is formed. 10A and 10B are plan and cross-sectional views illustrating a method of forming the passivation layer 160 of the thin film transistor substrate according to the present invention.

10A and 10B, the passivation layer 160 is deposited on the gate insulating layer 130 on which the first conductive pattern is formed through a deposition method such as PECVD. In this case, the passivation layer 160 may be formed of an inorganic insulating material such as the gate insulating film 130, an organic insulating material such as an acryl-based organic compound having a low dielectric constant, (Benzocyclobutene), or perfluorocyclobutene (PFCB).

Thereafter, the passivation layer 130 is patterned by a photolithography process and an etching process to form first and second contact holes 161 and 162.

Here, the first contact hole 161 passes through the passivation layer 160 to connect the drain electrode 142 and the pixel electrode 180 of the thin film transistor 150, and the second contact hole 162 forms the passivation layer 160. The common electrode 180 is connected to the common line 120 formed on the lower substrate 100 through the gate insulating layer 130.

After the passivation layer 160 is formed on the gate insulating layer 130 as described above, as shown in FIGS. 11A and 11B, the pixel electrode 170 having the horizontal portion 170a and the finger portion 170b is common. A third conductive pattern including the electrode 180 is formed. 11A and 11B are a plan view and a cross-sectional view illustrating a method of forming a third conductive pattern of a thin film transistor substrate according to the present invention.

11A and 11B, a transparent conductive film is formed on the gate insulating film 130. In addition, the projection layer is patterned through a third mask process so that the pixel includes a horizontal portion 170a parallel to the gate line 110 and a horizontal portion 170a and a finger portion 170b parallel to the data line 140. The common electrode 180 is connected to the common line 120 through the electrode 170 and the second contact hole 162 and formed in parallel with the finger portion 170b of the pixel electrode 170 to form a horizontal electric field. A third conductive pattern is formed.

In more detail, as illustrated in FIG. 12A, the transparent conductive film 170 ′ is formed on the protective film by a deposition method such as sputtering. Herein, the material of the transparent conductive layer 170 ′ may be indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (Indium). Tin Zinc Oxide (ITZO) and the like.

Thereafter, as shown in FIG. 12B, after the photoresist is formed on the transparent conductive film 170 ′, the third mask 300 is aligned at a predetermined interval. Here, the third mask 300 includes a mask substrate 310 made of a transparent material, an exposure part 320 formed in the exposure area of the mask substrate, and a blocking part 330 formed in the blocking area of the mask substrate 310. do.

Thereafter, as shown in FIG. 12C, the photoresist is patterned using a third mask to form the photoresist pattern 340 on the transparent conductive film 170 ′.

Next, by performing an etching process on the exposed transparent conductive film 170 ′ using the photoresist pattern 340, as shown in FIG. 12D, the horizontal portion 170a of the pixel electrode 170 is horizontal. The common electrode 180 connected to the common line 120 through the finger portion 170b and the second contact hole 162 extending from the portion 170a to the pixel region 171 and parallel to the finger portion 170b. A third conductive pattern including the) is formed.

At this time, the finger portion 170b and the common electrode 180 of the pixel electrode 170 are formed on the passivation layer 160 in parallel to each other in a three-dimensional structure having a predetermined height, more specifically, 1000A ° to 5000A °. 6, the horizontal electric field formed by the finger portion 170b and the common electrode 180 of the pixel electrode 170 is not only a parabolic first horizontal electric field extending from the upper surface to the upper surface. On each side a straight horizontal second electric field is formed which runs from side to side.

Accordingly, a uniform horizontal electric field is applied to the pixel region due to the second horizontal electric field extending from the finger portion 170b of the pixel electrode 170 to the side surface of the common electrode 180, thereby transmitting a transmittance and contrast ratio of the pixel region. This is improved.

In addition, the finger 170b and the common electrode 180 of the pixel electrode 170 are simultaneously formed on the passivation layer 160, whereby the horizontal electric field is not weakened by the passivation layer 160 and the gate insulating layer 130. A strong horizontal electric field is applied to the pixel region 171.

As described above, the horizontal field type thin film transistor substrate and the method of manufacturing the same according to the present invention form a pixel electrode and a common electrode in parallel with each other in a three-dimensional structure having a predetermined height on the protective film, thereby making the horizontal electric field uniform in the pixel region. It has the effect of improving the transmittance and contrast ratio by applying.

In addition, the present invention has the effect that the horizontal electric field can be applied to the pixel region without being weakened by the protective film and the gate insulating film by forming the pixel electrode and the common electrode in parallel on the protective film at the same height.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims

A gate line and a common line formed on the lower substrate in parallel;

A data line defining a pixel region by crossing the gate line with a gate insulating layer interposed therebetween;

A thin film transistor formed at an intersection of the gate line and the data line;

A passivation layer formed on the gate insulating layer and covering the thin film transistor;

A common electrode connected to the common line through a contact hole penetrating through the passivation layer and the gate insulating layer; And

A pixel electrode connected to the thin film transistor through a contact hole penetrating through the passivation layer and generating a horizontal electric field together with the common electrode;

The common electrode and the pixel electrode are formed in a three-dimensional structure having a predetermined height on the protective film.

The method of claim 1,

The common electrode and the pixel electrode are formed on the passivation layer in parallel with each other in a three-dimensional structure having a height of 1000A ° to 5000A °.

The method of claim 1, wherein the pixel electrode,

A horizontal portion connected to the thin film transistor and formed in parallel with the gate line; And

A finger part connected to the horizontal part and forming a horizontal electric field together with the common electrode;

And the finger portion is formed in parallel with the common electrode on the passivation layer.

The method of claim 3,

The thin film transistor substrate of claim 1, wherein the finger portion and the common electrode of the pixel electrode form a parabolic first horizontal electric field extending from an upper surface to an upper surface and a second horizontal electric field extending from a side surface to a side surface.

Forming a gate line and a common line in parallel on the substrate;

Forming a data line crossing the gate line with a gate insulating layer interposed therebetween to define a pixel area;

Forming a thin film transistor at an intersection of the gate line and the data line;

Forming a passivation layer formed on the gate insulating layer to cover the thin film transistor;

Forming a common electrode having a three-dimensional structure connected to a common line through a contact hole passing through the passivation layer and the gate insulating layer; And

Forming a three-dimensional pixel electrode connected to the thin film transistor through a contact hole passing through the passivation layer and forming a horizontal electric field together with the common electrode;

Method of manufacturing a thin film transistor substrate comprising a.

The method of claim 5,

And the common electrode and the pixel electrode are formed in parallel with each other in a three-dimensional structure having a height of 1000 A to 5000 A on the passivation layer.

The method of claim 5, wherein the forming of the pixel electrode comprises:

Forming a horizontal portion connected to the thin film transistor and in balance with the gate line; And

Forming a finger part connected to the horizontal part and forming a horizontal electric field together with the common electrode;

And the finger portion is formed parallel to the common electrode on the passivation layer.

The method of claim 7, wherein

The finger portion and the common electrode of the pixel electrode form a parabolic first horizontal electric field extending from an upper surface to an upper surface of the pixel electrode and a second horizontal electric field having a linear shape extending from side to side. Manufacturing method.

Forming a first conductive pattern on the substrate, the first conductive pattern including a gate line, a gate electrode connected to the gate line, and a common line formed in parallel with the gate line and the pixel region interposed therebetween;

Forming a gate insulating film on the substrate on which the first conductive pattern is formed;

Forming a second conductive pattern including a data line, a source electrode connected to the data line, a drain electrode facing each other with the source electrode and a channel interposed therebetween, and a semiconductor layer forming the channel on the gate insulating layer;

Forming a protective film on the gate insulating film on which the second conductive pattern and the semiconductor layer are formed; And

A three-dimensional pixel electrode composed of a horizontal portion parallel to a gate line and a finger portion connected to the horizontal portion on the passivation layer, and a three-dimensional common electrode connected to the common line and forming a horizontal electric field with a finger portion of the pixel electrode; Forming a third conductive pattern comprising

Method of manufacturing a thin film transistor substrate comprising a.

The method of claim 9, wherein the forming of the protective film,

Applying a protective film on the gate insulating film;

Forming a photoresist pattern by applying a photoresist on the passivation layer and then performing a photolithography process;

Etching the passivation layer exposed by the photoresist pattern to form a first contact hole connecting the thin film transistor and the pixel electrode;

Etching the passivation layer and the gate insulating layer exposed by the photoresist pattern to form a second contact hole connecting the common line and the common electrode; And

Removing the photoresist pattern remaining on the passivation layer through a strip process;

Method of manufacturing a thin film transistor substrate comprising a.

The method of claim 9,

In the forming of the third conductive pattern, the common electrode and the pixel electrode is a thin film transistor substrate manufacturing method, characterized in that formed in parallel to each other in a three-dimensional structure having a height of 1000A ° to 5000A ° on the protective film.

The method of claim 10, wherein the forming of the pixel electrode comprises:

Forming a finger part connected to the horizontal part and forming a horizontal electric field with the common electrode;

13. The method of claim 12,

The thin film transistor substrate may be fabricated by forming a first horizontal electric field having a parabolic shape extending from the upper surface to the upper surface of the common electrode and the pixel electrode and a second horizontal electric field having a straight line extending from the side to the side. Way.