KR100913056B1 - 반도체 소자의 제조방법 - Google Patents
반도체 소자의 제조방법 Download PDFInfo
- Publication number
- KR100913056B1 KR100913056B1 KR1020020084277A KR20020084277A KR100913056B1 KR 100913056 B1 KR100913056 B1 KR 100913056B1 KR 1020020084277 A KR1020020084277 A KR 1020020084277A KR 20020084277 A KR20020084277 A KR 20020084277A KR 100913056 B1 KR100913056 B1 KR 100913056B1
- Authority
- KR
- South Korea
- Prior art keywords
- region
- ion implantation
- semiconductor substrate
- gate electrode
- implantation process
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (5)
- (a) NMOS 영역과 PMOS 영역으로 정의되는 반도체 기판에 소자 분리막을 형성하는 단계;(b) 상기 반도체 기판 상에 NMOS 게이트 전극과 PMOS 게이트 전극을 형성하는 단계;(c) LDD 이온 주입 공정을 실시하여 상기 NMOS 게이트 전극 및 상기 PMOS 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 저농도 접합영역을 형성하는 단계;(d) 'n+' 이온 주입 공정을 실시하여 상기 NMOS 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 상기 저농도 접합영역보다 깊은 제1 고농도 접합영역을 형성하는 단계;(e) 퍼니스 어닐링 방식을 이용한 열처리공정을 실시하여 상기 (d) 단계에서 실시되는 상기 'n+' 이온 주입 공정에 의해 상기 반도체 기판 내에서 발생하는 격자결함을 제거하는 단계; 및(f) 'p+' 이온 주입 공정을 실시하여 상기 PMOS 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 상기 저농도 접합영역보다 깊은 제2 고농도 접합영역을 형성하는 단계를 포함하고,상기 (e) 단계에서 실시되는 상기 퍼니스 어닐링 방식의 열처리공정에 의해 상기 반도체 기판 상에 20 내지 150Å의 두께로 산화막이 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제 1 항에 있어서,상기 (e) 단계에서 실시되는 상기 퍼니스 어닐링 방식의 열처리공정은 700℃에서 10분 동안 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제 1 항에 있어서,상기 (e) 단계에서 실시되는 상기 퍼니스 어닐링 방식의 열처리공정은 650 내지 850℃에서 10 내지 20분 동안 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제 2 항 또는 제 3 항에 있어서,상기 열처리공정은 100% O2 분위기에 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 삭제
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020084277A KR100913056B1 (ko) | 2002-12-26 | 2002-12-26 | 반도체 소자의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020084277A KR100913056B1 (ko) | 2002-12-26 | 2002-12-26 | 반도체 소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040057519A KR20040057519A (ko) | 2004-07-02 |
KR100913056B1 true KR100913056B1 (ko) | 2009-08-20 |
Family
ID=37350089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020020084277A KR100913056B1 (ko) | 2002-12-26 | 2002-12-26 | 반도체 소자의 제조방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100913056B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7541234B2 (en) | 2005-11-03 | 2009-06-02 | Samsung Electronics Co., Ltd. | Methods of fabricating integrated circuit transistors by simultaneously removing a photoresist layer and a carbon-containing layer on different active areas |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09252055A (ja) * | 1996-03-18 | 1997-09-22 | Oki Electric Ind Co Ltd | Cmosfetの製造方法 |
KR19980084534A (ko) * | 1997-05-23 | 1998-12-05 | 문정환 | 반도체 소자의 제조방법 |
KR100334965B1 (ko) * | 1999-08-12 | 2002-05-04 | 박종섭 | 모스전계효과트랜지스터 소자의 제조방법 |
-
2002
- 2002-12-26 KR KR1020020084277A patent/KR100913056B1/ko active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09252055A (ja) * | 1996-03-18 | 1997-09-22 | Oki Electric Ind Co Ltd | Cmosfetの製造方法 |
KR19980084534A (ko) * | 1997-05-23 | 1998-12-05 | 문정환 | 반도체 소자의 제조방법 |
KR100334965B1 (ko) * | 1999-08-12 | 2002-05-04 | 박종섭 | 모스전계효과트랜지스터 소자의 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20040057519A (ko) | 2004-07-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100393216B1 (ko) | 엘디디 구조를 갖는 모오스 트랜지스터의 제조방법 | |
KR0129125B1 (ko) | 반도체 소자의 ldd mosfet 제조방법 | |
US20070184620A1 (en) | Field effect transistor and method of manufacturing a field effect transistor | |
KR100913056B1 (ko) | 반도체 소자의 제조방법 | |
US9412869B2 (en) | MOSFET with source side only stress | |
KR100840684B1 (ko) | 반도체 소자의 제조방법 | |
KR100328455B1 (ko) | 반도체소자의제조방법 | |
KR100607818B1 (ko) | 반도체 소자의 트랜지스터 제조 방법 | |
KR100418721B1 (ko) | 반도체 소자의 트랜지스터 제조 방법 | |
KR101017042B1 (ko) | 반도체 소자의 제조 방법 | |
KR100325596B1 (ko) | 비소이온주입후실리콘웨이퍼의결정결함형성억제방법 | |
KR100880336B1 (ko) | 반도체 소자의 제조방법 | |
KR100577607B1 (ko) | 반도체 장치용 웰 형성 방법 및 이를 포함하는 반도체장치의 제조 방법 | |
JP2008235567A (ja) | 半導体装置の製造方法および半導体装置 | |
KR100215697B1 (ko) | 반도체 소자의 아이솔레이션 방법 | |
KR100313090B1 (ko) | 반도체장치의 소오스/드레인 형성방법 | |
CN116314233A (zh) | Cmos图像传感器及其制造方法 | |
KR100487641B1 (ko) | 반도체소자의 제조방법 | |
KR100773243B1 (ko) | 반도체 소자의 제조방법 | |
CN105720010A (zh) | 半导体结构的形成方法 | |
KR20050059749A (ko) | 반도체 소자의 제조방법 | |
KR20000027495A (ko) | 반도체 소자의 제조방법 | |
JPH1050819A (ja) | 半導体装置の製造方法 | |
KR20050118467A (ko) | 게이트 절연막 형성방법 및 이를 이용한 반도체 소자의제조방법 | |
KR20040056450A (ko) | 반도체 소자의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20120720 Year of fee payment: 4 |
|
FPAY | Annual fee payment |
Payment date: 20130730 Year of fee payment: 5 |
|
FPAY | Annual fee payment |
Payment date: 20150716 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20160718 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20170719 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20180717 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20190716 Year of fee payment: 11 |