KR20000004408A - Method for fabricating semiconductor memory device - Google Patents
Method for fabricating semiconductor memory device Download PDFInfo
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- KR20000004408A KR20000004408A KR1019980025840A KR19980025840A KR20000004408A KR 20000004408 A KR20000004408 A KR 20000004408A KR 1019980025840 A KR1019980025840 A KR 1019980025840A KR 19980025840 A KR19980025840 A KR 19980025840A KR 20000004408 A KR20000004408 A KR 20000004408A
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- storage electrode
- insulating film
- cell region
- forming
- dummy pattern
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000003860 storage Methods 0.000 claims abstract description 37
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 20
- 230000002093 peripheral effect Effects 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 메모리 소자의 제조방법에 관한 것으로, 특히 셀영역과 주변영역의 배선형성시 공정 여유도를 확보할 수 있는 반도체 메모리 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device capable of securing a process margin when forming wirings of cell and peripheral regions.
디램(DRAM; Dynamic Random Access Memory)과 같은 반도체 메모리 소자는 캐패시터를 이용하여 정보를 저장한다.Semiconductor memory devices, such as dynamic random access memory (DRAM), use capacitors to store information.
도 1은 종래의 디램 소자를 나타낸 단면도이다.1 is a cross-sectional view showing a conventional DRAM device.
도 1을 참조하면, 셀영역(A)과 주변영역(B)이 정의된 반도체 기판(10) 상에 층간절연막(20)을 형성하고, 전면식각하여 층간절연막(20)을 평탄화한다. 여기서, 도시되지는 않았지만, 기판(10)의 셀영역(A)에는 트랜지스터 및 비트라인이 형성되고, 기판(10)의 주변영역(B)에는 트랜지스터가 형성된다. 층간절연막(20)을 식각하여 셀영역(A)에 캐패시터용 콘택홀을 형성하고, 상기 콘택홀에 매립되도록 층간절연막(20) 상에 제 1 폴리실리콘막과 코어산화막(미도시)을 순차적으로 증착하고 패터닝하여, 스토리지 전극의 하부층(21)을 형성한다. 그런 다음, 기판 전면에 제 2 폴리실리콘막을 증착하고 패터닝하여 하부층(21) 및 코어 산화막의 양 측에 스페이서(22)를 형성한 다음, 상기 코어산화막을 제거하여 스토리지 전극(100)을 형성한다. 스토리지 전극(100) 표면에 유전체막(23)을 형성하고, 기판 전면에 제 3 폴리실리콘막을 증착하고 패터닝하여 플레이트 전극(24)을 형성함으로써 캐패시터를 형성한다. 그리고 나서, 기판 전면에 절연막(25)을 형성하고, 절연막(25)을 식각하여 셀 영역(A)의 플레이트 전극(24) 및 주변영역(B)의 트랜지스터의 일부를 노출시키는 배선용 제 1 및 제 2 콘택홀(26a, 26b)을 형성한다.Referring to FIG. 1, an interlayer insulating film 20 is formed on a semiconductor substrate 10 in which a cell region A and a peripheral region B are defined, and the entire surface is etched to planarize the interlayer insulating film 20. Although not shown, transistors and bit lines are formed in the cell region A of the substrate 10, and transistors are formed in the peripheral region B of the substrate 10. The interlayer insulating film 20 is etched to form a capacitor contact hole in the cell region A, and a first polysilicon film and a core oxide film (not shown) are sequentially formed on the interlayer insulating film 20 so as to be filled in the contact hole. Deposition and patterning form the lower layer 21 of the storage electrode. Then, a second polysilicon film is deposited on the entire surface of the substrate and patterned to form spacers 22 on both sides of the lower layer 21 and the core oxide film, and then the core oxide film is removed to form the storage electrode 100. A capacitor is formed by forming a dielectric film 23 on the surface of the storage electrode 100, forming a plate electrode 24 by depositing and patterning a third polysilicon film on the entire surface of the substrate. Then, the insulating film 25 is formed on the entire surface of the substrate, and the insulating film 25 is etched to expose the plate electrodes 24 of the cell region A and a part of the transistors of the peripheral region B. 2 contact holes 26a and 26b are formed.
그러나, 상기한 바와 같은 종래의 디램 소자에서는, 셀영역(A)의 플레이트 전극(24)과 주변영역(B)의 트랜지스터의 단차에 의해, 도 1에 도시된 바와 같이, 배선용 제 1 및 제 2 콘택홀(26a, 26b)의 깊이(C1, C2)가 서로 다르기 때문에, 배선용 제 1 및 제 2 콘택홀(26a, 26b) 형성을 위한 식각 공정시 공정여유도를 확보하기가 어렵다. 이에 따라, 셀영역(A)의 플레이트 전극(24) 표면이 손상되고, 단차가 심한 경우에는 배선용 제 1 및 제 2 콘택홀(26a, 26b)의 깊이차이가 더욱더 심해져, 플레이트 전극(24)을 관통하여 스토리지 전극(100)의 표면까지 손상되는 경우가 발생되어, 결국 소자의 특성이 저하된다.However, in the conventional DRAM device as described above, as shown in FIG. 1, the first and second wirings are shown by the step difference between the plate electrode 24 of the cell region A and the transistor of the peripheral region B. FIG. Since the depths C1 and C2 of the contact holes 26a and 26b are different from each other, it is difficult to secure a process margin during the etching process for forming the first and second contact holes 26a and 26b for wiring. As a result, the surface of the plate electrode 24 in the cell region A is damaged, and when the step is severe, the depth difference between the first and second contact holes 26a and 26b for wiring becomes even more severe, and thus the plate electrode 24 is removed. In some cases, the surface of the storage electrode 100 penetrates and is damaged, resulting in deterioration of device characteristics.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 셀영역과 주변영역 사이의 배선용 콘택홀의 깊이 차이를 최소화하여, 콘택홀 형성을 위한 식각시 공정여유도를 확보할 수 있는 반도체 메모리 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-described problems, the semiconductor memory device that can ensure the process margin during etching for forming the contact hole by minimizing the depth difference of the wiring contact hole between the cell region and the peripheral region The purpose is to provide a method of manufacturing.
도 1은 종래의 디램의 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a conventional method for manufacturing a DRAM.
도 2는 본 발명의 실시예에 따른 디램의 제조방법을 설명하기 위한 단면도.2 is a cross-sectional view illustrating a method of manufacturing a DRAM according to an embodiment of the present invention.
〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]
30 : 반도체 기판 40 : 층간절연막30 semiconductor substrate 40 interlayer insulating film
41 : 하브층 42 : 스페이서41: hub layer 42: spacer
200 : 스토리지 전극 43 : 유전체막200: storage electrode 43: dielectric film
44 : 플레이트 전극 45 : 절연막44 plate electrode 45 insulating film
46a, 46b : 배선용 콘택홀 C3, C4 : 깊이46a, 46b: Wiring contact hole C3, C4: Depth
A : 셀영역 B ; 주변영역A: cell region B; Surrounding area
상기 목적을 달성하기 위한 본 발명에 따른 반도체 메모리 소자의 제조방법은 셀영역과 주변영역이 정의된 반도체 기판 상에 그의 표면이 평탄한 층간절연막을 형성하는 단계; 층간절연막을 식각하여 셀영역에 캐패시터용 콘택홀을 형성하는 단계; 콘택홀 및 층간절연막 상에 스토리지 전극을 형성함과 동시에 주변영역에 인접한 셀영역의 층간절연막 상에 스토리지 전극 더미패턴을 형성하는 단계; 스토리지 전극 표면 및 스토리지 전극 더미패턴 상에 유전체막을 형성하는 단계; 셀영역에 플레이트 전극을 형성하는 단계; 기판 전면에 절연막을 형성하는 단계; 및, 절연막을 식각하여 스토리지 전극 더미패턴 상의 플레이트 전극 및 주변영역의 일부를 노출시키는 배선용 제 1 및 제 2 콘택홀을 형성하는 단계를 포함한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, the method including: forming an interlayer insulating film having a flat surface on a semiconductor substrate having defined cell regions and peripheral regions; Etching the interlayer insulating film to form a capacitor contact hole in the cell region; Forming a storage electrode on the contact hole and the interlayer dielectric layer and simultaneously forming a storage electrode dummy pattern on the interlayer dielectric layer of the cell region adjacent to the peripheral region; Forming a dielectric film on the storage electrode surface and the storage electrode dummy pattern; Forming a plate electrode in the cell region; Forming an insulating film on the entire surface of the substrate; And etching the insulating film to form first and second contact holes for wiring exposing portions of the plate electrode and the peripheral area on the storage electrode dummy pattern.
또한, 스토리지 전극 더미 패턴은 스토리지 전극의 폭보다 더 넓은 폭을 갖는다.In addition, the storage electrode dummy pattern has a width wider than that of the storage electrode.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2는 본 발명의 실시예에 따른 디램의 제조방법을 설명하기 위한 단면도이다.2 is a cross-sectional view illustrating a method of manufacturing a DRAM according to an embodiment of the present invention.
도 2를 참조하면, 셀 영역(A)과 주변영역(B)이 정의된 반도체 기판(30) 상에 층간절연막(40)을 형성하고, 전면식각하여 층간절연막(40)을 평탄화한다. 이때, 전면식각은 화학기계연마(Chemical Mechanical Polishing; CMP)로 진행한다. 또한, 도시되지는 않았지만, 기판(30)의 셀영역(A)에는 트랜지스터 및 비트라인이 구비되고, 기판(20)의 주변영역(B)에는 트랜지스터가 구비된다. 층간절연막(40) 상에 포토리소그라피로 제 1 마스크 패턴(미도시)을 형성하고, 상기 제 1 마스크 패턴을 식각 마스크로 하여 층간절연막(40)을 식각하여, 셀영역(A)에 캐패시터용 콘택홀을 형성한다.Referring to FIG. 2, an interlayer insulating film 40 is formed on a semiconductor substrate 30 in which a cell region A and a peripheral region B are defined, and the entire surface is etched to planarize the interlayer insulating film 40. At this time, the front surface etching is performed by chemical mechanical polishing (CMP). Although not shown, transistors and bit lines are provided in the cell region A of the substrate 30, and transistors are provided in the peripheral region B of the substrate 20. A first mask pattern (not shown) is formed on the interlayer insulating layer 40 by photolithography, and the interlayer insulating layer 40 is etched using the first mask pattern as an etch mask, thereby contacting the capacitor with the cell region A. Form a hole.
그런 다음, 공지된 방법으로 제 1 마스크 패턴을 제거하고, 상기 콘택홀에 매립되도록 층간절연막(40) 상에 제 1 폴리실리콘막과 코어산화막(미도시)을 순차적으로 증착한다. 코어산화막 상에 포토리소그라피로 제 2 마스크 패턴(미도시)을 형성한다. 상기 제 2 마스크 패턴을 식각 마스크로 하여 코어산화막 및 제 1 폴리실리콘막을 식각하여, 스토리지 전극의 하부층(21)을 형성함과 동시에 주변영역(B)에 인접한 셀영역(A)의 층간절연막(40) 상에 스토리지 전극의 하부층 더미패턴(41a)을 형성한다. 이때, 하부층 더미패턴(41a)은 하부층(21)의 폭보다 넓게 형성한다. 그런 다음, 공지된 방법으로 제 2 마스크 패턴을 제거하고, 기판 전면에 제 2 폴리실리콘막을 증착한다. 제 2 폴리실리콘막을 상기 코어산화막의 표면이 노출되도록 블랭킷 식각하여, 하부층(41)과 코어산화막의 측벽에 스페이서(42)를 형성함과 동시에 하부층 더미패턴(41a)과 코어산화막의 측벽에 스페이서 더미패턴(42a)을 형성한다. 그리고 나서, 상기 코어산화막을 제거하여, 스토리지 전극(200)을 형성함과 동시에 스토리지 전극 더미패턴(200a)을 형성한다. 이때, 스토리지 전극 더미패턴(200a)은 하부층 더미패턴(41a)의 넓은 폭에 의해, 스토리지 전극(200)보다 더 넓은 폭을 갖는다.Then, the first mask pattern is removed by a known method, and a first polysilicon film and a core oxide film (not shown) are sequentially deposited on the interlayer insulating film 40 so as to be filled in the contact hole. A second mask pattern (not shown) is formed by photolithography on the core oxide film. The core oxide layer and the first polysilicon layer are etched using the second mask pattern as an etch mask to form the lower layer 21 of the storage electrode and at the same time, the interlayer insulating layer 40 of the cell region A adjacent to the peripheral region B. The lower layer dummy pattern 41a of the storage electrode is formed on the substrate. At this time, the lower layer dummy pattern 41a is formed wider than the width of the lower layer 21. Then, the second mask pattern is removed by a known method, and a second polysilicon film is deposited on the entire surface of the substrate. The second polysilicon film is blanket-etched to expose the surface of the core oxide film, thereby forming spacers 42 on the sidewalls of the lower layer 41 and the core oxide film, and simultaneously stacking the spacers on the lower layer dummy pattern 41a and the sidewalls of the core oxide film. The pattern 42a is formed. Then, the core oxide film is removed to form the storage electrode 200 and to form the storage electrode dummy pattern 200a. In this case, the storage electrode dummy pattern 200a has a wider width than the storage electrode 200 due to the wide width of the lower layer dummy pattern 41a.
그 후, 스토리지 전극(200) 및 스토리지 전극 더미패턴(200a)의 표면에 유전체막(43)을 형성하고, 기판 전면에 제 3 폴리실리콘막을 증착하고 패터닝하여 플레이트 전극(44)을 형성하여 캐패시터를 형성한다. 그리고 나서, 기판 전면에 절연막(45)을 형성하고, 절연막(45)을 식각하여 셀영역(A)의 플레이트 전극(44) 및 주변영역(B)의 트랜지스터의 일부를 노출시키는 배선용 제 1 및 제 2 콘택홀(46a, 46b)을 형성한다. 이때, 플레이트 전극(44) 하부의 스토리지 전극 더미패턴(200a)에 의해, 셀영역(A)의 배선용 제 1 콘택홀(46a)의 깊이(C3)와 주변영역(B)의 배선용 제 2 콘택홀(46b)의 깊이(C4)의 차이가 종래의 콘택홀(26a, 26b; 도 1 참조)의 깊이(C1, C2; 도 1 참조)의 차이보다 작아진다. 이에 따라, 셀영역(A)과 주변영역(B)의 배선용 제 1 및 제 2 콘택홀(46a, 46b)의 식각시, 플레이트 전극(44)의 손상이 방지된다.Thereafter, a dielectric film 43 is formed on the surfaces of the storage electrode 200 and the storage electrode dummy pattern 200a, and a third polysilicon film is deposited and patterned on the entire surface of the substrate to form a plate electrode 44 to form a capacitor. Form. Then, the insulating film 45 is formed on the entire surface of the substrate, and the insulating film 45 is etched to expose the plate electrodes 44 of the cell region A and a part of the transistors of the peripheral region B. 2 contact holes 46a and 46b are formed. At this time, the depth C3 of the first contact hole 46a for wiring in the cell region A and the second contact hole for wiring in the peripheral region B are formed by the storage electrode dummy pattern 200a under the plate electrode 44. The difference in depth C4 of 46b is smaller than the difference in depth C1, C2 (see FIG. 1) of the conventional contact holes 26a and 26b (see FIG. 1). Accordingly, damage to the plate electrode 44 is prevented when the first and second contact holes 46a and 46b for wiring in the cell region A and the peripheral region B are etched.
상기한 본 발명에 의하면, 별도의 추가공정을 진행하는 것 없이, 주변영역에 인접한 셀영역에 스토리지 전극의 형성시 스토리지 전극 더미패턴을 형성하여, 셀영역과 주변영역의 배선용 콘택홀의 깊이를 최소화함으로써, 콘택홀 형성을 위한 식각시 공정 여유도를 확보할 수 있다. 이에 따라, 식각에 의한 플레이트 전극의 손상이 방지되어, 결국 소자의 신뢰성이 향상된다.According to the present invention described above, by forming a storage electrode dummy pattern when forming the storage electrode in the cell region adjacent to the peripheral region without performing any additional process, by minimizing the depth of the contact hole for wiring between the cell region and the peripheral region In addition, it is possible to secure a process margin when etching to form contact holes. As a result, damage to the plate electrode due to etching is prevented, resulting in improved reliability of the device.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980025840A KR20000004408A (en) | 1998-06-30 | 1998-06-30 | Method for fabricating semiconductor memory device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980025840A KR20000004408A (en) | 1998-06-30 | 1998-06-30 | Method for fabricating semiconductor memory device |
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| KR20000004408A true KR20000004408A (en) | 2000-01-25 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100474579B1 (en) * | 2002-08-09 | 2005-03-10 | 삼성전자주식회사 | Method for manufacturing a standard wafer used in surface analysis system |
| KR100884346B1 (en) * | 2007-10-26 | 2009-02-18 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semicondutor device |
-
1998
- 1998-06-30 KR KR1019980025840A patent/KR20000004408A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100474579B1 (en) * | 2002-08-09 | 2005-03-10 | 삼성전자주식회사 | Method for manufacturing a standard wafer used in surface analysis system |
| US6995074B2 (en) | 2002-08-09 | 2006-02-07 | Samsung Electronics Co., Ltd. | Method for manufacturing a semiconductor wafer |
| KR100884346B1 (en) * | 2007-10-26 | 2009-02-18 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semicondutor device |
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