KR100873801B1 - Metal wiring formation method of semiconductor device using carbon nanotube - Google Patents

Metal wiring formation method of semiconductor device using carbon nanotube Download PDF

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KR100873801B1
KR100873801B1 KR1020020042300A KR20020042300A KR100873801B1 KR 100873801 B1 KR100873801 B1 KR 100873801B1 KR 1020020042300 A KR1020020042300 A KR 1020020042300A KR 20020042300 A KR20020042300 A KR 20020042300A KR 100873801 B1 KR100873801 B1 KR 100873801B1
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forming
metal wiring
film
semiconductor device
dual damascene
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KR1020020042300A
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KR20040008632A (en
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문봉웅
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers

Abstract

본 발명은 탄소나노튜브(carbon nanotubes:CNT)를 이용한 반도체 소자의 금속배선 형성 방법에 관한 것으로, 금속배선과 접촉될 도전층상에 상기 도전층의 일부 표면을 노출시키는 듀얼 다마신 패턴을 형성하는 단계, 상기 듀얼 다마신 패턴을 포함한 상기 노출된 도전층상에 촉매금속막을 형성하는 단계, 상기 촉매금속막을 선택적으로 제거하여 상기 도전층 상부와 상기 듀얼 다마신패턴의 상부에만 잔류시키는 단계, 및 상기 촉매금속막상에 탄소나노튜브층을 성장시켜 상기 듀얼 다마신 패턴을 채우는 단계를 포함한다.
The present invention relates to a method for forming a metal wiring of a semiconductor device using carbon nanotubes (CNTs), the method comprising: forming a dual damascene pattern exposing a part of the surface of the conductive layer on a conductive layer to be in contact with the metal wiring; Forming a catalyst metal film on the exposed conductive layer including the dual damascene pattern, selectively removing the catalyst metal film and leaving only the upper portion of the conductive layer and the upper portion of the dual damascene pattern, and the catalyst metal Growing a carbon nanotube layer on the film to fill the dual damascene pattern.

Description

탄소나노튜브를 이용한 반도체 소자의 금속배선 형성방법{Method for forming metal wire using CNT} Method for forming metal wire using CNTs in semiconductor devices {Method for forming metal wire using CNT}             

도 1a 내지 도 1b는 종래 기술에 따른 금속배선의 형성 방법을 도시한 공정 단면도,1a to 1b is a cross-sectional view showing a method of forming a metal wiring according to the prior art,

도 2a 내지 도 2d는 본 발명의 실시예에 따른 금속배선의 형성 방법을 도시한 공정 단면도.
2A to 2D are cross-sectional views illustrating a method of forming a metal wiring according to an embodiment of the present invention.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

21: 하부 금속배선 22 : 제1 층간절연막21: lower metal wiring 22: the first interlayer insulating film

23 : 제1 질화막 24 : 제2 층간절연막23: first nitride film 24: second interlayer insulating film

25 : 제2 질화막 26 : 반사방지막25: second nitride film 26: antireflection film

30: 촉매금속막 31 : 탄소나노튜브층
30: catalytic metal film 31: carbon nanotube layer

본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 탄소나노튜브(carbon nanotubes:CNT)를 이용한 반도체 소자의 금속배선 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device using carbon nanotubes (CNT).

일반적으로, 반도체 소자의 금속배선은 넓은 접촉면적과 낮은 면저항을 가지고 있어야 고속동작을 보장받을 수 있다. 특히, 반도체 소자의 직접도가 증가함에 따라 타포러지(topology)가 증가하게 되어 다층 금속배선에 있어서의 단락과 같은 문제를 해결하기 위하여 다양한 방법을 사용하고 있다.In general, the metal wiring of the semiconductor device should have a large contact area and low sheet resistance to ensure high speed operation. In particular, as the directivity of semiconductor devices increases, topologies increase, and various methods are used to solve problems such as short circuits in multilayer metal interconnections.

도 1a 내지 도 1b는 종래의 다마신 공정을 이용한 금속배선 형성 공정 단면도이다.1A to 1B are cross-sectional views of a metal wiring forming process using a conventional damascene process.

도 1a에 도시된 바와 같이, 하부 금속배선(11) 형성이 완료된 기판(10) 상에 절연막(12)을 형성하고, 절연막(12)을 선택적으로 식각하여 하부 금속배선(11)을 노출시키는 비아홀(C1)과 금속배선을 이루는 라인패턴(line pattern)을 정의하는 트렌치(C2)로 이루어진 듀얼 다마신 패턴을 형성한다.As shown in FIG. 1A, a via hole is formed on the substrate 10 on which the lower metal wiring 11 is formed, and then selectively etches the insulating film 12 to expose the lower metal wiring 11. A dual damascene pattern formed of trench C2 defining a line pattern forming a metal wiring with C1 is formed.

도 1b에 도시된 바와 같이, 비아홀(C1)과 트렌치(C2) 내에 금속막을 매립하여 비아(13a)와 상부 금속배선(13b)을 동시에 형성한다. 비아홀(C1)을 채우는 금속막은 하부 금속배선(11)과 상부 금속배선(13b)을 연결하는 비아(13a)를 이룬다.As shown in FIG. 1B, a metal film is embedded in the via hole C1 and the trench C2 to simultaneously form the via 13a and the upper metal wiring 13b. The metal film filling the via hole C1 forms a via 13a connecting the lower metal wiring 11 and the upper metal wiring 13b.

상기 종래의 듀얼 다마신 공정에 의한 금속배선은 도전층간의 접촉 불량을 최소화할 수 있지만, 서브마이크론(submicron) 영역의 고직접 소자에서는 전류밀도의 확보가 어렵고, RC지연 증가 및 후속 열처리 공정에 많은 제한을 주는 문제점이 있었다.The metallization by the conventional dual damascene process can minimize contact defects between the conductive layers, but it is difficult to secure current density in high-direct devices in the submicron region, and it is difficult to increase the RC delay and the subsequent heat treatment process. There was a problem that gave limitations.

상기 종래의 반도체 금속막 물질로 쓰이는 금속계열(Al, Al-Cu...)은, 소자 가 서브마이크론(submicron)영역으로 작아짐에 따라 디자인룰(design rule)의 감소로 인하여 소자의 성능을 낼 수 있는 전류밀도의 한계를 보여주고 있다. 한편, 피치(pitch) 32nm급에서 기존의 금속배선을 사용할 경우 입자표면의 산란효과로 인하여 저항증가와 정전용량 증가로 인하여 칩 상의 주파수 성능을 제한하며 칩(chip)상에서 발생될 수 있는 열을 충분히 제거하지 못하는 문제점을 가지고 있다.
The metal series (Al, Al-Cu ...) used as the conventional semiconductor metal film material exhibits device performance due to a reduction in design rules as the device becomes smaller into a submicron region. It shows the limit of possible current density. On the other hand, when the existing metal wiring is used at the pitch of 32 nm, the frequency performance on the chip is limited due to the increase of resistance and capacitance due to the scattering effect of the particle surface, and sufficient heat that can be generated on the chip is sufficient. There is a problem that can not be removed.

상기 문제점을 해결하기 위하여 안출된 본 발명은 탄소나노튜브층을 이용하여 금속배선을 형성함으로써 서브마이크론영역에서 높은 전류밀도를 확보하고 RC지연 감소를 얻을 수 있는 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems by providing a metal wiring using a carbon nanotube layer to provide a method for forming a metal wiring of a semiconductor device that can secure a high current density in the sub-micron region and obtain a reduction in RC delay. The purpose is.

또한, 본 발명은 뛰어난 열전도도 및 내열성을 가지는 금속배선을 제공함으로써 후속 공정을 용이하게 할 수 있는 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.
In addition, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device that can facilitate the subsequent process by providing a metal wiring having excellent thermal conductivity and heat resistance.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 금속배선과 접촉될 도전층상에 상기 도전층의 일부 표면을 노출시키는 듀얼 다마신 패턴을 형성하는 단계와, 상기 듀얼 다마신 패턴을 포함한 상기 노출된 도전층상에 촉매금속막을 형성하는 단계와, 상기 촉매금속막을 선택적으로 제거하여 상기 도전층 상부와 상기 듀얼 다마신패턴을 형성하는 절연막의 상부에만 잔류시키는 단계와, 상기 촉매금속막상에 탄소나노튜브층을 성장시켜 상기 듀얼 다마신 패턴을 채우는 단계포함함을 특징으로 하는 반도체 소자의 금속배선 형성 방법을 제공한다.According to an aspect of the present invention for achieving the above technical problem, forming a dual damascene pattern to expose a portion of the surface of the conductive layer on the conductive layer to be in contact with the metal wiring, including the dual damascene pattern Forming a catalyst metal film on the exposed conductive layer, selectively removing the catalyst metal film and remaining only on the conductive layer and on an insulating film forming the dual damascene pattern, and carbon on the catalyst metal film It provides a method for forming a metal wiring of the semiconductor device comprising the step of growing the nanotube layer to fill the dual damascene pattern.

이하, 첨부된 도면을 참조하여 본 발명에 따른 금속배선 형성방법을 상세히 설명하며 다음과 같다.Hereinafter, with reference to the accompanying drawings will be described in detail a metal wiring forming method according to the present invention.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 금속배선의 형성 방법을 도시한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a metal wiring according to an embodiment of the present invention.

먼저, 도 2a에 도시된 바와 같이, 하부 금속배선(21)이 형성된 반도체기판(20)상에 제1 층간절연막(22), 제1 질화막(23), 제2 층간절연막(24), 제2 질화막(25) 및 반사방지막(26)을 차례로 증착한다.First, as shown in FIG. 2A, the first interlayer insulating film 22, the first nitride film 23, the second interlayer insulating film 24, and the second interlayer insulating film 22 are formed on the semiconductor substrate 20 on which the lower metal wiring 21 is formed. The nitride film 25 and the antireflection film 26 are sequentially deposited.

다음에, 반사방지막(26) 상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 비아홀(via hole)을 정의하는 제1 감광막패턴(27)을 형성한다.Next, a photoresist film is coated on the antireflection film 26 and patterned by exposure and development to form a first photoresist pattern 27 defining a via hole.

다음에, 제1 감광막패턴(27)을 식각 마스크로 사용하여 반사방지막(26), 제2 질화막(25), 제2 층간절연막(24), 제2 질화막(23) 및 제1 층간절연막(22)을 순차적으로 식각하여 하부 금속배선(21)의 일부영역을 노출시킨다. Next, the anti-reflection film 26, the second nitride film 25, the second interlayer insulating film 24, the second nitride film 23, and the first interlayer insulating film 22 are formed by using the first photosensitive film pattern 27 as an etching mask. ) Is sequentially etched to expose a portion of the lower metal wiring 21.

이때, 제1, 제 2 질화막(23, 25)은 식각 공정에서 식각정지층의 역할을 담당하기 위한 층으로 사용된다. In this case, the first and second nitride films 23 and 25 are used as layers for playing the role of the etch stop layer in the etching process.

그리고, 도 2b에 도시된 바와 같이, 제1 감광막패턴(27)을 제거한 후, 듀얼 다마신 공정을 수행하기 위하여 식각처리된 반사방지막(26) 상에 다시 감광막을 도 포하고 노광 및 현상으로 패터닝하여 라인패턴(또는 트렌치라고도 일컬음)을 정의하는 제2 감광막패턴(28)을 형성한다. 이때, 제2 감광막패턴(28)은 제1 감광막패턴(27)보다 더 넓은 폭을 가지도록 한다.2B, after removing the first photoresist layer pattern 27, the photoresist layer is again coated on the etched antireflection layer 26 to perform a dual damascene process and patterned by exposure and development. As a result, a second photosensitive film pattern 28 defining a line pattern (or also called a trench) is formed. In this case, the second photoresist pattern 28 may have a wider width than the first photoresist pattern 27.

다음으로, 제2 감광막패턴(28)을 식각 마스크로 사용하여 반사방지막(26), 제2 질화막(25), 제2 층간절연막(24), 제1 질화막(23), 제1 층간절연막(22)을 차례로 식각하여 상부가 넒은 입구를 가지는 트렌치(29a)를 형성한다. 이때, 비아홀(29b)도 동시에 오픈된다.Next, the anti-reflection film 26, the second nitride film 25, the second interlayer insulating film 24, the first nitride film 23, and the first interlayer insulating film 22 are formed by using the second photosensitive film pattern 28 as an etching mask. ) Is sequentially etched to form a trench 29a having a narrow inlet. At this time, the via hole 29b is also opened at the same time.

다음에, 도 2c에 도시된 바와 같이, 제2 감광막패턴(28)을 제거한 후, 전체구조 상부에 촉매금속막(30)을 50nm∼100nm 두께로 증착한 후 노출된 하부 금속배선(21) 및 반사방지막(26) 상에만 촉매금속막(30)이 위치하도록 패터닝 공정을 수행한다. Next, as shown in FIG. 2C, after removing the second photoresist layer pattern 28, the catalyst metal layer 30 is deposited to a thickness of 50 nm to 100 nm over the entire structure, and then the exposed lower metal wiring 21 and The patterning process is performed such that the catalytic metal film 30 is positioned only on the antireflection film 26.

여기서, 촉매금속막(30)은 이후에 증착될 탄소나노튜브층의 성장을 돕기 위한 것으로 Fe, Co 또는 Ni 중에서 선택된 전이금속막을 사용할 수 있다. 한편, 촉매금속막(30)의 패터닝은 HF 용액을 이용한 습식식각 공정이 이용되며 NH3 가스분위기에서 열처리과정을 거치게 된다. Here, the catalyst metal film 30 may be used to assist the growth of the carbon nanotube layer to be deposited later, using a transition metal film selected from Fe, Co or Ni. On the other hand, the patterning of the catalytic metal film 30 is a wet etching process using the HF solution is subjected to a heat treatment process in the NH 3 gas atmosphere.

끝으로, 도 2d에 도시된 바와 같이, 촉매금속막(30)상에 탄소나노튜브층(31)을 CVD(chemical vapor deposition)공정을 이용하여 성장시킨다. 이때, 트렌치(29a)와 비아홀(29b)을 채울때까지 촉매금속막(30) 상에만 선택적으로 탄소나노튜브층(31)이 형성된다. 여기서, 탄소나노튜브층(31)은 상부 금속배선(31)과 비아(31a)를 이룬다.Finally, as shown in FIG. 2D, the carbon nanotube layer 31 is grown on the catalytic metal film 30 using a chemical vapor deposition (CVD) process. At this time, the carbon nanotube layer 31 is selectively formed only on the catalyst metal film 30 until the trench 29a and the via hole 29b are filled. Here, the carbon nanotube layer 31 forms the upper metal wiring 31 and the via 31a.

본 발명에서 배선물질로 사용하는 탄소나노튜브층(31)은 물질의 특성상 길이와 무관한 낮은 저항을 가지고 있음에도 불구하고 구조적 결함을 거의 갖지 않기 때문에 Cu 및 Ti와 같은 확산방지막을 필요로 하지 않는다. 즉, 탄소나노튜브층(31)을 금속배선으로 사용하기 때문에 층간절연막으로 전자의 이동이나 확산이 없어 확산방지막을 사용할 필요가 없다.The carbon nanotube layer 31 used as the wiring material in the present invention does not require a diffusion barrier such as Cu and Ti because it has almost no structural defects despite the low resistance irrespective of the length of the material. That is, since the carbon nanotube layer 31 is used as the metal wiring, there is no need to use a diffusion barrier because there is no movement or diffusion of electrons as the interlayer insulating film.

따라서, 서브마이크론 영역에서도 높은 전류밀도를 낼 수 있으며, 저항의 감소로 인하여 RC지연 문제도 해결할 수 있게 된다. 또한, 탄소나노튜브층(31)은 높은 내열성을 가지므로 백엔드(back end) 공정에서도 열처리 공정을 사용할수 있는 장점을 가지고 있다. 또한, 불순물주입으로 전도성의 증가를 꾀할 수 있다.Therefore, high current density can be obtained even in the submicron region, and the RC delay problem can be solved due to the reduction of the resistance. In addition, since the carbon nanotube layer 31 has high heat resistance, the carbon nanotube layer 31 may also use a heat treatment process in a back end process. In addition, the conductivity can be increased by impurity injection.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 탄소나모튜층을 금속배선용 도전체로 사용 함으로써, 확산방지막을 필요로 하는 종래의 금속배선이 가지는 구조적 복잡성을 제거할 수 있다. 특히, 종래의 금속배선으로 사용되는 알루미늄층의 경우 녹는점이 약 600℃이기 때문에 열처리공정상의 어려움이 많이 따랐으나, 본 발명의 탄 소나노튜브는 내열성이 강하므로 후속 열처리의 공정에 효과적인 장점이 있다. The present invention made as described above can eliminate the structural complexity of the conventional metal wiring, which requires the diffusion barrier film, by using the carbon nano-tuft layer as the conductor for metal wiring. In particular, in the case of the aluminum layer used as a conventional metal wiring has a melting point of about 600 ℃ due to a lot of difficulties in the heat treatment process, but the carbon nanotubes of the present invention has a strong heat resistance, there is an effective advantage in the process of subsequent heat treatment.

Claims (5)

금속배선과 접촉될 도전층상에 상기 도전층의 일부 표면을 노출시키는 듀얼 다마신 패턴을 형성하는 단계;Forming a dual damascene pattern exposing a portion of the surface of the conductive layer on the conductive layer to be in contact with the metallization; 상기 듀얼 다마신 패턴을 포함한 상기 노출된 도전층상에 촉매금속막을 형성하는 단계;Forming a catalytic metal film on the exposed conductive layer including the dual damascene pattern; 상기 촉매금속막을 선택적으로 제거하여 상기 도전층 상부와 상기 듀얼 다마신패턴을 형성하는 절연막의 상부에만 잔류시키는 단계; 및Selectively removing the catalyst metal film and remaining only on an upper portion of the conductive layer and an insulating layer forming the dual damascene pattern; And 상기 촉매금속막상에 탄소나노튜브층을 성장시켜 상기 듀얼 다마신 패턴을 채우는 단계Growing a carbon nanotube layer on the catalytic metal film to fill the dual damascene pattern; 포함함을 특징으로 하는 반도체 소자의 금속배선 형성 방법.Metal wire forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 촉매금속막을 선택적으로 제거하는 단계는,Selectively removing the catalyst metal film, HF용액을 이용한 습식식각을 이용함을 특징으로 하는 반도체소자의 금속배선 형성 방법.A method for forming metal wiring in a semiconductor device, comprising using wet etching with HF solution. 제 1 항에 있어서,The method of claim 1, 상기 촉매금속막은 50∼100nm 두께로 형성되는 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The catalyst metal film is a metal wiring forming method of the semiconductor device, characterized in that formed in a thickness of 50 to 100nm. 제 1 항에 있어서,The method of claim 1, 상기 촉매금속막을 선택적으로 제거하여 상기 도전층 상부와 상기 듀얼 다마신패턴을 형성하는 절연막의 상부에만 잔류시키는 단계는,Selectively removing the catalyst metal film and remaining only on the conductive layer and on an insulating film forming the dual damascene pattern; NH3분위기에서 열처리하는 단계를 더 포함함을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The method of forming a metal wiring of the semiconductor device characterized in that it further comprises the step of heat treatment in an NH 3 atmosphere. 제1항에 있어서,The method of claim 1, 상기 촉매금속막은 Fe, Co 또는 Ni 중에서 선택되는 것을 특징으로 하는 반도체소자의 금속배선 형성 방법.The catalyst metal film is a metal wiring forming method of the semiconductor device, characterized in that selected from Fe, Co or Ni.
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