KR100855857B1 - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

Info

Publication number
KR100855857B1
KR100855857B1 KR1020070036465A KR20070036465A KR100855857B1 KR 100855857 B1 KR100855857 B1 KR 100855857B1 KR 1020070036465 A KR1020070036465 A KR 1020070036465A KR 20070036465 A KR20070036465 A KR 20070036465A KR 100855857 B1 KR100855857 B1 KR 100855857B1
Authority
KR
South Korea
Prior art keywords
recess
semiconductor substrate
forming
gate
etching
Prior art date
Application number
KR1020070036465A
Other languages
Korean (ko)
Inventor
이상돈
정성웅
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070036465A priority Critical patent/KR100855857B1/en
Application granted granted Critical
Publication of KR100855857B1 publication Critical patent/KR100855857B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A semiconductor device and a manufacturing method thereof are provided to enhance control performance of a transistor by improving current driving performance and a short channel effect. A pad insulating layer pattern is formed on a semiconductor substrate(210). A spacer is formed at a sidewall of the pad insulating layer pattern. A trench for defining an active region is formed by etching the semiconductor substrate. The spacer is removed. An isolation structure(220) is formed by burying the trench. The active region is exposed by removing the pad insulating layer pattern. A first recess is formed by etching the exposed active region. A second recess is formed by etching the exposed semiconductor substrate. A gate insulating layer(250) is formed on the active region including an SOI(Silicon-On-Insulator) recess channel structure(240) defined by the first and second recesses. A gate including a gate conductive layer is formed to bury the SOI recess channel structure.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is a layout of a semiconductor device in accordance with an embodiment of the present invention.

2 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a silicon-on-insulator (SOI) transistor and a method for manufacturing the same.

In general, as the channel length of the cell transistor decreases, the ion concentration of the cell channel increases to match the threshold voltage of the cell transistor. As a result, the electric field of the S / D region is increased to increase the leakage current, which in turn degrades the refresh characteristics of the DRAM. In addition, due to the reduction of design rules, problems related to short channel effects have gradually become difficult to overcome. Accordingly, in order to increase the channel length of the cell transistor, a multi-channel field effect transistor (hereinafter referred to as a "McFET") such as a recess transistor and a fin transistor has been proposed.

However, in the McFET technology, the process complexity is increased by the additional deposition process and the planarization etching process. In addition, the fin transistor technology has a disadvantage in that it is difficult to control the thickness and height of the fin channel as the design rule decreases. And because the lower part of the fin channel is connected to the semiconductor substrate, the punch-through phenomenon easily occurs between the source and drain regions when the height of the fin channel is smaller than the depth of the source / drain regions according to the design rule reduction. There is a disadvantage. Accordingly, there is a need for a device having a new structure that improves gate control ability and improves device performance.

The present invention is to solve the above problems, by designing the device to include a silicon-on-insulator (SOI) recess channel structure in the three-dimensional recess transistor to prevent the source / drain punch through phenomenon, The present invention provides a semiconductor device capable of forming a high-speed low voltage semiconductor device by improving the controllability of a transistor by improving current driving capability and short channel effect, and a method of manufacturing the same.

The present invention is to achieve the above object, the manufacturing method of a semiconductor device according to an embodiment of the present invention,

Forming a pad insulating film pattern on the semiconductor substrate, forming a spacer on the sidewalls of the pad insulating film pattern, and etching a semiconductor substrate using the spacer and the pad insulating film pattern as an etching mask to form a trench defining an active region Removing the spacers, forming a device isolation structure by filling the trench, exposing the active region by removing the pad insulating layer pattern, and etching the active region exposed by the recess gate mask. Forming a recess, further etching the semiconductor substrate exposed under the first recess to form a second recess, and a silicon-on-insulator defined as the first recess and the second recess ) Forming a gate insulating layer over the active region including the recess channel structure, and forming a gate conductive layer filling the SOI recess channel structure. Forming a gate comprising a.

In addition, a method of manufacturing a semiconductor device according to another embodiment of the present invention,

Forming a pad insulating layer pattern on the semiconductor substrate, forming a trench defining an active region by etching the semiconductor substrate exposed using the pad insulating layer pattern as an etching mask, and selectively etching a portion of the pad insulating layer pattern to form an active region Exposing a portion of the semiconductor substrate at an end of the semiconductor substrate, forming a device isolation structure filling the trench including the exposed semiconductor substrate, removing the pad insulating film pattern to expose the active region, and a recess gate mask. Etching the exposed active region to form a first recess including the fin type active region, and further etching the exposed semiconductor substrate under the first recess to form a second recess; Forming a gate insulating film over the active region including an SOI recess channel structure defined by a recess and a second recess; And forming a gate including a gate electrode filling the SOI recess channel structure.

In addition, the semiconductor device according to an embodiment of the present invention is a semiconductor device manufactured by the method of manufacturing the semiconductor device.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1 is a layout of a semiconductor device according to an embodiment of the present invention. The semiconductor device includes an active region 101, a recess gate region 103, and a gate region 105. The active region 101 is defined by the device isolation region 102. Hereinafter, the longitudinal direction of the gate region 105 is defined as "vertical direction", and the longitudinal direction of the active region 101 is defined as "horizontal direction". According to an embodiment of the present disclosure, the recess gate region 103 is an island-type, and the horizontal line width of the recess gate region 103 is preferably equal to or smaller than that of the gate region 105. Do. In addition, the vertical line width of the recess gate region 103 is preferably equal to or larger than that of the active region 101. And the vertical line width of the active region 101 is preferably equal to or larger than that of the conventional.

2 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, FIG. 2 (i) is a cross-sectional view taken along line II ′ of FIG. 1, and FIG. 2 (ii) is a cross-sectional view taken along line II-II ′ of FIG. It is a cross section. The semiconductor device according to the present invention includes a device isolation structure 220, a recess channel structure 240 including a silicon-on-insulator (SOI) channel structure 246, and a gate structure 290. The device isolation structure 220 defines the active region 101 of FIG. 1 and is in contact with one side of the SOI channel structure in the vertical direction.

The recess channel structure 240 is located in the semiconductor substrate 210 and is defined by the upper recess channel structure 242 and the lower recess channel structure 244. In addition, the recess channel structure 240 is separated from the lower semiconductor substrate 210 by a predetermined distance, and includes an SOI channel structure 246 in contact with both device isolation structures 220 in a vertical direction. According to an embodiment of the present invention, the horizontal line width of the upper recess channel structure 242 in the horizontal direction is preferably less than or equal to that of the lower recess channel structure 244. In addition, the horizontal thickness t SOI of the SOI channel structure 246 is preferably 50 kV to 1,000 kV. In addition, the separated distance between the SOI channel structure 246 and the semiconductor substrate 210 below is preferably 100 to 2,000 mW.

The gate structure 290 is positioned on the gate insulating layer 250 of the gate region 105 of FIG. 1, and includes a gate electrode 272 and a gate hard mask layer 280, and the gate electrode 272 is a lower gate. An electrode 260 and an upper gate electrode 270. The lower gate electrode 260 fills the recess channel structure 240 including the SOI channel structure 246. The upper gate electrode 270 and the gate hard mask layer 280 are formed on the lower gate electrode 260. According to an embodiment of the present invention, the lower gate electrode 260 is preferably formed of a polysilicon layer, and the upper gate electrode 270 is a cobalt (Co) layer, a nickel (Ni) layer, or a titanium (Ti) layer. , Titanium nitride (TiN) film, tungsten (W) layer, tungsten nitride (WN) film, aluminum (Al) layer, copper (Cu) layer, tungsten silicide (WSi x ) layer, cobalt silicide (CoSi x ) layer, titanium It is preferable to form one selected from the group consisting of a silicide (TiSi x ) layer, a nickel silicide (NiSi x ) layer, and a combination thereof.

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. 3A (i) to 3H (i) are cross-sectional views taken along line II ′ of FIG. 1, and FIGS. 3A (ii) to 3H (ii) are cross-sectional views taken along line II-II ′ of FIG. 1. A pad oxide layer 312, a pad nitride layer (not shown), and a first hard mask layer (not shown) are formed on the semiconductor substrate 310. Next, after forming a photoresist film (not shown) on the entire surface, it is exposed and developed with an element isolation mask (not shown) to form a photoresist pattern (not shown). Thereafter, the first hard mask layer and the pad nitride layer are etched using the photoresist pattern as a mask to form the first hard mask layer pattern 316 and the second pad insulating layer pattern 314, and then the photoresist pattern is removed. Next, after forming the first insulating film spacer 318 on the sidewalls of the first hard mask layer pattern 316 and the pad nitride film pattern 314, the first insulating film spacer 318 and the first hard mask layer pattern 316 are formed. Using the etching mask, the pad oxide layer 312 and the semiconductor substrate 310 are etched to form a trench 322 for device isolation.

According to one embodiment of the present invention, the first hard mask layer is preferably formed of any one selected from the group consisting of an oxide film, a polysilicon layer, and a combination thereof. In addition, the first insulating film spacer 318 is preferably formed of any one selected from the group consisting of an oxide film, a nitride film, and a combination thereof. Meanwhile, in the vertical direction, the horizontal thickness t 1 of the first insulating film spacer 318 may be determined according to the horizontal thickness t SOI of the subsequent SOI channel structure, and may be determined in subsequent etching and thermal oxidation processes than the horizontal thickness t SOI of the SOI channel structure. It is desirable to form thicker as the thickness of the semiconductor substrate lost by. The horizontal thickness t 1 of the first insulating film spacer 318 is preferably 100 kPa to 1,200 kPa.

According to another embodiment of the present invention, after forming a photoresist pattern (not shown) defining an isolation region on the semiconductor substrate 310 on which the pad oxide film, the pad nitride film and the first hard mask layer are formed, the photoresist pattern is masked. The first hard mask layer, the pad nitride film, and the pad oxide film are etched to form a pad oxide film pattern, a pad nitride film pattern, and a first hard mask layer pattern. Next, after the photoresist pattern is removed, a first insulating film spacer is formed on sidewalls of the first hard mask layer pattern, the pad nitride film pattern, and the pad oxide film pattern, and then the first insulating film spacer and the first hard mask layer pattern are etched. The semiconductor substrate 310 may be etched to form a trench 322 for device isolation.

Referring to FIG. 3B, the semiconductor substrate 310 is exposed by removing the first insulating layer spacer 318 and the pad oxide layer 312 below, and then, including the exposed semiconductor substrate 310 and the trench 322. An insulating film (not shown) for device isolation is formed on the surface. Next, the device isolation insulating film 320 is planarized and etched until the pad nitride film pattern 314 is exposed to form the device isolation structure 320 defining the active region 101 of FIG. 1.

According to an embodiment of the present invention, it is preferable that the removal process of the first insulating layer spacer 318 and the pad oxide layer 312 below is performed by a wet etching method. In addition, it is preferable that the insulating film for element isolation is an oxide film. According to another embodiment of the present invention, the planarization etching of the insulating film for device isolation to form the device isolation structure 320 is preferably performed by a CMP or etch back method.

Referring to FIG. 3C, after the device isolation structure 320 having a predetermined thickness is etched to lower its height, the pad nitride layer pattern 314 and the pad oxide layer 312 are removed to expose the semiconductor substrate 310. Next, after the buffer layer 324 is formed on the exposed semiconductor substrate 310, impurities are implanted into the semiconductor substrate 310 by performing a well and channel ion implantation process. Thereafter, the second hard mask layer 326 is formed on the entire structure.

According to one embodiment of the present invention, it is preferable to perform the removal process on the pad nitride layer pattern 314 and the pad oxide layer 312 by a wet etching method. The buffer layer 324 is formed of an oxide film, and the second hard mask layer 326 is selected from the group consisting of a polysilicon layer, an amorphous carbon film, a nitride film, a silicon nitride oxide (SiON) film, and a combination thereof. It is preferable to form one.

Referring to FIG. 3D, after forming a photoresist layer (not shown) on the second hard mask layer 326, the photoresist layer is exposed and developed with a recess gate mask (not shown) to form the recess gate region 103 of FIG. 1. A photoresist pattern 330 is defined. Next, the second hard mask layer 326 is etched using the photoresist pattern 330 as an etch mask to form a recess region (not shown) exposing the buffer layer 324 and the device isolation structure 320. The buffer layer 324 exposed in the recess region and the semiconductor substrate 310 having a predetermined thickness are etched to form a first recess 342 (that is, an upper recess channel structure). Thereafter, the photoresist pattern 330 is removed.

According to an embodiment of the present invention, the fin active region 332 is formed on the sidewalls of the device isolation structure 320 on both sides in the vertical direction, and the thickness t C of the fin active region 332 is the horizontal of the subsequent SOI channel structure. It is desirable to form thicker than the thickness t SOI by the thickness of the semiconductor substrate lost in the subsequent thermal oxidation process. The thickness t C of the fin type active region 332 is preferably 70 kPa to 1,150 kPa.

Referring to FIG. 3E, after forming a second insulating film (not shown) on the entire structure, the second insulating film spacer 334 is formed on the sidewall of the first recess 342. Next, the semiconductor substrate 310 exposed under the first recess 342 is etched to form a second recess 344. At this time, a recess channel structure 340 defined by the first recess 342 and the second recess 344 is formed.

According to one embodiment of the present invention, the etching process for forming the second recess 344 is preferably performed by an isotropic etching method. At this time, the horizontal line width of the second recess 344 in the horizontal direction is preferably greater than or equal to that of the first recess 342. In addition, the fin type active region 332 of FIG. 3D formed on both sidewalls of the device isolation structure 320 in the vertical direction is separated from the lower semiconductor substrate 310 by a predetermined distance to separate the device isolation structure 320 and the second insulating layer spacer 334. ) Forms an SOI channel structure 346. According to another embodiment of the present invention, the SOI channel structure 346 connects the semiconductor substrate 310 in which subsequent source / drain regions will be formed in the vertical direction. In addition, it is preferable that the predetermined distance separated between the SOI channel structure 346 and the semiconductor substrate 310 below is 200 mW to 2,000 mW.

Referring to FIG. 3F, after removing the second insulating layer spacer 334 and the remaining second hard mask layer 326, the buffer layer 324 is removed to form the recess channel structure 340 including the SOI channel structure 346. Fully expose the Next, after the gate insulating layer 350 is formed on the exposed semiconductor substrate 310 including the recess channel structure 340, the lower gate conductive layer 360 is formed on the entire structure to form the SOI channel structure 346. Recess recessed channel structure 340 is embedded. Thereafter, an upper gate conductive layer 370 and a gate hard mask layer 380 are formed on the lower gate conductive layer 360.

According to one embodiment of the present invention, it is preferable that the removal process for the remaining second hard mask layer 326 and the second insulating layer spacer 334 is performed by a wet etching method. In addition, the removal process for the buffer layer 324 is preferably performed by a wet etching method. According to another embodiment of the present invention, the lower gate conductive layer 360 is preferably formed of a polysilicon layer. In addition, the upper gate conductive layer 370 may include a cobalt (Co) layer, a nickel (Ni) layer, a titanium (Ti) layer, a titanium nitride (TiN) film, a tungsten (W) layer, a tungsten nitride (WN) film, and an aluminum ( Al) layer, copper (Cu) layer, tungsten silicide (WSi x ) layer, cobalt silicide (CoSi x ) layer, titanium silicide (TiSi x ) layer, nickel silicide (NiSi x ) layer, and combinations thereof. It is preferable to form one.

Referring to FIG. 3G, the gate hard mask layer pattern 382 is patterned by patterning the gate hard mask layer 380, the upper gate conductive layer 370, and the lower gate conductive layer 360 using a gate mask (not shown) as an etch mask. And a gate structure 390 formed of a stacked structure of the gate electrode 374. In this case, the gate electrode 374 has a stacked structure of the upper gate electrode 372 and the lower gate electrode 362. The lower gate electrode 362 may surround three surfaces of the junction SOI channel structure 346 at both sides of the device isolation structure 320 in the vertical direction, thereby improving current driving capability and improving short channel effects.

4A and 4B are cross-sectional views illustrating a process of manufacturing a semiconductor device according to another embodiment of the present invention. 4A (i) and 4B (i) are cross-sectional views taken along the line II ′ of FIG. 1, and FIGS. 4A (ii) and 4B (ii) are cross-sectional views taken along the line II-II ′ of FIG. 1. The pad oxide layer 412 and the pad nitride layer 414 are formed on the semiconductor substrate 410. Next, after forming a photoresist film (not shown) on the entire surface, it is exposed and developed with an element isolation mask to form a photoresist pattern (not shown). Subsequently, the pad nitride layer 414, the pad oxide layer 412, and the semiconductor substrate 410 having a predetermined thickness are etched using the photoresist pattern as a mask to form an isolation trench 422, and then the photoresist pattern is removed. Next, the pad nitride layer 414 having a predetermined thickness is etched to form a pad nitride layer pattern 416 having a reduced pad nitride layer 414 on the pad oxide layer 412.

According to an embodiment of the present disclosure, the thickness t 2 of one side of the pad nitride layer pattern 416 reduced by the etching process for the pad nitride layer 414 may be determined according to the horizontal thickness of the subsequent SOI channel structure. The thickness is preferably formed thicker by the thickness of the semiconductor substrate lost by subsequent etching and thermal oxidation processes. The thickness of one side of the pad nitride film pattern 416 is preferably 100 kPa to 1,200 kPa.

Referring to FIG. 4B, after etching the pad oxide layer 412 exposing the pad nitride layer pattern 416 as an etch mask, an insulation layer (not shown) is formed on the entire structure. Next, the device isolation structure 420 is formed by planarizing etching of the device isolation insulating layer until the pad nitride layer pattern 416 is exposed. According to an embodiment of the present invention, the planarization etching process for forming the device isolation structure 420 is preferably performed by a CMP or etch back method.

Thereafter, the process may proceed in the same manner as in FIGS. 3C to 3G.

As described above, the semiconductor device and the method of manufacturing the same according to the present invention can simplify the process by forming the SOI channel structure as an etching process for forming the device isolation structure and the recess channel structure. In addition, the horizontal thickness of the SOI channel structure may be determined by the thickness of the sidewall insulating layer formed when the device isolation structure is formed, thereby improving process margin. In addition, the SOI channel structure may be separated from the lower semiconductor substrate by a predetermined distance to prevent punch-through between the source and drain regions. As a result, the current driving capability of the device and the short channel effect can be improved. Accordingly, there is an advantage that a high speed low voltage semiconductor device can be provided by improving the controllability of the transistor.

In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (12)

Forming a pad insulating layer pattern on the semiconductor substrate; Forming a spacer on sidewalls of the pad insulating layer pattern; Forming a trench defining an active region by etching the semiconductor substrate using the spacer and the pad insulating layer pattern as an etch mask; Removing the spacers; Filling the trench to form an isolation structure; Removing the pad insulating layer pattern to expose the active region; Etching the exposed active region with a recess gate mask to form a first recess; Further etching the semiconductor substrate exposed under the first recess to form a second recess; Forming a gate insulating layer over the active region including a silicon-on-insulator (SOI) recess channel structure defined by the first recess and the second recess; And Forming a gate including a gate conductive layer filling the SOI recess channel structure. The method of claim 1, The pad insulating film pattern is formed of an oxide film, a nitride film, and a hard mask layer, wherein the hard mask layer is formed of any one selected from the group consisting of an oxide film, a polysilicon layer, and a stacked structure thereof. . The method of claim 1, The spacer removal process is a method of manufacturing a semiconductor device, characterized in that performed by a wet etching method. The method of claim 1, The device isolation structure forming step Forming an insulating film for isolation of the device to fill the trench; And And forming the device isolation structure by planarizing etching the device isolation insulating film until the pad insulating film pattern is exposed. The method of claim 4, wherein And the insulating film for device isolation formed at the interface between the trench and the device isolation structure is an oxide film. The method of claim 1, And forming a well and a channel ion implantation region in the semiconductor substrate under the active region. The method of claim 1, The first recess forming step Forming a hard mask layer on the semiconductor substrate; Applying a photoresist film on the hard mask layer; Exposing and developing the photoresist layer using an island type recess gate mask to form a photoresist pattern defining a recess gate region; Etching the hard mask layer and a portion of the semiconductor substrate using the photoresist pattern as an etch mask to form the first recess; Removing the photoresist pattern; And Removing the hard mask layer; And the first recess includes fin-type active regions on sidewalls of both device isolation structures in a length direction of the gate region. The method of claim 7, wherein Forming a gate insulating layer on the active region including the SOI recess channel structure Forming recess channel spacers on sidewalls of the first recesses; Isotropically etching the semiconductor substrate exposed under the first recess to form a second Forming a recess; Removing the recess channel spacers; And Removing the hard mask layer to form an SOI recess channel structure defined by the first recess and the second recess, And the SOI recess channel structure is spaced apart from the lower semiconductor substrate in the longitudinal direction of the gate region. The method of claim 8, The spaced distance between the SOI recess channel structure and the lower semiconductor substrate is 100 to 2,000 Å. Forming a pad insulating layer pattern on the semiconductor substrate; Etching the semiconductor substrate exposing the pad insulating layer pattern with an etching mask to form a trench defining an active region; Selectively etching a portion of the pad insulating layer pattern to expose a portion of the semiconductor substrate at an end of the active region; Forming a device isolation structure filling the trench including the exposed semiconductor substrate; Removing the pad insulating layer pattern to expose the active region; Etching the exposed active region with a recess gate mask to form a first recess; Further etching the semiconductor substrate exposed under the first recess to form a second recess; Forming a gate insulating layer on the active region including an SOI recess channel structure defined by the first recess and the second recess; And And forming a gate including a gate electrode filling the SOI recess channel structure. The method of claim 10, Forming a gate including a gate electrode filling the SOI recess channel structure Forming recess channel spacers on sidewalls of the first recesses; Isotropically etching the semiconductor substrate exposed under the first recess to form a second recess; And Removing the recess channel spacers to form an SOI recess channel structure defined by the first recess and the second recess, And the SOI recess channel structure is spaced apart from the lower semiconductor substrate in the longitudinal direction of the gate region. The method of claim 1, The spacer is a method of manufacturing a semiconductor device, characterized in that formed by any one selected from the group consisting of an oxide film, a nitride film, and a combination thereof.
KR1020070036465A 2007-04-13 2007-04-13 Semiconductor device and method for fabricating the same KR100855857B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070036465A KR100855857B1 (en) 2007-04-13 2007-04-13 Semiconductor device and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070036465A KR100855857B1 (en) 2007-04-13 2007-04-13 Semiconductor device and method for fabricating the same

Publications (1)

Publication Number Publication Date
KR100855857B1 true KR100855857B1 (en) 2008-09-01

Family

ID=40022237

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070036465A KR100855857B1 (en) 2007-04-13 2007-04-13 Semiconductor device and method for fabricating the same

Country Status (1)

Country Link
KR (1) KR100855857B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101213811B1 (en) 2010-04-15 2012-12-18 에스케이하이닉스 주식회사 Semiconductor device and method for forming the same
WO2014051762A1 (en) * 2012-09-28 2014-04-03 Intel Corporation Trench confined epitaxially grown device layer(s)
US9076886B2 (en) 2012-08-07 2015-07-07 Samsung Electronics Co., Ltd. Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050019363A (en) * 2003-08-18 2005-03-03 주식회사 케이이씨 Transistor and its manufacturing method
KR20050034879A (en) * 2003-10-10 2005-04-15 삼성전자주식회사 Method for forming recess channel trench pattern, method for fabricating recess channel transistor and recess channel transistor fabricated by the same
KR20050043424A (en) * 2003-11-06 2005-05-11 삼성전자주식회사 Method for fabrication recessed channel of transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050019363A (en) * 2003-08-18 2005-03-03 주식회사 케이이씨 Transistor and its manufacturing method
KR20050034879A (en) * 2003-10-10 2005-04-15 삼성전자주식회사 Method for forming recess channel trench pattern, method for fabricating recess channel transistor and recess channel transistor fabricated by the same
KR20050043424A (en) * 2003-11-06 2005-05-11 삼성전자주식회사 Method for fabrication recessed channel of transistor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101213811B1 (en) 2010-04-15 2012-12-18 에스케이하이닉스 주식회사 Semiconductor device and method for forming the same
US8536644B2 (en) 2010-04-15 2013-09-17 SK Hynix Inc. Semiconductor device having a buried gate and method for forming the same
US9076886B2 (en) 2012-08-07 2015-07-07 Samsung Electronics Co., Ltd. Semiconductor device
WO2014051762A1 (en) * 2012-09-28 2014-04-03 Intel Corporation Trench confined epitaxially grown device layer(s)
US8765563B2 (en) 2012-09-28 2014-07-01 Intel Corporation Trench confined epitaxially grown device layer(s)
EP2901472A4 (en) * 2012-09-28 2016-05-18 Intel Corp Trench confined epitaxially grown device layer(s)
US9634007B2 (en) 2012-09-28 2017-04-25 Intel Corporation Trench confined epitaxially grown device layer(s)

Similar Documents

Publication Publication Date Title
KR100745885B1 (en) Semiconductor device and method for fabricating the same
KR100720238B1 (en) Semiconductor device and method for fabricating the same
KR100689514B1 (en) Semiconductor device and method for fabricating the same
US7709328B2 (en) Semiconductor device and method for fabricating same
KR101087936B1 (en) Semiconductor device and method for forming using the same
KR100861211B1 (en) Semiconductor device and method for fabricating the same
KR100835278B1 (en) Semiconductor device having a recess-fin field effect transistor and methods of fabrication the same
KR100653536B1 (en) Method for fabricating fin fet of semiconductor device
KR100855857B1 (en) Semiconductor device and method for fabricating the same
KR100843900B1 (en) Semiconductor device and method for fabricating the same
KR100843855B1 (en) Semiconductor device and method for fabricating the same
KR20050107090A (en) Methods of forming a semiconductor device having a fin field effect transistor
US20080032466A1 (en) Method for Fabricating Semiconductor Device
CN109599366B (en) Semiconductor device and method of forming the same
KR100944356B1 (en) Semiconductor device and method of fabricating the same
KR100745882B1 (en) Semiconductor device and method for fabricating the same
CN109273407B (en) Semiconductor device and method of forming the same
KR100713941B1 (en) Semiconductor device and method of manufacturing the same
KR100929629B1 (en) Manufacturing Method of Semiconductor Device
KR20100028435A (en) Method for fabricating semiconductor device having saddle fin transistor
KR20080061985A (en) Semiconductor device and manufacturing method of the same
KR20060135226A (en) Method of manufacturing semiconductor device
KR20080090815A (en) Fin type gates of semiconductor device and method for forming the same
KR20090098282A (en) Saddle fin transistor and method for manufacturing the same
KR20080090811A (en) Fin type gates of semiconductor device and method for forming the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J201 Request for trial against refusal decision
AMND Amendment
B701 Decision to grant
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee