KR100824632B1 - Method of Manufacturing Semiconductor Device by 90nm Design Rule - Google Patents

Method of Manufacturing Semiconductor Device by 90nm Design Rule Download PDF

Info

Publication number
KR100824632B1
KR100824632B1 KR1020060083440A KR20060083440A KR100824632B1 KR 100824632 B1 KR100824632 B1 KR 100824632B1 KR 1020060083440 A KR1020060083440 A KR 1020060083440A KR 20060083440 A KR20060083440 A KR 20060083440A KR 100824632 B1 KR100824632 B1 KR 100824632B1
Authority
KR
South Korea
Prior art keywords
roughness
forming
silicon substrate
insulating film
semiconductor device
Prior art date
Application number
KR1020060083440A
Other languages
Korean (ko)
Other versions
KR20080020236A (en
Inventor
장정렬
Original Assignee
동부일렉트로닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부일렉트로닉스 주식회사 filed Critical 동부일렉트로닉스 주식회사
Priority to KR1020060083440A priority Critical patent/KR100824632B1/en
Publication of KR20080020236A publication Critical patent/KR20080020236A/en
Application granted granted Critical
Publication of KR100824632B1 publication Critical patent/KR100824632B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 90nm 디자인 룰에 따른 반도체 소자 형성방법에 있어서, 특히 절연막 내측벽에 형성된 불규칙적인 러프네스를 효과적으로 제거하는 반도체 소자 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor device in accordance with 90 nm design rules, and in particular, to a method for forming a semiconductor device for effectively removing irregular roughness formed on an inner wall of an insulating film.

본 발명에 따른 반도체 소자 형성방법은, 실리콘 기판상에 절연막 및 포토레지스트 패턴을 순차적으로 형성하는 단계, 상기 포토레지스트 패턴을 식각 마스크로 상기 실리콘 기판이 노출될 때까지 상기 절연막을 식각하는 단계, 상기 식각된 절연막 내측벽에 불규칙한 러프네스가 형성되면, 상기 절연막에 대해 러프네스 제거공정을 수행하여 상기 러프네스를 제거하는 단계 및 상기 러프네스를 제거한 후, 상기 실리콘 기판에 STI 공정을 수행하여 STI를 형성하는 단계를 포함하여 이루어지는 것이다. In the semiconductor device forming method according to the invention, the step of sequentially forming an insulating film and a photoresist pattern on a silicon substrate, etching the insulating film until the silicon substrate is exposed using the photoresist pattern as an etching mask, the When irregular roughness is formed on the inner wall of the etched insulating layer, a roughness removing process is performed on the insulating layer to remove the roughness, and after the roughness is removed, an STI process is performed on the silicon substrate. It comprises the step of forming.

LER, 누설전류, STI LER, Leakage Current, STI

Description

90ｎｍ 디자인 룰에 따른 반도체 소자 형성방법{Method of Manufacturing Semiconductor Device by 90nm Design Rule}Method of manufacturing semiconductor device according to 90nm design rule {Method of Manufacturing Semiconductor Device by 90nm Design Rule}

도 1은 종래 기술에서 ArF용 포토레지스트 패턴을 이용하여 실리콘 기판에 STI를 형성한 후 실리콘 기판의 상면을 SEM을 통해 촬영한 이미지.FIG. 1 is an image of an upper surface of a silicon substrate taken through an SEM after forming an STI on a silicon substrate using an ArF photoresist pattern according to the related art.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자 형성방법을 설명하기 위한 단면도.2A to 2E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

*** 도면의 주요 부분에 대한 부호의 설명 ****** Explanation of symbols for the main parts of the drawing ***

200 : 실리콘 기판 201 : 절연막200 silicon substrate 201 insulating film

202 : 제 1 실리콘 질화막 204 : 실리콘 산화막202: first silicon nitride film 204: silicon oxide film

206 : 제 2 실리콘 질화막206: second silicon nitride film

본 발명은 90nm 디자인 룰에 따른 반도체 소자 형성방법에 있어서, 절연막 내측벽에 형성된 불규칙적인 러프네스를 효과적으로 제거하는 반도체 소자 형성방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device for effectively removing irregular roughness formed on an inner wall of an insulating film in a method of forming a semiconductor device according to a 90 nm design rule.

도 1은 종래 기술에서 ArF용 포토레지스트 패턴을 이용하여 실리콘 기판에 STI를 형성한 후 실리콘 기판의 상면을 SEM(Scanning Electron Microscop)을 통해 촬영한 이미지이다.FIG. 1 is an image obtained by scanning electron microscop (SEM) of an upper surface of a silicon substrate after forming an STI on a silicon substrate using an ArF photoresist pattern in the prior art.

도 1에서 보는 바와 같이, 실리콘 기판 상부에 절연막(ONO:Oxide-Nitride-Oxide))을 형성하고, 상기 절연막(ONO:Oxide-Nitride-Oxide) 상부에 ArF용 포토레지스트를 형성한다. 그리고, 상기 절역만 상부에 형성된 ArF용 포토레지스트를 패터닝한 후, 상기 패터닝된 ArF용 포토레지스트를 식각 마스크로 상기 절연막을 선택적으로 식각한다. 그런 다음, STI 공정을 수행하여 상기 실리콘 기판에 STI를 형성한다.As shown in FIG. 1, an insulating film (ONO: Oxide-Nitride-Oxide) is formed on the silicon substrate, and an ArF photoresist is formed on the insulating film (ONO: Oxide-Nitride-Oxide). After the patterning of the ArF photoresist formed only on the region, the insulating layer is selectively etched using the patterned ArF photoresist as an etching mask. Then, an STI process is performed to form an STI on the silicon substrate.

그러나 이러한 반도체 소자 형성공정에서 ArF용 포토레지스트를 패터닝하는 경우에 ArF용 포토레지스트에 불규칙적인 러프네스(roughness)가 형성되고, 상기 불규칙한 러프네스가 형성된 포토레지스트를 식각 마스크로 식각공정을 수행하면, 식각 대상물인 상기 절연막 내측에도 불규칙적인 러프네스가 형성된다. 따라서, 상기 실리콘 기판의 활성화 영역을 형성하는 경우, 누설전류가 증가하는 문제점이 발생한다.However, when the ArF photoresist is patterned in the semiconductor device forming process, irregular roughness is formed on the ArF photoresist, and the etching process is performed using the photoresist on which the irregular roughness is formed using an etching mask. Irregular roughness is also formed inside the insulating film, which is an etching target. Therefore, when the active region of the silicon substrate is formed, a problem of increasing leakage current occurs.

본 발명은 상술한 바와 같은 종래 기술의 문제점을 해결하기 위하여 제안된 것으로, 러프네스(roughness) 제거공정을 추가로 수행하여 상기 절연막 내측에 형성된 불규칙적인 러프네스를 제거하는 반도체 소자 형성방법을 제공하는 데 목적이 있다.The present invention has been proposed to solve the problems of the prior art as described above, and further provides a method of forming a semiconductor device for removing the irregular roughness formed inside the insulating film by further performing a roughness (roughness) removing process. There is a purpose.

상기한 목적을 달성하기 위한 본 발명의 일실시 예에 따른 반도체 소자 형성방법의 일 특징은, 실리콘 기판상에 절연막 및 포토레지스트 패턴을 순차적으로 형성하는 단계, 상기 포토레지스트 패턴을 식각 마스크로 상기 실리콘 기판이 노출될 때까지 상기 절연막을 식각하는 단계, 상기 식각된 절연막 내측벽에 불규칙한 러프네스가 형성되면, 상기 절연막에 대해 러프네스 제거공정을 수행하여 상기 러프네스를 제거하는 단계 및 상기 러프네스를 제거한 후, 상기 실리콘 기판에 STI 공정을 수행하여 STI를 형성하는 단계를 포함하여 이루어지는 것이다.
보다 바람직하게, 상기 절연막은, 상기 실리콘 기판 상부에 제1 실리콘 질화막, 실리콘 산화막 및 제2 실리콘 질화막을 순차적으로 적층하여 형성한다.
보다 바람직하게, 상기 러프네스 제거 공정은, 5~30mTorr의 분위기 압력을 갖는 챔버 내에 300~800W의 소스 파워 및 10~80W의 바이어스 파워를 인가한 상태에서 CF계의 공정가스를 이용하여 5~20sec 동안 반응성 이온식각(Reactive Ion Etching) 공정을 수행한다.
보다 바람직하게, 상기 공정챔버 내에 상기 CF계의 공정 가스를 20~80sccm 유량으로 유입하되, 상기 CF계의 공정가스는 1~10sccm 유량의 수소가 첨가된 CF계 가스 및 1~5sccm 유량의 Cl계 가스를 포함한다. One feature of the method for forming a semiconductor device according to an embodiment of the present invention for achieving the above object is the step of sequentially forming an insulating film and a photoresist pattern on a silicon substrate, the photoresist pattern as an etching mask Etching the insulating film until the substrate is exposed; if irregular roughness is formed on the inner side of the etched insulating film, performing a roughness removing process on the insulating film to remove the roughness; After removal, the step of forming an STI by performing an STI process on the silicon substrate.
More preferably, the insulating film is formed by sequentially stacking a first silicon nitride film, a silicon oxide film, and a second silicon nitride film on the silicon substrate.
More preferably, the roughness removing process is performed using a CF-based process gas in a state in which a source power of 300 to 800 W and a bias power of 10 to 80 W are applied to a chamber having an atmospheric pressure of 5 to 30 mTorr. Reactive Ion Etching process is performed.
More preferably, the CF-based process gas is introduced into the process chamber at a flow rate of 20 to 80 sccm, but the CF-based process gas is a CF-based gas to which hydrogen is added at a flow rate of 1 to 10 sccm and a Cl system at a flow rate of 1 to 5 sccm. Contains gas.

삭제delete

삭제delete

삭제delete

삭제delete

삭제delete

삭제delete

이하에서는 첨부된 도면을 참조하여 본 발명에 따른 90nm 디자인 룰에 따른 STI 형성방법을 포함한 반도체 소자 형성방법에 대해서 상세히 설명한다.Hereinafter, a semiconductor device forming method including an STI forming method according to a 90nm design rule according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자 형성방법을 설명하기 위한 단면도이다.2A through 2E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

먼저, 도 2a를 참조하면, 소정의 반도체 회로 소자들(예를 들면, 트랜지스터, 다층의 금속 배선 등)을 포함하는 실리콘 반도체 기판(200) 상에 제1 실리콘 질화막(202), 실리콘 산화막(204), 제2 실리콘 질화막(206)을 순차적으로 적층한 절연막(201)을 형성한다. 이때, 상기 제1 실리콘 질화막(202) 및 상기 제2 실리콘 질화막(206)은 SiN 막을 이용할 수 있으며, 상기 실리콘 산화막(204)은 SiO2 막을 이용할 수 있다.First, referring to FIG. 2A, a first silicon nitride film 202 and a silicon oxide film 204 are formed on a silicon semiconductor substrate 200 including predetermined semiconductor circuit elements (eg, transistors, multilayer metal wirings, and the like). ), An insulating film 201 in which the second silicon nitride film 206 is sequentially stacked is formed. In this case, an SiN film may be used for the first silicon nitride film 202 and the second silicon nitride film 206, and an SiO 2 film may be used for the silicon oxide film 204.

삭제delete

그런 다음, 상기 제2 실리콘 질화막(206) 상에 트렌치를 형성시키기 위한 포토 레지스트 패턴(Photo Resist Pattern)(208)이 형성한다. 상기 포토 레지스트 패턴(208)은 상기 제2 실리콘 질화막(206) 상부에 포토 레지스트 물질(예를 들어, ArF용 PR)을 소정의 두께로 도포한 후, 사진식각공정(PEP: Photo etching process)을 통해 형성한다. 이때, 상기 포토레지스트 패턴(208)에 불규칙적인 러프네스가 형성된다.Then, a photo resist pattern 208 for forming a trench on the second silicon nitride film 206 is formed. The photoresist pattern 208 may apply a photoresist material (for example, an ArF PR) to a predetermined thickness on the second silicon nitride layer 206 and then perform a photo etching process (PEP). Form through. At this time, irregular roughness is formed in the photoresist pattern 208.

상기 불규칙적인 러프네스(212)가 형성된 포토레지스트 패턴(208)을 식각 마스크(Mask)로 상기 절연막 하부의 반도체 기판에 노출될 때까지 상기 절연막(201)을 식각한다. 그러면, 도 2b에 도시된 바와 같이, 상기 식각된 절연막(201)의 측벽에도 불규칙적인 러프네스가 형성된다. The insulating layer 201 is etched until the photoresist pattern 208 having the irregular roughness 212 is exposed to the semiconductor substrate under the insulating layer using an etch mask. Then, as shown in FIG. 2B, irregular roughness is formed on sidewalls of the etched insulating layer 201.

따라서, 상기 불규칙적인 러프네스가 형성된 포토레지스트 패턴(208)을 식각 마스크로 상기 절연막(201)을 식각하면, 도 2b 및 도 2c에 도시된 바와 같이, 식각 대상물인 상기 절연막(201)의 내측벽에도 불규칙한 러프네스(212) 예를 들어, LER(Line Edge Roughness)가 형성됨을 알 수 있다.Therefore, when the insulating film 201 is etched using the photoresist pattern 208 having the irregular roughness formed as an etching mask, as shown in FIGS. 2B and 2C, an inner wall of the insulating film 201 as an etching target is formed. In addition, it can be seen that irregular roughness 212, for example, LER (Line Edge Roughness) is formed.

도 2c는 포토레지스트 패턴(208)을 식각 마스크로 절연막(201)을 식각한 후, 그 상면을 SEM(Scanning Electron Microscope)을 통해 촬영한 이미지이다.2C is an image obtained by etching the insulating film 201 using the photoresist pattern 208 as an etching mask, and then photographing an upper surface of the insulating film 20 through a scanning electron microscope (SEM).

상기 식각 공정을 통해 절연막(201)을 식각한 후, 에싱(ashing) 및 세정(cleaning) 공정을 통해 상기 절연막(201) 상에 잔존하는 포토 레지스트 패턴(208)을 제거한 후, 러프네스 제거공정을 수행하여 상기 절연막(201)의 내측벽에 형성된 불규칙적인 러프네스(212)를 제거한다. 그러면, 도 2d에서 도시된 바와 같이, 상기 절연막(201) 내측벽의 평탄도를 향상시킬 수 있다.After the insulating film 201 is etched through the etching process, the photoresist pattern 208 remaining on the insulating film 201 is removed through an ashing and cleaning process, and then a roughness removing process is performed. By removing the irregular roughness 212 formed on the inner wall of the insulating film 201. Then, as illustrated in FIG. 2D, the flatness of the inner wall of the insulating film 201 may be improved.

도 2d는 상기와 같은 러프네스 제거공정을 통해 불규칙적인 러프네스가 제거된 실리콘 기판(200)의 상면을 SEM을 통해 촬영한 이미지이다.FIG. 2D illustrates an image of the top surface of the silicon substrate 200 from which the irregular roughness is removed through the roughness removing process as described above.

이때, 상기 러프네스 제거공정은, 예를 들어, 5~30mTorr의 압력으로 유지되는 공정 챔버 내에서 CF계의 공정가스를 이용하여 300~800W의 소스파워(source power) 및 10~80W의 바이어스 파워(bias power)로 5~20sec 동안 반응성 이온식각을 수행하는 것이다.
상기 제시된 러프네스 제거공정 조건을 이용하여 절연막(201) 내측 벽에 형성된 불규칙적인 러프네스 제거 동작을 상세히 설명하면, 5~30mTorr의 압력이 유지되는 공정챔버 내에서 5~20sec 동안, 300~800W의 소스파워와 10~80W의 바이어스 파워로 CF계의 공정가스를 이용하여 반응성 이온 식각 공정을 수행하는 것이다. 이때, 상기 CF계의 공정가스는, 예를 들어, 20~80sccm의 CF계 가스에 수소가 첨가된 CF계 가스와 Cl계 가스를 포함하되, 상기 수소가 첨가된 CF계 가스인 CH2F2 가스를 1~10sccm으로 포함하고, Cl계 가스인 Cl2 가스를 1~5sccm으로 포함한다. At this time, the roughness removal process, for example, using a CF-based process gas in the process chamber maintained at a pressure of 5 ~ 30mTorr 300 ~ 800W source power (bias power) and 10 ~ 80W bias power (bias power) to perform reactive ion etching for 5-20 sec.
Using the roughness removal process conditions described above, the irregular roughness removal operation formed on the inner wall of the insulating film 201 will be described in detail. For 5 to 20 sec in a process chamber in which a pressure of 5 to 30 mTorr is maintained, Reactive ion etching is performed by using CF-based process gas with source power and bias power of 10 ~ 80W. In this case, the CF-based process gas includes, for example, a CF-based gas and a Cl-based gas to which hydrogen is added to a CF-based gas of 20 to 80 sccm, but the CF-based gas to which the hydrogen is added is CH 2 F 2. It includes a gas with 1 ~ 10sccm and includes Cl 2 gas, Cl-based gas as a 1 ~ 5sccm.

삭제delete

이와 같은 CF계의 공정가스를 이용하여, 반응성 이온 식각(RIE:Reactive Ion Etching) 또는 자기강화 반응성 이온식각(MERIE:Magnetic Enhanced Reative Ion Etching) 방법을 통해 절연막(201) 내측 벽에 형성된 불규칙한 러프네스를 도 2e에서 도시된 바와 같이 절연막의 내측벽을 평탄하게 식각한 후(불규칙적인 러프네스 제거), STI(Shallow Trench Isolation) 공정을 통해 실리콘 기판(200a)에 STI(208)를 형성한다. Using such a CF-based process gas, irregular roughness formed on the inner wall of the insulating film 201 by using reactive ion etching (RIE) or magnetic enhanced reactive ion etching (MERIE). As shown in FIG. 2E, the inner wall of the insulating layer is etched evenly (irregular roughness removal), and then the STI 208 is formed on the silicon substrate 200a through a shallow trench isolation (STI) process.

따라서, 본 발명을 통해 90nm 이하의 STI 형성공정에서 발생하는 LER을 개선하여 패턴을 형성할 수 있으므로, 종래 실리콘 기판의 활성화 영역에서 누설전류가 증가하여 발생하는 것을 방지할 수 있다.Therefore, according to the present invention, since the pattern can be formed by improving the LER generated in the STI forming process of 90 nm or less, it is possible to prevent the leakage current from increasing in the activation region of the conventional silicon substrate.

이상과 같이 본 발명은 비록 한정된 실시 예와 도면에 의해 설명되었으나, 본 발명은 상기의 실시 예에 한정되는 것은 아니며, 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면, 이러한 기재로부터 다양한 수정 및 변형이 가능하다.As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above-described embodiments, and those skilled in the art to which the present invention pertains, various modifications and Modifications are possible.

그러므로 본 발명의 범위는 설명된 실시 예에 국한되어 정해져서는 아니 되 며, 후술하는 특허청구범위뿐만 아니라 이 특허 청구범위와 균등한 것들에 의해 정해져야 한다.Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자 형성방법은, 러프네스 제거공정을 추가적으로 수행하여 절연막 내측 벽에 형성된 불규칙적인 러프네스를 제거함으로써, 실리콘 기판의 활성화 영역을 형성 후에 누설 전류가 증가하는 현상을 방지할 수 있는 효과가 있다. As described above, in the method of forming a semiconductor device according to the present invention, by additionally performing a roughness removing process to remove irregular roughness formed on the inner wall of the insulating layer, leakage current increases after forming the active region of the silicon substrate. There is an effect that can prevent the phenomenon.

Claims (7)

실리콘 기판상에 절연막 및 포토레지스트 패턴을 순차적으로 형성하는 단계; Sequentially forming an insulating film and a photoresist pattern on the silicon substrate; 상기 포토레지스트 패턴을 식각 마스크로 상기 실리콘 기판이 노출될 때까지 상기 절연막을 식각하는 단계; Etching the insulating layer using the photoresist pattern as an etching mask until the silicon substrate is exposed; 상기 식각된 절연막 내측벽에 불규칙한 러프네스가 형성되면, 상기 절연막에 대해 러프네스 제거공정을 수행하여 상기 러프네스를 제거하는 단계; 및If irregular roughness is formed on the inner sidewall of the etched insulating layer, removing the roughness by performing a roughness removing process on the insulating layer; And 상기 러프네스가 제거된 상기 절연막을 식각 마스크로 이용하여 상기 실리콘 기판에 STI를 형성하는 단계를 포함하여 이루어지는 반도체 소자 형성방법. Forming an STI on the silicon substrate using the insulating film from which the roughness is removed as an etching mask. 제 1 항에 있어서, The method of claim 1, 상기 절연막은, 상기 실리콘 기판 상부에 제1 실리콘 질화막, 실리콘 산화막 및 제2 실리콘 질화막을 순차적으로 적층하여 형성하는 것을 특징으로 하는 반도체 소자 형성방법.And the insulating film is formed by sequentially laminating a first silicon nitride film, a silicon oxide film, and a second silicon nitride film on the silicon substrate. 제 1 항에 있어서, The method of claim 1, 상기 러프네스 제거 공정은, 5~30mTorr의 분위기 압력을 갖는 공정챔버 내에 300~800W의 소스 파워 및 10~80W의 바이어스 파워를 인가한 상태에서 CF계의 공정가스를 이용하여 5~20sec 동안 반응성 이온식각(Reactive Ion Etching)을 수행하는 것을 특징으로 하는 반도체 소자 형성방법. The roughness removal process is reactive ions for 5 to 20 seconds using a CF-based process gas while applying a source power of 300 to 800 W and a bias power of 10 to 80 W in a process chamber having an atmospheric pressure of 5 to 30 mTorr. A method of forming a semiconductor device, characterized in that to perform etching (Reactive Ion Etching). 제 3 항에 있어서, The method of claim 3, wherein 상기 공정챔버 내에 상기 CF계의 공정 가스를 20~80sccm 유량으로 유입하되, 상기 CF계의 공정가스는 1~10sccm 유량의 수소가 첨가된 CF계 가스 및 1~5sccm 유량의 Cl계 가스를 포함하는 것을 특징으로 반도체 소자 형성방법. The CF-based process gas is introduced into the process chamber at a flow rate of 20 to 80 sccm, wherein the CF-based process gas includes a CF-based gas at which hydrogen is added at a flow rate of 1 to 10 sccm and a Cl-based gas at a flow rate of 1 to 5 sccm. Method for forming a semiconductor device, characterized in that. 삭제delete 삭제delete 삭제delete
KR1020060083440A 2006-08-31 2006-08-31 Method of Manufacturing Semiconductor Device by 90nm Design Rule KR100824632B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060083440A KR100824632B1 (en) 2006-08-31 2006-08-31 Method of Manufacturing Semiconductor Device by 90nm Design Rule

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060083440A KR100824632B1 (en) 2006-08-31 2006-08-31 Method of Manufacturing Semiconductor Device by 90nm Design Rule

Publications (2)

Publication Number Publication Date
KR20080020236A KR20080020236A (en) 2008-03-05
KR100824632B1 true KR100824632B1 (en) 2008-04-25

Family

ID=39395291

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060083440A KR100824632B1 (en) 2006-08-31 2006-08-31 Method of Manufacturing Semiconductor Device by 90nm Design Rule

Country Status (1)

Country Link
KR (1) KR100824632B1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006053A (en) * 1996-06-26 1998-03-30 문정환 Method for forming a separation film of a semiconductor device
KR20050101036A (en) * 2004-04-16 2005-10-20 주식회사 하이닉스반도체 Method for forming metal wiring of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006053A (en) * 1996-06-26 1998-03-30 문정환 Method for forming a separation film of a semiconductor device
KR20050101036A (en) * 2004-04-16 2005-10-20 주식회사 하이닉스반도체 Method for forming metal wiring of semiconductor device

Also Published As

Publication number Publication date
KR20080020236A (en) 2008-03-05

Similar Documents

Publication Publication Date Title
JP4476196B2 (en) Manufacturing method of semiconductor device
US7169682B2 (en) Method for manufacturing semiconductor device
US20070111467A1 (en) Method for forming trench using hard mask with high selectivity and isolation method for semiconductor device using the same
KR100607326B1 (en) Method for fabricating semiconductor device
US7384869B2 (en) Protection of silicon from phosphoric acid using thick chemical oxide
KR100824632B1 (en) Method of Manufacturing Semiconductor Device by 90nm Design Rule
US6924217B2 (en) Method of forming trench in semiconductor device
JP2008053438A (en) Method of manufacturing semiconductor device
JP2005129946A (en) Post plasma clean process for a hardmask
US20090197388A1 (en) Method of manufacturing semiconductor device
KR100643484B1 (en) method for manufacturing semiconductor devices
KR100423064B1 (en) Method of manufacturing a semiconductor device
KR100356478B1 (en) Method of forming a gate electrode in a semiconductor device
KR100481557B1 (en) Method for making narrow sti by using double nitride etch
KR100561513B1 (en) Method of Shallow Trench Isolation In Semiconductor Device
KR100733558B1 (en) Method for fabricating semiconductor device
KR101006510B1 (en) Method for forming isolation layer of semiconductor device
KR100939161B1 (en) Method for fabricating device isolation film of semiconductor device
KR20100032039A (en) Method for manufacturing shallow trench isolation of semiconductor device
KR20070036203A (en) Method for manufacturing recess gate in semiconductor device
KR20000028124A (en) Separation method for trench element of semiconductor device
KR20050011471A (en) Method for forming isolation layer of semiconductor device
KR20060010446A (en) Method of forming a pattern in a semiconductor device
KR20060074693A (en) Method for forming trench in semiconductor device
KR20080002533A (en) Method for fabricating fine pattern in semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110322

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee