KR100481557B1 - Method for making narrow sti by using double nitride etch - Google Patents
Method for making narrow sti by using double nitride etch Download PDFInfo
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- KR100481557B1 KR100481557B1 KR10-2002-0054014A KR20020054014A KR100481557B1 KR 100481557 B1 KR100481557 B1 KR 100481557B1 KR 20020054014 A KR20020054014 A KR 20020054014A KR 100481557 B1 KR100481557 B1 KR 100481557B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
Abstract
본 발명은 반도체 소자에 있어서, 디자인 룰이 점차 감소함에 따라 발생되는 내로우한 STI 폭을 형성하기 위한 것으로, 이를 위한 작용은 실리콘 기판 상에 얇은 초기 산화막과 제1질화막을 증착한 후, 그 상부에 타겟으로 하는 스페이스 보다 큰 패터닝 작업을 수행한 상태에서, 포트 레지스트 패턴을 형성하는 단계와, 포토 레지스트 패턴을 마스크로 드러난 제1질화막을 시간 식각을 통하여 일정 두께의 제1질화막이 남아있도록 식각하는 단계와, 포토 레지스트 패턴을 제거하고 제1질화막 상부 전면에 제2질화막을 증착하는 단계와, 제2질화막과 제1질화막을 에치백 공정을 이용하여 더블 식각을 실시하여 트랜치 형성을 위한 트랜치 패턴을 형성하는 단계와, 트랜치 패턴을 마스크로 초기 산화막과 실리콘 기판을 식각하여 트랜치를 형성하는 단계를 포함한다. 따라서, 트랜치가 형성된 상태에서 다른 질화막 단차로 인해 형성되는 스페이스를 최종적으로 원하는 타겟의 스페이스로 형성하며, STI 스페이스의 감소로 인한 패터닝의 어려움을 개선하여 디바이스의 쉬링크가 가능하게 할 수 있는 효과가 있다. The present invention is to form a narrow STI width generated as the design rule is gradually reduced in the semiconductor device, the effect is to deposit a thin initial oxide film and the first nitride film on the silicon substrate, and then Forming a port resist pattern, and etching the first nitride film having a predetermined thickness through time etching the first nitride film exposed by using the photoresist pattern as a mask while performing a patterning operation larger than a target space for Removing the photoresist pattern, depositing a second nitride film on the entire upper surface of the first nitride film, and etching the second nitride film and the first nitride film using an etch back process to form a trench pattern for trench formation. Forming the trench by etching the initial oxide layer and the silicon substrate using the trench pattern as a mask; The. Accordingly, in the trench formed state, the space formed by the other nitride film step is finally formed as the space of the desired target, and the difficulty of patterning due to the reduction of the STI space is improved, thereby enabling the device to have a shrinkage. have.
Description
본 발명은 더블 질화막 식각(double netride etch)을 이용한 내로우(narrow) 에스티아이(Shallow Trench for transistor Isolation, STI) 형성방법에 관한 것으로, 특히 0.25㎛ 이하의 반도체 소자 제조에 있어서, 디자인 룰(Design rule)이 점차 감소함에 따라 발생되는 내로우한 STI 폭을 형성할 수 있도록 하는 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a narrow trench for transistor isolation (STI) using double netride etch, and in particular, in manufacturing semiconductor devices having a thickness of 0.25 μm or less, design rules To a narrow STI width that is generated as) gradually decreases.
통상적으로, 반도체 소자 제조에 있어서, 디자인 룰(design rule)이 점차 감소함에 따라 내로우한 폭을 가지는 STI의 제조가 필요한데, 0.25㎛ 이상의 스페이스(space)를 갖는 STI의 경우에는 패터닝(patterning) 방법의 개선으로 조절이 가능하다. In general, in the manufacture of semiconductor devices, as the design rule gradually decreases, manufacturing of STIs having a narrow width is required. In the case of STIs having a space of 0.25 μm or more, a patterning method is required. Can be adjusted by the improvement.
도 1을 참조하면, 종래 반도체 제조 공정을 도시한 도면으로서, 실리콘 기판(Si-substrate)(10) 상에 산화막(oxide)(20)과 질화막(nitride)(30)을 형성한 후, 그 상부에 포토 레지스트 패턴(40)을 형성한다.Referring to FIG. 1, a conventional semiconductor manufacturing process is illustrated. An oxide film 20 and a nitride film 30 are formed on a silicon substrate 10, and then, an upper portion thereof. The photoresist pattern 40 is formed in the film.
포토 레지스트 패턴(40)을 형성한 후, 산화막과 질화막을 엔트 포인트(endpoint) 장비를 이용하여 식각시킨 상태에서, 포트 레지스트 패턴(40)을 스트립(strip)시킨 후, 실리콘 식각(silicon etch)을 시간(time)을 이용하여 식각(etch)을 실시하여 트랜치(trench)(60)를 형성한다. After the photoresist pattern 40 is formed, the oxide and nitride films are etched using an endpoint device, and then the port resist pattern 40 is stripped, and then silicon etch is performed. Using a time (etch) is etched to form a trench (60).
이러한 방법은, 0.18㎛ 테크놀로지(technology) 까지는 STI의 스페이스가 0.24㎛로 패터닝을 하는데 문제가 발생할 가능성은 크지 않았다. In this method, the problem of patterning the space of the STI to 0.24 μm until 0.18 μm technology is not high.
그러나, 0.15㎛나 0.13㎛ 등으로 테크놀로지가 변화되면서 요구되어지는 STI 스페이스가 0.21㎛, 0.18㎛ 등으로 줄어들게 되어 단순하게 패터닝 후 식각(etch)하는 방법으로는 내로우한 STI 폭을 형성할 수 없어 디바이스의 쉬링크(shrink)가 불가능하게 되는 문제점이 발생한다. However, as the technology changes to 0.15 μm or 0.13 μm, the required STI space is reduced to 0.21 μm, 0.18 μm, etc., and it is impossible to form a narrow STI width by simply etching after patterning. The problem arises that the shrinking of the device becomes impossible.
따라서, 본 발명은 상술한 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 0.25㎛ 이하의 반도체 소자 제조에 있어서, 디자인 룰(Design rule)이 점차 감소함에 따라 발생되는 내로우한 STI 폭을 형성하도록 하는 더블 질화막 식각을 이용한 내로우 에스티아이 형성방법을 제공함에 있다. Accordingly, the present invention has been made to solve the above-described problems, the object of which is to produce a narrow STI width generated as the design rule gradually decreases in the manufacture of semiconductor devices of 0.25 μm or less. The present invention provides a method for forming narrow estee using double nitride film etching.
이러한 목적을 달성하기 위한 본 발명에서 더블 질화막 식각을 이용한 내로우 에스티아이 형성방법은, 실리콘 기판 상에 얇은 초기 산화막과 제1질화막을 증착한 후, 그 상부에 타겟으로 하는 스페이스 보다 큰 패터닝 작업을 수행한 상태에서, 포트 레지스트 패턴을 형성하는 단계와, 포토 레지스트 패턴을 마스크로 드러난 제1질화막을 시간 식각을 통하여 일정 두께의 제1질화막이 남아있도록 식각하는 단계와, 포토 레지스트 패턴을 제거하고 제1질화막 상부 전면에 제2질화막을 증착하는 단계와, 제2질화막과 제1질화막을 에치백 공정을 이용하여 더블 식각을 실시하여 트랜치 형성을 위한 트랜치 패턴을 형성하는 단계와, 트랜치 패턴을 마스크로 초기 산화막과 실리콘 기판을 식각하여 트랜치를 형성하는 단계를 포함하는 것을 특징으로 한다.In the present invention for achieving the above object, a narrow estee forming method using double nitride film etching is performed by depositing a thin initial oxide film and a first nitride film on a silicon substrate, and then performing a patterning operation larger than a target space on the top. In one state, forming a port resist pattern, etching the first nitride film exposed by using the photoresist pattern as a mask to etch the first nitride film having a predetermined thickness through time etching, and removing the photoresist pattern and removing the first resist film. Depositing a second nitride film on the entire upper surface of the nitride film, performing a double etching of the second nitride film and the first nitride film using an etch back process to form a trench pattern for trench formation, and initializing the trench pattern using a mask Etching the oxide film and the silicon substrate to form a trench.
이하, 첨부된 도면을 참조하여 본 발명의 구성 및 동작에 대하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the present invention.
도 2a 내지 도 2d는 본 발명에 따른 더블 질화막 식각을 이용한 내로우 에스티아이 형성방법에 대하여 도시한 도면이다.2A to 2D are views illustrating a narrow estee forming method using double nitride film etching according to the present invention.
즉, 도 2a를 참조하면, N형 또는 P형 단결정 실리콘 기판(Si-Substrate)(10) 상에 얇은 초기 산화막(20)과 질화막(30)을 증착하고, 그 상부에 포토 레지스트를 형성하고 타겟(target)으로 하는 스페이스 보다 큰 패터닝(patterning) 작업을 수행하여 포트 레지스트 패턴(40)을 형성한다. 다음으로, 도 2b에 도시된 바와 같이, 포토 레지스트 패턴(40)을 마스크로 드러난 질화막(30)을 시간 식각(time etch)을 통하여 일정 두께의 질화막(30)이 남아있게 식각을 실시한다. 이때, 질화막의 두께는 후속으로 진행될 사이드 월(side wall) 식각을 통하여 최종 타겟(target)의 스페이스가 형성될 수 있는 정도의 두께가 남을 수 있도록 시간을 조절하여 형성한다. That is, referring to FIG. 2A, a thin initial oxide film 20 and a nitride film 30 are deposited on an N-type or P-type single crystal silicon substrate (Si-Substrate) 10, and a photoresist is formed on the target. The port resist pattern 40 is formed by performing a patterning operation larger than the target space. Next, as illustrated in FIG. 2B, the nitride film 30 exposed by using the photoresist pattern 40 as a mask is etched so that the nitride film 30 having a predetermined thickness remains through time etching. At this time, the thickness of the nitride film is formed by adjusting the time so that the thickness of the space of the final target can be formed through side wall etching to be performed subsequently.
삭제delete
이후, 도 2c와 같이, 포토 레지스트 패턴(40)을 제거한 후 단차를 가진 질화막(30) 상부 전면에 질화막(50)을 더블로 증착한다. 이때, 식각이 이미 진행된 부분과 식각이 진행되지 않은 부분의 단차가 발생하며, 만약 타겟으로 하는 크리티컬 디멘젼(Critical Dimension, CD) 보다 패턴을 크게 진행했거나, 또는 작게 진행하였을 경우 증착하는 질화막(50)의 두께를 조절하여 최종 타겟 CD를 확보한다.Thereafter, as shown in FIG. 2C, after the photoresist pattern 40 is removed, the nitride film 50 is double deposited on the entire upper surface of the nitride film 30 having the step difference. At this time, a step between the portion where the etching has already proceeded and the portion where the etching has not proceeded occurs, and if the pattern is made larger or smaller than the critical dimension (CD), the deposition nitride film 50 is deposited. Adjust the thickness of to secure the final target CD.
마지막으로, 도 2d를 참조하면, 질화막(50)이 증착된 상태에서, 에치백(etchback) 공정을 이용하여 더블 식각(etch)을 실시하여 질화막 단차로 인해 형성되는 스페이스를 최종적으로 원하는 타겟의 스페이스로 형성한다. 즉, 더블 식각에 의해 질화막(50)이 질화막(30)의 측벽에 스페이서로 형성되며 계속하여 에치백에 의해 식각 공정이 이루어져 단차에 의해 초기 식각된 영역은 완전히 제거되며, 초기 식각되지 않은 영역과 측벽으로 형성된 질화막(50)에 의해 트랜치 형성을 위한 트랜치 패턴에 의해 드러난 초기 산화막(20)과 실리콘 기판(10)을 식각하여 트랜치(60)를 형성한다. Lastly, referring to FIG. 2D, in the state in which the nitride film 50 is deposited, the space formed by the nitride film step may be finally etched by double etching using an etchback process. To form. That is, the nitride film 50 is formed as a spacer on the sidewall of the nitride film 30 by double etching, and then an etching process is performed by etch back to completely remove the region that is initially etched by the step. The trench 60 is formed by etching the initial oxide film 20 and the silicon substrate 10 exposed by the trench pattern for trench formation by the nitride film 50 formed as sidewalls.
상기와 같이 설명한 본 발명은 디자인 룰(Design rule)이 점차 감소함에 따라 발생되는 내로우한 STI 폭을 형성함으로써, STI 스페이스의 감소로 인한 패터닝(patterning)의 어려움을 개선하여 디바이스의 쉬링크(shrink)가 가능하게 할 수 있는 효과가 있다. As described above, the present invention forms a narrow STI width generated as the design rule gradually decreases, thereby improving the difficulty of patterning due to the reduction of the STI space, thereby reducing the shrinkage of the device. ) Has the effect of enabling it.
도 1은 종래 반도체 제조 공정에 대하여 도시한 도면이며,1 is a view showing a conventional semiconductor manufacturing process,
도 2는 본 발명에 따른 더블 질화막 식각을 이용한 내로우 에스티아이 형성방법에 대하여 도시한 도면이다.2 is a view illustrating a narrow estee forming method using double nitride film etching according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 실리콘 기판 20 : 산화막10 silicon substrate 20 oxide film
30 : 질화막 40 : 포트 레지스트30 nitride film 40 port resist
50 : 질화막 60 : 트랜치50: nitride film 60: trench
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990003538A (en) * | 1997-06-25 | 1999-01-15 | 김영환 | Manufacturing method of semiconductor device |
| KR19990057378A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Method of forming device isolation film of semiconductor device |
| KR20000042870A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Forming method of trench of semiconductor device |
| KR20000073800A (en) * | 1999-05-14 | 2000-12-05 | 김영환 | Manufacturing method for isolation in semiconductor device |
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- 2002-09-07 KR KR10-2002-0054014A patent/KR100481557B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990003538A (en) * | 1997-06-25 | 1999-01-15 | 김영환 | Manufacturing method of semiconductor device |
| KR19990057378A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Method of forming device isolation film of semiconductor device |
| KR20000042870A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Forming method of trench of semiconductor device |
| KR20000073800A (en) * | 1999-05-14 | 2000-12-05 | 김영환 | Manufacturing method for isolation in semiconductor device |
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