KR100772706B1 - Method for fabricating contact in semiconductor device - Google Patents

Method for fabricating contact in semiconductor device Download PDF

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KR100772706B1
KR100772706B1 KR1020060095066A KR20060095066A KR100772706B1 KR 100772706 B1 KR100772706 B1 KR 100772706B1 KR 1020060095066 A KR1020060095066 A KR 1020060095066A KR 20060095066 A KR20060095066 A KR 20060095066A KR 100772706 B1 KR100772706 B1 KR 100772706B1
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amorphous carbon
carbon layer
contact hole
layer
semiconductor device
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Korean (ko)
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조성윤
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of forming a contact hole in a semiconductor device is provided to eliminate a bowing from an upper portion of the contact hole by laminating amorphous carbon layers at different temperature atmospheres. An insulating layer(22) is formed on a substrate(21), and then a first amorphous carbon layer and a second amorphous carbon layer are formed on the insulating layer, in which the first amorphous carbon layer is formed at a lower temperature lower relative to the second amorphous carbon layer. The second and first amorphous carbon layers are selectively etched, and then the insulating layer is etched to form a contact hole(28).

Description

반도체 소자의 콘택홀 제조 방법{METHOD FOR FABRICATING CONTACT IN SEMICONDUCTOR DEVICE}Method for manufacturing contact hole of semiconductor device {METHOD FOR FABRICATING CONTACT IN SEMICONDUCTOR DEVICE}

도 1은 종래 기술에 따른 반도체 소자의 콘택홀 제조 방법을 도시한 단면도,1 is a cross-sectional view showing a method for manufacturing a contact hole in a semiconductor device according to the prior art;

도 2a 내지 도 2f는 본 발명의 일실시예에 따른 반도체 소자의 콘택홀 제조 방법을 도시한 단면도. 2A to 2F are cross-sectional views illustrating a method of manufacturing a contact hole in a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 기판 22 : 층간절연막21 substrate 22 interlayer insulating film

23 : 제1비정질 카본층 24 : 제2비정질 카본층23: first amorphous carbon layer 24: second amorphous carbon layer

25 : SiON막 26 : 반사방지막25 SiON film 26 Antireflection film

27 : 포토레지스트 패턴 28 : 콘택홀27: photoresist pattern 28: contact hole

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 깊은 콘택홀(Deep contact hole) 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing deep contact holes in a semiconductor device.

일반적으로, 반도체 소자는 그 내부에 다수의 단위 소자들을 포함하여 이루어진다. 반도체 소자가 고집적화되면서 일정한 셀(cell) 면적 상에 고밀도로 여러 요소들을 형성하여야 하며, 이로 인하여 단위 소자 예를 들면 트랜지스터, 캐패시터들의 크기는 점차 줄어들고 있다. In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices become highly integrated, various elements must be formed at a high density on a certain cell area, and thus, the size of unit devices, for example, transistors and capacitors, is gradually reduced.

특히, DRAM(Dynamic Random Access Memory)과 같은 반도체 메모리 장치에서 디자인 룰(Design rule)이 감소하면서 셀의 내부에 형성되는 단위 소자들의 크기가 점차 작아지지만, 소자의 용량을 확보하기 위해서 종횡비(Aspect ratio)의 증가가 불가피하다.In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule decreases, the size of the unit devices formed inside the cell gradually decreases, but in order to secure device capacity, the aspect ratio (Aspect ratio) is used. ) Is inevitable.

도 1은 종래 기술에 따른 반도체 소자의 콘택홀 제조 방법을 도시한 단면도이다.1 is a cross-sectional view illustrating a method for manufacturing a contact hole in a semiconductor device according to the prior art.

도 1에 도시된 바와 같이, 소정의 반도체 공정이 진행된 기판(11) 상부에 층간절연막(12)을 증착한다. 층간절연막(12)의 소정 영역 상부에 비정질 카본(Amorphous Carbon) 하드마스크(13)를 형성한 후, 비정질 카본 하드마스크(13)를 식각 베리어로 층간절연막(12)을 식각하여 기판(11)의 표면을 드러내는 콘택홀(14)을 형성한다. 콘택홀(14)을 형성하면서 비정질 카본 하드마스크(13)는 일부 식각 손실되며, 잔류하는 비정질 카본 하드마스크(13)는 스트립(Strip)한다.As illustrated in FIG. 1, an interlayer insulating layer 12 is deposited on the substrate 11 on which a predetermined semiconductor process is performed. After the amorphous carbon hard mask 13 is formed on the predetermined region of the interlayer insulating layer 12, the interlayer insulating layer 12 is etched using the amorphous carbon hard mask 13 as an etch barrier to etch the substrate 11. A contact hole 14 exposing the surface is formed. While forming the contact hole 14, the amorphous carbon hard mask 13 is partially etched away, and the remaining amorphous carbon hard mask 13 is stripped.

그러나, 상술한 종래 기술에서 반도체 소자가 고집적화될수록 종횡비(Aspect ratio)가 높아지므로 식각 난이도가 증가하게 된다. 특히, 반도체 소자의 깊은 콘택홀 식각시, 인가되는 식각 플라즈마가 콘택홀의 상부에 부딪혀 콘택홀의 상부에 보잉(Bowing)을 유발시킨다. 이러한 보잉으로 인해, 후속 공정에서 콘택홀에 금속막(예컨대, 텅스텐 또는 알루미늄막)을 매립할 때, 콘택홀 내부에 보이드(void)를 발생시키므로 소자 특성에 악영향을 미치고 있다. 보이드와 같은 현상은 소자의 불량 현상으로 이어져 제조 수율을 감소시키고 소자 특성을 저하시키는 문제가 있다.However, in the above-described conventional technology, as the semiconductor device is highly integrated, the aspect ratio is increased, so that the etching difficulty increases. In particular, during the deep contact hole etching of the semiconductor device, an etch plasma is applied to the upper part of the contact hole to cause bowing on the upper part of the contact hole. Due to such bowing, voids are generated inside the contact hole when the metal film (eg, tungsten or aluminum film) is embedded in the contact hole, thereby adversely affecting device characteristics. Voids, such as voids, lead to poor device phenomena, leading to a reduction in manufacturing yield and device characteristics.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 소자가 고집적화되면서 깊은 콘택홀 식각시 발생하는 보잉을 제거하여 후속 공정에서 매립되는 물질막의 보이드를 방지하면서, 기설정된 폭보다 넓은 폭을 가지는 콘택홀을 구현하는데 적합한 반도체 소자의 콘택홀 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above-described problems of the prior art, while the device is highly integrated, thereby eliminating the bowing generated during deep contact hole etching to prevent voiding of the material film embedded in the subsequent process, while wider than the predetermined width. It is an object of the present invention to provide a method for manufacturing a contact hole of a semiconductor device suitable for implementing a contact hole having a.

상기 목적을 달성하기 위한 특징적인 본 발명의 반도체 소자의 콘택홀 제조 방법은 기판 상부에 절연막을 형성하는 단계; 상기 절연막 상에 제1비정질 카본층과 제2비정질 카본층을 형성하되, 상기 제1비정질 카본층은 상기 제2비정질 카본층 에 비해 상대적으로 낮은 온도 분위기에서 형성하는 단계; 상기 제2 및 제1비정질 카본층을 선택적으로 식각하는 단계; 및 상기 절연막을 식각하여 콘택홀을 형성하는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of manufacturing a contact hole in a semiconductor device, the method including: forming an insulating film on a substrate; Forming a first amorphous carbon layer and a second amorphous carbon layer on the insulating layer, wherein the first amorphous carbon layer is formed in a relatively low temperature atmosphere compared to the second amorphous carbon layer; Selectively etching the second and first amorphous carbon layers; And forming a contact hole by etching the insulating film.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2f는 본 발명의 일실시예에 따른 반도체 소자의 콘택홀 제조 방법을 도시한 단면도이다. 2A through 2F are cross-sectional views illustrating a method of manufacturing a contact hole in a semiconductor device according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, DRAM 구성에 필요한 소정의 구조가 형성된 기판(21) 상에 절연막(Dielectric layer, 22)을 형성한다. 이어서 서로 다른 온도 분위기에서 하드마스크로 사용될 제1비정질 카본층(23)과 제2비정질 카본층(24)을 차례로 형성한다. 이 때, 제1비정질 카본층(23)은 250∼350℃에서, 제2비정질 카본층(24)은 450∼550℃ 온도 분위기에서 형성한다. 제1비정질 카본층(23)과 제2비정질 카본층(24)의 두께의 합은 6000∼7000Å을 가지며, 통상 제1비정질 카본층(23)과 제2비정질 카본층(24)은 동일한 두께로 형성한다.As shown in FIG. 2A, an insulating layer 22 is formed on the substrate 21 on which a predetermined structure necessary for DRAM construction is formed. Subsequently, the first amorphous carbon layer 23 and the second amorphous carbon layer 24 to be used as hard masks in different temperature atmospheres are sequentially formed. At this time, the first amorphous carbon layer 23 is formed at 250 to 350 ° C, and the second amorphous carbon layer 24 is formed at a temperature of 450 to 550 ° C. The sum of the thicknesses of the first amorphous carbon layer 23 and the second amorphous carbon layer 24 has a thickness of 6000 to 7000 GPa, and the first amorphous carbon layer 23 and the second amorphous carbon layer 24 have the same thickness. Form.

한편, 제1비정질 카본층(23)은 제2비정질 카본층(24)에 비해 상대적으로 낮은 온도 분위기에서 형성되었으므로 제2비절질 카본층(24)에 비해 카본 함유량 적으므로 폴리머(polymer) 발생이 적고, 가교 결합(Crosslinking)이 약해 측면 식각(Lateral etch)이 잘되는 특성을 갖는다. On the other hand, since the first amorphous carbon layer 23 is formed in a relatively low temperature atmosphere compared to the second amorphous carbon layer 24, since the carbon content is smaller than that of the second amorphous carbon layer 24, polymer generation occurs. It has a low crosslinking property, and has good latent etching.

반면, 제2비정질 카본층(24)은 제1비정질 카본층(23)에 비해 상대적으로 높은 온도에서 형성되었으므로, 제1비정질 카본층(23)에 비해 카본 함유량이 높아 폴리머가 많이 발생되는 특성이 있다.On the other hand, since the second amorphous carbon layer 24 is formed at a relatively high temperature than the first amorphous carbon layer 23, the carbon content is higher than that of the first amorphous carbon layer 23, so that a lot of polymers are generated. have.

이어서, 제2비정질 카본층(24) 상에 SiON막(25)과 반사방지막(26)을 차례로 증착한다. 그리고 나서, 반사방지막(26)의 소정 영역 상에 포토레지스트 패턴(27)을 형성한다.Subsequently, the SiON film 25 and the antireflection film 26 are sequentially deposited on the second amorphous carbon layer 24. Then, the photoresist pattern 27 is formed on the predetermined region of the antireflection film 26.

도 2b에 도시된 바와 같이, 포토레지스트 패턴(27)을 식각 베리어로 반사방지막(26), SiON막(25)을 식각한 후 포토레지스트 패턴(27), 식각된 반사방지막(26) 및 식각된 SiON막(25)을 식각 베리어로 및 제2비정질 카본층(24)을 식각한다. 제2비정질 카본층(24)은 O2 또는 N2 플라즈마를 이용하여 건식 식각한다. 이하. 식각된 제2비정질 카본층(24)은 제2비정질카본하드마스크(24A)라고 한다. 제2비정질카본하드마스크(24A)에 의해 후속 공정에서 형성될 제1콘택홀의 선폭(CD1)이 정의된다.As shown in FIG. 2B, the anti-reflection film 26 and the SiON film 25 are etched using the photoresist pattern 27 as an etch barrier, and then the photoresist pattern 27, the etched anti-reflection film 26 and the etched layer are etched. The SiON film 25 is used as an etching barrier and the second amorphous carbon layer 24 is etched. The second amorphous carbon layer 24 is dry etched using O 2 or N 2 plasma. Below. The etched second amorphous carbon layer 24 is referred to as a second amorphous carbon hard mask 24A. The line width CD1 of the first contact hole to be formed in a subsequent process is defined by the second amorphous carbon hard mask 24A.

도 2c에 도시된 바와 같이, 제2비정질카본하드마스크(24A)를 형성한 후 잔류하는 포토레지스트 패턴을 스트립(Strip)한다.As shown in FIG. 2C, the remaining photoresist pattern is stripped after forming the second amorphous carbon hard mask 24A.

계속해서, 반사방지막(26), SiON막(25) 및 제2비정질카본하드마스크(24A)를 식각 베리어로 제1비정질 카본층(23)을 식각한다. 제1비정질 카본층(23)은 O2 또는 N2 플라즈마를 이용하여 건식 식각하는데, 제1비정질 카본층(23)은 제2비정질 카본층(24)에 비해 가교 결합(Crosslinking)이 약하고 측면 식각이 잘되는 특성이 있다. 따라서, 제1비정질 카본층(23)은 수직 방향에 비해 측면 방향으로 과도 식각되 므로, 제1비정질 카본층(23) 식각 공정 후 제2비정질카본하드마스크(24A)에 의해 정의된 선폭(CD1)보다 넓은 선폭(CD2)을 정의하게 된다. 넓은 선폭(CD2)은 제1비정질카본하드마스크(23A)에 의해 후속 공정에서 형성될 제2콘택홀의 선폭(CD2)을 말한다. 이하, 식각된 제1비정질 카본층을 제1비정질카본하드마스크(23A)라고 한다.Subsequently, the first amorphous carbon layer 23 is etched using the antireflection film 26, the SiON film 25, and the second amorphous carbon hard mask 24A as an etching barrier. The first amorphous carbon layer 23 is dry etched using O 2 or N 2 plasma. The first amorphous carbon layer 23 has a weaker crosslinking and side etching than the second amorphous carbon layer 24. This is a good thing. Therefore, since the first amorphous carbon layer 23 is excessively etched laterally than the vertical direction, the line width CD1 defined by the second amorphous carbon hard mask 24A after the etching process of the first amorphous carbon layer 23 is performed. We will define a wider line width (CD2) than. The wide line width CD2 refers to the line width CD2 of the second contact hole to be formed in a subsequent process by the first amorphous carbon hard mask 23A. Hereinafter, the etched first amorphous carbon layer is referred to as a first amorphous carbon hard mask 23A.

도 2d에 도시된 바와 같이, 제1비정질카본하드마스크(23A) 식각시, 제2비정질카본하드마스크(24A) 상부의 SiON막(25) 및 반사방지막(26)은 모두 식각된다.As illustrated in FIG. 2D, when the first amorphous carbon hard mask 23A is etched, both the SiON film 25 and the anti-reflection film 26 on the second amorphous carbon hard mask 24A are etched.

계속해서, 제2비정질카본하드마스크(24A)를 식각 베리어로 층간절연막(22)을 식각하여 기판(21)의 소정 영역을 오픈하는 제1콘택홀(28)을 형성한다. 제1콘택홀(28)은 제2비정질카본하드마스크(24A)에 의해 정의된 선폭(CD1)을 가지며, 제1콘택홀(28)의 상부에는 보잉(A)이 발생하게 된다. Subsequently, the interlayer insulating film 22 is etched using the second amorphous carbon hard mask 24A as an etch barrier to form a first contact hole 28 that opens a predetermined region of the substrate 21. The first contact hole 28 has a line width CD1 defined by the second amorphous carbon hard mask 24A, and a boeing A is generated on the first contact hole 28.

도 2e에 도시된 바와 같이, 제1콘택홀(28) 식각시 제2비정질카본하드마스크(24A)는 모두 식각된다. 계속해서, 제1비정질카본하드마스크(23A)를 식각 베리어로 층간절연막(22)을 식각하여 도 2d의 단계에서 형성된 제1콘택홀(28) 보다 선폭(CD1→CD2)이 증가된 제2콘택홀(28A)을 형성한다. 이 때, 제1비정질카본하드마스크(23A)에 의해 정의된 선폭(CD2)은 제2비정질카본하드마스크(24A)에 의해 정의된 선폭(CD1)보다 더 크면서, 보잉을 제거할 수 있을 만큼의 선폭(CD2)을 가지므로 보잉을 제거하면서, 제1콘택홀(28) 보다 선폭이 큰 제2콘택홀(28A)을 형성할 수 있다. 따라서, 소자의 문제점이 되었던 보잉을 방지하면서 콘택홀의 선폭을 넓힐 수 있으므로 후속 공정에서 매립되는 금속막의 매립 특성을 개선할 수 있다.As illustrated in FIG. 2E, the second amorphous carbon hard mask 24A is etched when the first contact hole 28 is etched. Subsequently, the second contact having the line width CD1? CD2 increased by etching the interlayer insulating layer 22 using the first amorphous carbon hard mask 23A as an etch barrier to increase the width of the first contact hole 28 formed in the step of FIG. 2D. The hole 28A is formed. At this time, the line width CD2 defined by the first amorphous carbon hard mask 23A is larger than the line width CD1 defined by the second amorphous carbon hard mask 24A, so as to remove the boeing. The second contact hole 28A having a line width larger than the first contact hole 28 can be formed while having the line width CD2. Therefore, the line width of the contact hole can be widened while preventing the bowing, which is a problem of the device, and thus the embedding property of the metal film embedded in the subsequent process can be improved.

도 2f에 도시된 바와 같이, 제2콘택홀(28A) 식각시 대부분의 제1비정질카본 하드마스크(23A)는 모두 식각 손실되고 잔류하는 제1비정질카본하드마스크는 스트립 공정을 이용하여 제거한다. 이와 같은 공정을 통해, 상부에 보잉이 없으면서 기설정된 선폭보다 증가된 선폭(CD2)을 갖는 제2콘택홀(28A)을 형성할 수 있다.As shown in FIG. 2F, most of the first amorphous carbon hard mask 23A is etched away during the etching of the second contact hole 28A, and the remaining first amorphous carbon hard mask is removed using a strip process. Through this process, the second contact hole 28A having the line width CD2 increased from the predetermined line width without boeing on the top can be formed.

상술한 바와 같이, 서로 다른 온도 분위기에서 비정질 카본층을 적층하여 하드마스크로 사용하므로서, 콘택홀 상부의 보잉을 제거할 수 있을 뿐만 아니라 보잉을 제거하였으므로 후속 공정에서 금속막 증착시 콘택홀 내부의 보이드도 방지할 수 있다.As described above, by stacking the amorphous carbon layers in different temperature atmospheres and using them as hard masks, not only the bowing on the upper portion of the contact hole can be removed but also the bowing is removed, so that the voids in the contact hole during the deposition of the metal film in the subsequent process are removed. Can also be prevented.

본 발명은 깊은 콘택홀 제조 공정에 관련된 모든 공정에 적용 가능하다.The present invention is applicable to all processes related to the deep contact hole manufacturing process.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 서로 다른 온도 분위기에서 형성한 비정질 카본층을 적층하여 하드마스크로 사용하므로서, 콘택홀 상부의 보잉을 제거하면서 콘택홀의 선폭을 증가시킬 수 있는 효과가 있다.The present invention described above has the effect of increasing the line width of the contact hole while removing the bowing on the upper part of the contact hole by stacking the amorphous carbon layers formed in different temperature atmospheres as a hard mask.

또한, 보잉을 제거하였으므로 콘택홀 형성 후 매립하는 금속막의 보이드 현 상도 방지할 수 있으므로, 금속막의 매립 특성을 향상시킬 수 있는 효과가 있다.In addition, since voiding is removed, void development of the metal film to be buried after the formation of the contact hole can be prevented, thereby improving the embedding characteristics of the metal film.

Claims (5)

기판 상부에 절연막을 형성하는 단계;Forming an insulating film on the substrate; 상기 절연막 상에 제1비정질 카본층과 제2비정질 카본층을 형성하되, 상기 제1비정질 카본층은 상기 제2비정질 카본층에 비해 상대적으로 낮은 온도 분위기에서 형성하는 단계;Forming a first amorphous carbon layer and a second amorphous carbon layer on the insulating layer, wherein the first amorphous carbon layer is formed in a relatively low temperature atmosphere compared to the second amorphous carbon layer; 상기 제2 및 제1비정질 카본층을 선택적으로 식각하는 단계; 및Selectively etching the second and first amorphous carbon layers; And 상기 절연막을 식각하여 콘택홀을 형성하는 단계Etching the insulating layer to form a contact hole 를 포함하는 반도체 소자의 콘택홀 제조 방법.Contact hole manufacturing method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제2 및 제1비정질 카본층을 선택적으로 식각하는 단계에서,In the step of selectively etching the second and first amorphous carbon layer, 상기 제1비정질 카본층은 상기 제2비정질 카본층보다 상대적으로 넓은 선폭으로 식각되는 반도체 소자의 콘택홀 제조 방법.The method of claim 1, wherein the first amorphous carbon layer is etched with a line width relatively wider than that of the second amorphous carbon layer. 제2항에 있어서,The method of claim 2, 상기 제1비정질 카본층은 250∼350℃, 상기 제2비정질 카본층은 450∼550℃ 온도에서 형성하는 반도체 소자의 콘택홀 제조 방법.The method of claim 1, wherein the first amorphous carbon layer is formed at a temperature of 250 to 350 ° C., and the second amorphous carbon layer is formed at a temperature of 450 to 550 ° C. 6. 제1항에 있어서,The method of claim 1, 상기 제2 및 제1비정질 카본층을 선택적으로 식각하는 단계에서,In the step of selectively etching the second and first amorphous carbon layer, 상기 제2비정질 카본층 상에 SiON막을 형성하는 단계;Forming a SiON film on the second amorphous carbon layer; 상기 SiON막 상에 포토레지스트 패턴을 형성하는 단계; 및Forming a photoresist pattern on the SiON film; And 상기 SiON막과 상기 제2 및 제1비정질 카본층을 식각하는 단계를 포함하는 반도체 소자의 콘택홀 제조 방법.And etching the SiON film and the second and first amorphous carbon layers. 제1항에 있어서,The method of claim 1, 상기 제1비정질 카본층과 상기 제2비정질 카본층의 식각은,Etching of the first amorphous carbon layer and the second amorphous carbon layer, N2 또는 O2 플라즈마를 사용하는 반도체 소자의 콘택홀 제조 방법.Method for manufacturing a contact hole in a semiconductor device using N 2 or O 2 plasma.
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KR20050019905A (en) 2002-07-31 2005-03-03 어드밴스드 마이크로 디바이시즈, 인코포레이티드 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
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