KR20030002110A - Method for forming self aligned contact plug - Google Patents
Method for forming self aligned contact plug Download PDFInfo
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- KR20030002110A KR20030002110A KR1020010038851A KR20010038851A KR20030002110A KR 20030002110 A KR20030002110 A KR 20030002110A KR 1020010038851 A KR1020010038851 A KR 1020010038851A KR 20010038851 A KR20010038851 A KR 20010038851A KR 20030002110 A KR20030002110 A KR 20030002110A
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- interlayer insulating
- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000011229 interlayer Substances 0.000 claims abstract description 74
- 239000010410 layer Substances 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims description 41
- 239000007789 gas Substances 0.000 claims description 30
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 17
- 229910052799 carbon Inorganic materials 0.000 claims description 17
- 150000004767 nitrides Chemical group 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 28
- 229920005591 polysilicon Polymers 0.000 description 28
- 239000003990 capacitor Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로서, 특히 고집적 반도체소자의 자기정렬 콘택 플러그의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a self-aligned contact plug of a highly integrated semiconductor device.
최근의 반도체소자는 소자의 집적도가 증가함에 따라 메모리 셀 크기가 점점 감소되면서 워드라인과 캐패시터 콘택, 비트라인과 캐패시터 콘택의 마진이 점점 작아져 캐패시터 콘택을 더욱 작게 형성해야만 한다.In recent years, as the integration of devices increases, the size of memory cells decreases gradually, so that margins of word lines and capacitor contacts, bit lines and capacitor contacts become smaller, and thus capacitor capacitors must be made smaller.
또한, 반도체 집적회로가 고집적화됨에 따라 다수의 배선층 또는 콘택홀 사이의 미스얼라인 마진(mis-align margin)이 점점 줄어들고 있다. 더욱이, 반도체 메모리셀과 같이 디자인 룰(design rule)에 여유가 없고 같은 형태의 패턴이 반복되는 경우, 콘택홀을 자기정렬(self-align) 방식으로 형성함으로써 메모리셀의 면적을 축소시키는 방법이 연구/개발되었다. 이는 주변구조물의 단차를 이용하여 콘택홀을 형성하는 것으로, 주변구조물의 높이, 콘택홀이 형성될 절연물질의 두께 및식각방법 등에 의해 다양한 크기의 콘택홀을 마스크 사용없이 얻을 수 있기 때문에 고집적화에 의해 미세화되는 반도체소자의 구현에 적합한 방법으로 사용된다.In addition, as semiconductor integrated circuits become highly integrated, mis-align margins between a plurality of wiring layers or contact holes are gradually decreasing. Furthermore, in the case where there is no room in a design rule like a semiconductor memory cell and a pattern of the same pattern is repeated, a method of reducing the area of the memory cell by forming a contact hole in a self-aligned manner is studied. / Developed. This is to form a contact hole by using the step of the peripheral structure, the contact hole of various sizes can be obtained without using a mask by the height of the peripheral structure, the thickness of the insulating material to be formed and the etching method, etc. It is used in a method suitable for the implementation of the semiconductor device to be miniaturized.
도 1a 내지 도 1d는 종래기술에 따른 자기정렬 콘택 플러그의 형성 방법을 도시한 도면이다.1A to 1D illustrate a method of forming a self-aligned contact plug according to the prior art.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 워드라인(도시 생략)을 형성하고, 반도체기판(11)내에 소스/드레인(12)을 형성하여 트랜지스터를 형성한 후,반도체기판(11)의 전면에 제 1 층간절연막(13)을 증착한다.As shown in FIG. 1A, after forming a word line (not shown) on the semiconductor substrate 11, forming a source / drain 12 in the semiconductor substrate 11, and forming a transistor, the semiconductor substrate 11 is formed. The first interlayer insulating film 13 is deposited on the entire surface of the substrate.
계속해서, 제 1 콘택마스크(도시 생략)를 이용하여 제 1 층간절연막(13)을 식각하여 소스/드레인(12)의 표면이 노출되는 콘택홀을 형성한 후, 콘택홀을 포함한 전면에 폴리실리콘을 증착한다. 그리고, 폴리실리콘을 에치백하거나 화학적기계적연마하여 콘택홀에 매립되는 제 1 폴리실리콘플러그(14)를 형성한다.Subsequently, the first interlayer insulating film 13 is etched using a first contact mask (not shown) to form a contact hole through which the surface of the source / drain 12 is exposed, and then polysilicon on the entire surface including the contact hole. Deposit. Then, the polysilicon is etched back or chemical mechanically polished to form a first polysilicon plug 14 embedded in the contact hole.
이어서 제 1 폴리실리콘플러그(14)를 포함한 전면에 제 2 층간절연막(15)을 증착한 후, 제 2 층간절연막(15)상에 비트라인 도전막, 하드마스크(hard mask)를 순차적으로 적층한다. 그리고, 하드마스크상에 감광막을 도포하고 포토리소그래피 공정을 통해 비트라인마스크(도시 생략)를 형성한 후, 비트라인마스크를 이용한 건식식각으로 하드마스크(17)를 갖는 비트라인(16)을 형성한다.Subsequently, a second interlayer insulating film 15 is deposited on the entire surface including the first polysilicon plug 14, and then a bit line conductive film and a hard mask are sequentially stacked on the second interlayer insulating film 15. . After the photoresist is coated on the hard mask and a bit line mask (not shown) is formed through a photolithography process, the bit line 16 having the hard mask 17 is formed by dry etching using the bit line mask. .
계속해서, 비트라인(16)을 포함한 전면에 스페이서용 절연막, 통상적으로 질화막을 증착한 후, 전면식각하여 비트라인(16)의 측벽에 접하는 스페이서(18)를 형성한다.Subsequently, an insulating film for a spacer, typically a nitride film, is deposited on the entire surface including the bit line 16 and then etched to form a spacer 18 in contact with the sidewall of the bit line 16.
도 1b에 도시된 바와 같이, 하드마스크(17)를 갖는 비트라인(16)을 포함한 전면에 제 3 층간절연막(19)을 증착한 후, 제 3 층간절연막(19)상에 감광막을 도포하고다. 제 3 층간절연막(19)상에 감광막을 도포하고 포토리소그래피 공정을 통해 홀형(Hole type), 라인형(Line type), 티형(T-type) 또는 아이형(I-type) 중에서 선택된 제 2 콘택마스크(20)를 형성한다.As shown in FIG. 1B, after the third interlayer insulating film 19 is deposited on the entire surface including the bit line 16 having the hard mask 17, a photosensitive film is coated on the third interlayer insulating film 19. . A second contact selected from a hole type, a line type, a T-type, or an I-type by applying a photoresist film on the third interlayer insulating film 19 and performing a photolithography process The mask 20 is formed.
도 1c에 도시된 바와 같이, 제 2 콘택마스크(20)를 이용한 자기정렬콘택식각(SAC)으로 비트라인(16) 사이의 제 3 층간절연막(19)을 식각하고,연속해서 제 2 층간절연막(15)을 식각하여 제 1 폴리실리콘플러그(14)의 표면을 노출시키는 콘택홀(21)을 형성한다. 여기서, 콘택홀(11)은 후속 제 2 폴리실리콘플러그(22)와 제 1 폴리실리콘플러그(14)간의 접속통로이다.As shown in FIG. 1C, the third interlayer dielectric layer 19 between the bit lines 16 is etched using a self-aligned contact etching (SAC) using the second contact mask 20, and subsequently, the second interlayer dielectric layer ( 15 is etched to form a contact hole 21 exposing the surface of the first polysilicon plug 14. Here, the contact hole 11 is a connection path between the subsequent second polysilicon plug 22 and the first polysilicon plug 14.
도 1d에 도시된 바와 같이, 제 2 콘택마스크(20)를 제거하고, 콘택홀(21)이 형성된 제 3 층간절연막(19)상에 폴리실리콘을 증착한 후, 폴리실리콘을 화학적기계적연마하거나, 에치백하여 제 1 폴리실리콘플러그(14)에 접속되는 제 2 폴리실리콘플러그(22)를 형성한다.As shown in FIG. 1D, after the second contact mask 20 is removed and polysilicon is deposited on the third interlayer insulating layer 19 on which the contact holes 21 are formed, the polysilicon is chemically mechanically polished, or It is etched back to form a second polysilicon plug 22 connected to the first polysilicon plug 14.
그러나, 상술한 종래기술은 제 3 층간절연막(19)의 증착 과정에서 비트라인(16) 사이를 채우지 못하여 보이드('A')가 형성되거나(도 2a 참조), 자기정렬식각 과정에서 측면 식각방지막이 어택('B')을 받아서 도선이 드러나게 되면(도 2b 참조), 전기적 페일의 원인이 된다.However, in the above-described conventional technology, voids 'A' are formed due to the gap between bit lines 16 in the deposition process of the third interlayer insulating layer 19 (see FIG. 2A), or the side etch barrier layer in the self-aligned etching process. When the wire is exposed by the attack 'B' (see FIG. 2B), it causes electric failure.
일반적으로 층간절연막으로 이용되는 산화막은 좁고 깊은 간격을 채우는 과정에서 간격을 채우지 못하여 보이드가 발생하게 된다. 이를 해결하기 위해 패턴의 측벽에 스페이서(또는 측면식각방지막)을 형성하고 있으나, 간격의 깊이는 그대로유지하지만, 간격이 좁아지는 효과가 발생하여 층간절연막 증착과정에서 보이드가 발생할 가능성이 높아지고, 이러한 보이드는 이후의 식각 공정에서 문제를 일으키거나 전기적 오동작의 원인이 된다.In general, an oxide film used as an interlayer insulating film does not fill a gap in the process of filling a narrow and deep gap, thereby causing voids. In order to solve this problem, spacers (or side etch barriers) are formed on the sidewalls of the pattern, but the depth of the gap is maintained as it is, but the gap is narrowed, so that voids are more likely to occur during the deposition of the interlayer insulating film. May cause problems or cause electrical malfunction in subsequent etching processes.
한편, 자기정렬 식각 과정에서 스페이서가 어택을 받아서 패턴이 드러나게 되는 문제를 해결하기 위해서 스페이서의 두께를 증가시키는 방법이 제안되었으나, 이러한 방법은 전술한 바와 같이 층간절연막의 증착 과정에서 보이드를 발생시킬가능성을 증가시키므로 적용하기 어렵다.On the other hand, in order to solve the problem that the spacer is attacked and the pattern is revealed in the self-aligned etching process, a method of increasing the thickness of the spacer has been proposed, but as described above, it is possible to generate voids in the deposition process of the interlayer dielectric film. It is difficult to apply because it increases.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 측간절연막 증착과정에서의 보이드 및 식각과정에서의 스페이서 어택에 의한 전기적 불 량을 방지하는데 적합한 자기정렬콘택 플러그의 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and provides a method of forming a self-aligned contact plug suitable for preventing electrical failure due to void attack in the side-side insulating film deposition process and spacer attack during the etching process. The purpose is.
도 1a 내지 도 1d는 종래기술에에 따른 자기정렬 콘택 플러그의 형성 방법을 도시한 공정 단면도,1A to 1D are cross-sectional views illustrating a method of forming a self-aligned contact plug according to the prior art;
도 2a 및 도 2b는 종래기술에 따른 문제점을 도시한 도면,2A and 2B illustrate a problem according to the prior art,
도 3a 내지 도 3d는 본 발명의 실시예에 따른 자기정렬 콘택 플러그의 형성 방법을 도시한 공정 단면도.3A through 3D are cross-sectional views illustrating a method of forming a self-aligned contact plug according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 소스/드레인31: semiconductor substrate 32: source / drain
33 : 제 1 층간절연막 34 : 제 1 폴리실리콘 플러그33: first interlayer insulating film 34: first polysilicon plug
35 : 제 2 층간절연막 36 : 비트라인35 second interlayer insulating film 36 bit line
37 : 하드마스크 38 : 제 3 층간절연막37: hard mask 38: third interlayer insulating film
39 : 제 2 콘택마스크 40 : 스페이서39: second contact mask 40: spacer
41 : 콘택홀 42 : 제 2 폴리실리콘 플러그41: contact hole 42: second polysilicon plug
상기의 목적을 달성하기 위한 본 발명의 자기정렬콘택 플러그의 형성 방법은 반도체기판상에 하드마스크를 구비한 다수의 도전층 패턴을 형성하는 단계, 상기 도전층 패턴을 포함한 상기 반도체기판상에 층간절연막을 형성하는 단계, 상기 층간절연막상에 콘택마스크를 형성하는 단계, 상기 콘택마스크를 이용하여 상기 도전층패턴의 상측 표면까지 상기 층간절연막을 부분 식각하는 단계, 및 상기 부분 식각된 층간절연막을 자기정렬식각하여 상기 도전층패턴의 측벽에 스페이서를 형성시키면서 상기 반도체기판을 노출시키는 콘택홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 하며, 상기 콘택홀을 형성하는 단계는, 카본함량이 높은 가스를 포함하는 가스 조합으로 이루어지되, 상기 카본함량이 높은 가스의 분압이 높은 식각조건으로 이루어짐을 특징으로 하고, 상기 상기 층간절연막을 부분 식각하는 단계는, 카본함량이 높은 가스를 포함하는 가스 조합으로 이루어지되, 상기 카본함량이높은 가스의 분압이 낮은 식각 조건으로 이루어짐을 특징으로 한다.In order to achieve the above object, a method of forming a self-aligned contact plug according to an embodiment of the present invention includes forming a plurality of conductive layer patterns having a hard mask on a semiconductor substrate, and forming an interlayer insulating layer on the semiconductor substrate including the conductive layer patterns. Forming a contact mask on the interlayer insulating film, partially etching the interlayer insulating film to an upper surface of the conductive layer pattern using the contact mask, and self-aligning the partially etched interlayer insulating film And etching to form contact holes for exposing the semiconductor substrate while forming spacers on sidewalls of the conductive layer pattern, wherein forming the contact holes includes a gas having a high carbon content. Composed of a gas combination, the partial pressure of the gas with a high carbon content is achieved in a high etching condition Step of luggage, characterized, and etching the interlayer insulating the part is made of a carbon content jidoe gas combination including a high gas, characterized in that the carbon content of the high partial pressure of a gas constituted by any low etching conditions.
또한 본 발명의 자기정렬 콘택 플러그의 형성 방법은 반도체기판상에 제 1 플러그를 형성하는 단계, 상기 제 1 플러그상에 제 1 층간절연막을 형성하는 단계, 상기 제 1 층간절연막상에 복수의 비트라인패턴을 형성하는 단계, 상기 비트라인패턴상에 제 2 층간절연막을 형성하는 단계, 상기 제 2 층간절연막상에 콘택마스크를 형성하는 단계, 상기 콘택마스크를 이용하여 상기 비트라인패턴의 상측 표면까지 상기 제 2 층간절연막을 부분 식각하는 단계, 및 상기 부분 식각된 제 2 층간절연막을 자기정렬식각하여 상기 비트라인패턴의 측벽에 스페이서를 형성시키는 단계, 및 상기 제 2 층간절연막 식각으로 노출된 상기 제 1 층간절연막을 식각하여 상기 제 1 플러그를 노출시키는 콘택홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In addition, the method of forming a self-aligned contact plug according to the present invention includes forming a first plug on a semiconductor substrate, forming a first interlayer insulating film on the first plug, and a plurality of bit lines on the first interlayer insulating film. Forming a pattern, forming a second interlayer insulating film on the bit line pattern, forming a contact mask on the second interlayer insulating film, and using the contact mask to the upper surface of the bit line pattern. Partially etching the second interlayer dielectric layer; and self-aligning the partially etched second interlayer dielectric layer to form spacers on sidewalls of the bit line pattern; and the first exposed by the second interlayer dielectric layer etch. And etching the interlayer insulating layer to form a contact hole exposing the first plug.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3d는 본 발명의 실시예에 따른 자기정렬 콘택식각 방법을 도시한 도면으로서, 비트라인과 교차하는 방향에 대한 공정 단면도이다.3A to 3D are diagrams illustrating a self-aligned contact etching method according to an exemplary embodiment of the present invention, which is a cross-sectional view of a process line crossing a bit line.
도 3a에 도시된 바와 같이, 반도체기판(31)상에 워드라인(도시 생략)을 형성하고, 반도체기판(31)내에 소스/드레인(32)을 형성하여 트랜지스터를 형성한 후, 반도체기판(31)의 전면에 제 1 층간절연막(33)을 증착한다.As shown in FIG. 3A, after forming a word line (not shown) on the semiconductor substrate 31, forming a source / drain 32 in the semiconductor substrate 31, and forming a transistor, the semiconductor substrate 31 is formed. The first interlayer insulating film 33 is deposited on the entire surface of the substrate.
계속해서, 제 1 콘택마스크를 이용하여 제 1 층간절연막(33)을 식각하여 소스/드레인(32)의 표면이 노출되는 콘택홀을 형성한 후, 콘택홀을 포함한 전면에 폴리실리콘을 증착한다. 그리고, 폴리실리콘을 에치백하거나 화학적기계적연마하여 콘택홀에 매립되는 제 1 폴리실리콘플러그(34)를 형성한다.Subsequently, the first interlayer insulating layer 33 is etched using the first contact mask to form a contact hole through which the surface of the source / drain 32 is exposed, and then polysilicon is deposited on the entire surface including the contact hole. Then, the polysilicon is etched back or chemical mechanically polished to form a first polysilicon plug 34 embedded in the contact hole.
이어서 제 1 폴리실리콘플러그(34)를 포함한 전면에 제 2 층간절연막(35)을 증착한 후, 제 2 층간절연막(35)상에 비트라인 도전막, 하드마스크(hard mask)를 순차적으로 적층한다. 그리고, 하드마스크상에 감광막을 도포하고 포토리소그래피 공정을 통해 비트라인마스크(도시 생략)를 형성한 후, 비트라인마스크를 이용한 건식식각으로 하드마스크(37)를 갖는 비트라인(36)을 형성한다.Subsequently, a second interlayer insulating film 35 is deposited on the entire surface including the first polysilicon plug 34, and then a bit line conductive film and a hard mask are sequentially stacked on the second interlayer insulating film 35. . Then, after applying a photoresist film on the hard mask and forming a bit line mask (not shown) through a photolithography process, the bit line 36 having the hard mask 37 is formed by dry etching using the bit line mask. .
여기서, 비트라인(36)은 텅스텐, 텅스텐실리사이드, 티타늄실리사이드, 코발트실리사이드, 알루미늄 또는 구리에서 선택된 어느 하나이고, 하드마스크(37)는 후속 제 3 층간절연막(도 3b의 '38')의 식각 과정에서 선택비를 가질 수 있는 모든 막을 이용한다.Here, the bit line 36 is any one selected from tungsten, tungsten silicide, titanium silicide, cobalt silicide, aluminum or copper, and the hard mask 37 is a subsequent etching process of the third interlayer dielectric layer ('38' of FIG. 3B). Use all the membranes that have a selectivity in.
예컨대, 제 3 층간절연막이 산화막계인 경우 SiN, SiON과 같은 질화막계 하드마스크를 이용하며, 제 3 층간절연막이 폴리머성 저유전율막인 경우 산화막계 하드마스크를 이용한다.For example, when the third interlayer insulating film is an oxide film system, a nitride film hard mask such as SiN or SiON is used, and when the third interlayer insulating film is a polymer low dielectric film, an oxide film hard mask is used.
그리고, 하드마스크(37)는 콘택식각시 비트라인(36)의 식각을 방지하고 제 2 폴리실리콘플러그(도 3d의 '42')와 비트라인(36)간의 절연을 고려하여 500Å∼5000Å의 두께로 증착한다.In addition, the hard mask 37 prevents the etching of the bit line 36 during the contact etching, and has a thickness of 500 μs to 5000 μs in consideration of the insulation between the second polysilicon plug ('42' in FIG. 3D) and the bit line 36. To be deposited.
도 3b에 도시된 바와 같이, 하드마스크(37)를 갖는 비트라인(36)을 포함한전면에 제 3 층간절연막(38)을 증착한다. 이 때, 제 3 층간절연막(38)은 전술한 것처럼 산화막계 절연막 또는 폴리머성 저유전율막중에서 선택하고, 하드마스크(37)의 표면을 기준으로 500Å∼10000Å만큼 두껍게 증착한다.As shown in FIG. 3B, a third interlayer insulating film 38 is deposited on the entire surface including the bit line 36 having the hard mask 37. As shown in FIG. At this time, the third interlayer insulating film 38 is selected from an oxide-based insulating film or a polymer low dielectric constant film as described above, and is deposited as thick as 500 kPa to 10000 kPa based on the surface of the hard mask 37.
계속해서, 제 3 층간절연막(38)상에 감광막을 도포하고 포토리소그래피 공정을 통해 홀형(Hole type), 라인형(Line type), 티형(T-type) 또는 아이형(I-type) 중에서 선택된 제 2 콘택마스크(39)를 형성한다.Subsequently, a photosensitive film is coated on the third interlayer insulating film 38 and selected from a hole type, a line type, a T-type, or an I-type through a photolithography process. The second contact mask 39 is formed.
도 3c에 도시된 바와 같이, 제 2 콘택마스크(39)를 이용한 자기정렬콘택식각(SAC)으로 비트라인(36) 사이의 제 3 층간절연막(38)을 식각하여 비트라인(36)의 측벽에 접하는 스페이서(40)를 형성하고, 연속해서 제 2 층간절연막(35)을 식각하여 제 1 폴리실리콘플러그(34)의 표면을 노출시키는 콘택홀(41)을 형성한다. 여기서, 콘택홀(41)은 제 2 폴리실리콘플러그(42)와 제 1 폴리실리콘플러그(34)간의 접속통로이다.As shown in FIG. 3C, the third interlayer dielectric layer 38 between the bit lines 36 is etched using a self-aligned contact etching (SAC) using the second contact mask 39 to form sidewalls of the bit lines 36. The contacting spacers 40 are formed, and the second interlayer insulating film 35 is subsequently etched to form contact holes 41 exposing the surface of the first polysilicon plug 34. Here, the contact hole 41 is a connection path between the second polysilicon plug 42 and the first polysilicon plug 34.
이 때, 자기정렬콘택식각 공정은 고밀도플라즈마(High density plasma; HDP) 또는 중밀도 플라즈마(Middle density plasma; MDP) 식각 반응기를 이용하되, 하드마스크(37)에 대해 선택적으로 제 3 층간절연막(38)을 식각할 수 있는 공정 조건을 사용한다.In this case, the self-aligned contact etching process uses a high density plasma (HDP) or a medium density plasma (MDP) etching reactor, but the third interlayer insulating film 38 selectively with respect to the hard mask 37. Use process conditions to etch).
예컨대, 질화막 계열의 하드마스크와 산화막 계열의 제 3 층간절연막을 사용하는 경우, Ar/C4F8/CH2F2, Ar/C4F8/O2, Ar/C4F8/CH3F, Ar/C4F8/CHF3, Ar/C5F8, Ar/C5F8/O2가스 조합과 이들 가스들의 다른 조합으로 건식각하는 조건을 포함한다.For example, in the case of using a nitride film-based hard mask and an oxide film-based third interlayer insulating film, Ar / C 4 F 8 / CH 2 F 2 , Ar / C 4 F 8 / O 2 , Ar / C 4 F 8 / CH Conditions for dry etching with 3 F, Ar / C 4 F 8 / CHF 3 , Ar / C 5 F 8 , Ar / C 5 F 8 / O 2 gas combinations and other combinations of these gases.
또한, 산화막 계열의 하드마스크와 질화막 계열의 제 3 층간절연막을 사용하는 경우, Ar/O2/N2/H2/CH4/C2H4/CxFy가스의 조합으로 진행하는 조건을 포함한다.In addition, in the case where an oxide-based hard mask and a nitride-based third interlayer insulating film are used, the conditions proceed by a combination of Ar / O 2 / N 2 / H 2 / CH 4 / C 2 H 4 / C x F y gas. It includes.
그리고, 자기정렬콘택식각 공정은 1mtorr∼100mtorr의 압력범위에서 진행하고, 비트라인(36)의 측벽에 제 3 층간절연막(38)으로 이루어진 스페이서(40)가 잔류하도록하기 위해 카본함량이 높은 가스(Carbon-rich gas; 이하 '카본부화가스'라 약칭함), 예컨대, C4F8, C5F6, C4F6의 분압이 높은 식각 조건을 이용한다.In addition, the self-aligned contact etching process is performed in a pressure range of 1 mtorr to 100 mtorr, and a gas having a high carbon content so that the spacer 40 made of the third interlayer insulating film 38 remains on the sidewall of the bit line 36. Carbon-rich gas (hereinafter abbreviated as 'carbon hatched gas'), for example, C 4 F 8 , C 5 F 6 , C 4 F 6 partial pressure etching conditions are used.
그리고, 자기정렬콘택식각 공정은 2단계 또는 3단계 식각을 하는데, 비트라인 주변을 식각하는 단계에서는 카본부화가스의 분압이 높은 조건을 이용하고, 비트라인(36) 상부를 노출시키는 제 3 층간절연막(38)의 식각 단계 또는 비트라인(36) 하부의 제 1 폴리실리콘플러그(34)의 표면을 노출시키는 제 2 층간절연막(35) 식각 단계에서는 제 2 폴리실리콘플러그 또는 제 1 폴리실리콘플러그와의 접촉 면적을 증가시키기 위해 카본부화가스의 분압이 낮은 조건을 이용한다.In the self-aligned contact etching process, a two-stage or three-stage etching process is performed. In the step of etching around the bit line, a third interlayer insulating film exposing the upper portion of the bit line 36 is used under conditions where the partial pressure of carbon enrichment gas is high. In the etching step (38) or the etching step of the second interlayer insulating film 35 exposing the surface of the first polysilicon plug 34 under the bit line 36, the second polysilicon plug or the first polysilicon plug In order to increase the contact area, a condition in which the partial pressure of carbon enrichment gas is low is used.
도 3d에 도시된 바와 같이, 제 2 콘택마스크(39)를 제거하고, 스페이서(40) 및 비트라인(36)을 포함한 전면에 폴리실리콘을 증착한 후, 폴리실리콘을 화학적기계적연마하거나, 에치백하여 제 1 폴리실리콘플러그(34)에 접속되는 제 2 폴리실리콘플러그(42)를 형성한다.As shown in FIG. 3D, after removing the second contact mask 39, depositing polysilicon on the front surface including the spacer 40 and the bitline 36, chemical mechanical polishing or etch back of the polysilicon is performed. To form a second polysilicon plug 42 connected to the first polysilicon plug 34.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 자기정렬콘택식각시 비트라인의 측면에 자연적으로 스페이서를 형성하므로, 층간절연막 증착과정에서의 보이드 및 자기정렬식각시의 스페이서 어택을 억제하여 콘택의 전기적 안정성을 향상시킬 수 있는 효과가 있다.As described above, the present invention naturally forms a spacer on the side of the bit line during the self-aligned contact etching, thereby suppressing the void attack and the spacer attack during the self-aligned etching during the interlayer insulating film deposition process, thereby improving the electrical stability of the contact. It has an effect.
Claims (12)
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| CN111146088A (en) * | 2018-11-06 | 2020-05-12 | 南亚科技股份有限公司 | Method for manufacturing semiconductor structure |
| CN111146088B (en) * | 2018-11-06 | 2022-09-16 | 南亚科技股份有限公司 | Method for manufacturing semiconductor structure |
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