KR100768292B1 - 전자 기판, 전자 기판의 제조 방법 및 전자 기기 - Google Patents
전자 기판, 전자 기판의 제조 방법 및 전자 기기 Download PDFInfo
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- KR100768292B1 KR100768292B1 KR1020060054348A KR20060054348A KR100768292B1 KR 100768292 B1 KR100768292 B1 KR 100768292B1 KR 1020060054348 A KR1020060054348 A KR 1020060054348A KR 20060054348 A KR20060054348 A KR 20060054348A KR 100768292 B1 KR100768292 B1 KR 100768292B1
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Abstract
Description
Claims (12)
- 전자 기판으로서,접속 단자를 갖는 전자 회로가 형성된 기판과,상기 기판 위에 형성된 응력 완화층과,상기 응력 완화층의 표면측에 배치된 상기 접속 단자의 재배치 배선과,상기 기판과 상기 응력 완화층 사이에 배치된 제 1 전극과, 상기 응력 완화층의 상기 표면측에 배치된 제 2 전극과, 상기 제 1 전극과 상기 제 2 전극 사이에 배치된 유전체 재료를 포함하는 커패시터를 구비하는 것을 특징으로 하는 전자 기판.
- 제 1 항에 있어서,상기 응력 완화층은 상기 유전체 재료를 포함하는 것을 특징으로 하는 전자 기판.
- 제 1 항에 있어서,상기 제 1 전극과 상기 제 2 전극 사이에 복수의 상기 응력 완화층이 배치되어 있는 것을 특징으로 하는 전자 기판.
- 제 1 항에 있어서,상기 제 2 전극의 표면에 돌기 전극이 형성되어 있는 것을 특징으로 하는 전자 기판.
- 제 1 항에 있어서,상기 기판과 상기 응력 완화층 사이에 상기 기판의 패시베이션막이 배치되고,상기 제 1 전극은 상기 기판과 상기 패시베이션막 사이에 배치되어 있는 것을 특징으로 하는 전자 기판.
- 제 1 항에 있어서,상기 제 1 전극은 상기 전자 회로의 상기 접속 단자인 것을 특징으로 하는 전자 기판.
- 제 1 항에 있어서,상기 응력 완화층은 유전체 재료에 세라믹 분말을 분산시킨 재료로 이루어지는 것을 특징으로 하는 전자 기판.
- 제 7 항에 있어서,상기 유전체 재료는 감광성을 갖는 수지 재료인 것을 특징으로 하는 전자 기판.
- 전자 기판의 제조 방법으로서,접속 단자를 갖는 전자 회로가 형성된 기판을 형성하는 공정과,상기 기판 위에 유전체 재료로 이루어지는 응력 완화층을 형성하는 공정과,상기 기판과 상기 응력 완화층 사이에 배치되는 제 1 전극을 형성하는 공정과,상기 응력 완화층의 표면측에 배치되는 제 2 전극을 형성하는 공정과,상기 응력 완화층의 상기 표면측에 배치되는, 상기 접속 단자의 재배치 배선을 형성하는 공정을 구비하고,상기 응력 완화층과 상기 제 1 전극과, 상기 제 2 전극이 커패시터를 구성하는 것을 특징으로 하는 전자 기판의 제조 방법.
- 전자 기판의 제조 방법으로서,접속 단자를 갖는 전자 회로가 형성된 기판을 형성하는 공정과,상기 기판 위에 응력 완화층을 형성하는 공정과,상기 기판과 상기 응력 완화층 사이에 배치되는 제 1 전극을 형성하는 공정과,상기 응력 완화층의 표면측에 배치되는 제 2 전극을 형성하는 공정과,상기 제 1 전극과 상기 제 2 전극 사이에 배치되는 유전체 재료를 상기 기판 위에 배치하는 공정과,상기 응력 완화층의 상기 표면측에 배치되는, 상기 접속 단자의 재배치 배선을 형성하는 공정을 구비하고,상기 제 2 전극의 형성과 상기 재배치 배선의 형성이 실질적으로 동시에 행해지는 것을 특징으로 하는 전자 기판의 제조 방법.
- 전자 기판의 제조 방법으로서,접속 단자를 갖는 전자 회로가 형성된 기판을 형성하는 공정과,상기 기판 위에 응력 완화층을 형성하는 공정과,상기 기판과 상기 응력 완화층 사이에 배치되는 제 1 전극을 형성하는 공정과,상기 응력 완화층의 표면측에 배치되는 제 2 전극을 형성하는 공정과,상기 제 1 전극과 상기 제 2 전극 사이에 배치되는 유전체 재료를 상기 기판 위에 배치하는 공정과,상기 응력 완화층의 상기 표면측에 배치되는, 상기 접속 단자의 재배치 배선을 형성하는 공정과,상기 제 2 전극을 트리밍하여, 상기 제 1 전극과 상기 제 2 전극과, 상기 유전체 재료를 포함하는 커패시터의 특성을 조정하는 공정을 구비하는 것을 특징으로 하는 전자 기판의 제조 방법.
- 제 1 항에 기재된 전자 기판을 구비한 것을 특징으로 하는 전자 기기.
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JP2005180400A JP4265575B2 (ja) | 2005-06-21 | 2005-06-21 | 半導体チップおよび電子機器 |
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JP (1) | JP4265575B2 (ko) |
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JP4903123B2 (ja) * | 2007-12-27 | 2012-03-28 | 株式会社フジクラ | 半導体装置の製造方法 |
JP5728171B2 (ja) * | 2009-06-29 | 2015-06-03 | 株式会社半導体エネルギー研究所 | 半導体装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030025712A (ko) | 2001-09-22 | 2003-03-29 | 한국전기연구원 | 집적화 전자기소자용 박막 커패시터 제조 방법 |
JP2003282792A (ja) * | 2002-03-25 | 2003-10-03 | Hitachi Ltd | 半導体装置の製造方法、半導体装置、ならびに半導体モジュール |
KR20040037234A (ko) | 1997-01-17 | 2004-05-04 | 세이코 엡슨 가부시키가이샤 | 반도체 장치, 전자 부품, 이것들의 제조 방법, 회로 기판및 전자 기기 |
JP2004349394A (ja) * | 2003-05-21 | 2004-12-09 | New Japan Radio Co Ltd | 薄膜高誘電体キャパシタの製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02162820A (ja) | 1988-12-15 | 1990-06-22 | Matsushita Electric Ind Co Ltd | 発振回路 |
EP0734059B1 (en) * | 1995-03-24 | 2005-11-09 | Shinko Electric Industries Co., Ltd. | Chip sized semiconductor device and a process for making it |
JP3356921B2 (ja) | 1995-03-24 | 2002-12-16 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
JPH10135270A (ja) * | 1996-10-31 | 1998-05-22 | Casio Comput Co Ltd | 半導体装置及びその製造方法 |
US6097087A (en) * | 1997-10-31 | 2000-08-01 | Micron Technology, Inc. | Semiconductor package including flex circuit, interconnects and dense array external contacts |
JP2000340955A (ja) | 1999-05-26 | 2000-12-08 | Matsushita Electric Ind Co Ltd | 受動部品内蔵複合多層配線基板およびその製造方法 |
JP4479015B2 (ja) | 1999-06-10 | 2010-06-09 | パナソニック株式会社 | コンデンサ内蔵キャリア基板およびその製造方法 |
JP4468528B2 (ja) | 1999-11-26 | 2010-05-26 | イビデン株式会社 | 多層プリント配線板およびその製造方法。 |
EP1198003B1 (en) * | 2000-03-23 | 2013-08-28 | Seiko Epson Corporation | Method of manufacturing a semiconductor device and electronic device |
JP3796099B2 (ja) * | 2000-05-12 | 2006-07-12 | 新光電気工業株式会社 | 半導体装置用インターポーザー、その製造方法および半導体装置 |
US6847066B2 (en) | 2000-08-11 | 2005-01-25 | Oki Electric Industry Co., Ltd. | Semiconductor device |
US6686659B2 (en) * | 2001-02-23 | 2004-02-03 | Intel Corporation | Selectable decoupling capacitors for integrated circuit and methods of use |
JP3850262B2 (ja) | 2001-10-25 | 2006-11-29 | イビデン株式会社 | 半導体チップ |
JP3734039B2 (ja) * | 2004-03-15 | 2006-01-11 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20040037234A (ko) | 1997-01-17 | 2004-05-04 | 세이코 엡슨 가부시키가이샤 | 반도체 장치, 전자 부품, 이것들의 제조 방법, 회로 기판및 전자 기기 |
KR20030025712A (ko) | 2001-09-22 | 2003-03-29 | 한국전기연구원 | 집적화 전자기소자용 박막 커패시터 제조 방법 |
JP2003282792A (ja) * | 2002-03-25 | 2003-10-03 | Hitachi Ltd | 半導体装置の製造方法、半導体装置、ならびに半導体モジュール |
JP2004349394A (ja) * | 2003-05-21 | 2004-12-09 | New Japan Radio Co Ltd | 薄膜高誘電体キャパシタの製造方法 |
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JP2007005350A (ja) | 2007-01-11 |
JP4265575B2 (ja) | 2009-05-20 |
TW200707727A (en) | 2007-02-16 |
KR20060133897A (ko) | 2006-12-27 |
US20060284322A1 (en) | 2006-12-21 |
CN1886027A (zh) | 2006-12-27 |
US7598459B2 (en) | 2009-10-06 |
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