KR100680409B1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR100680409B1
KR100680409B1 KR1020050135219A KR20050135219A KR100680409B1 KR 100680409 B1 KR100680409 B1 KR 100680409B1 KR 1020050135219 A KR1020050135219 A KR 1020050135219A KR 20050135219 A KR20050135219 A KR 20050135219A KR 100680409 B1 KR100680409 B1 KR 100680409B1
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gate
semiconductor device
manufacturing
photoresist pattern
line width
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KR1020050135219A
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Korean (ko)
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구동철
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A method for manufacturing a semiconductor device is provided to prevent the fall-down of a photoresist pattern by forming the photoresist pattern using an improved gate mask structure. A gate oxide layer and a gate material layer are sequentially formed on a semiconductor substrate with an isolation region(115) for defining an active region(100). A photoresist pattern is formed on the gate material layer. The photoresist pattern is defined with a first gate forming portion of the active region and a second gate forming portion of the isolation region. The CD of the first gate forming portion is smaller than that of the second gate forming portion. A plurality of gate patterns are formed on the resultant structure by etching selectively the gate material layer and the gate oxide layer using the photoresist pattern as an etch mask. A spacer is formed at both sidewalls of each gate pattern.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1은 종래기술에 따른 반도체 소자의 제조 방법을 도시한 평면도. 1 is a plan view showing a method for manufacturing a semiconductor device according to the prior art.

도 2는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 평면도. 2 is a plan view showing a method of manufacturing a semiconductor device according to the present invention.

도 3a 및 도 3b는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들. 3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 활성 영역 상의 게이트 선폭보다 소자 분리 영역 상의 게이트 선폭이 넓게 형성된 게이트용 마스크를 이용한 노광 및 현상 공정을 수행하여 감광막 패턴을 형성함으로써 감광막의 쓰러짐(Collapse)을 방지하며, 코어(Core) 및 페리(Peri)부의 게이트를 안정적으로 확보하여 생산량을 향상시키는 기술을 개시한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, wherein the photosensitive film is collapsed by forming a photoresist pattern by performing an exposure and development process using a gate mask having a gate linewidth wider than a gate line width on an active region. The present invention discloses a technology for stably securing a gate of a core and a ferri part to improve production.

최근 DRAM의 생산성이 향상됨에 따라 디자인 룰(Design Rule)이 감소되고 있으며, 디자인 룰이 감소됨에 따라 트랜지스터의 선폭 또한 감소되고 있다. Recently, as the DRAM productivity is improved, design rules are decreasing, and as the design rules are reduced, the line width of the transistor is also decreasing.

이에 따라 포토 공정이 약하게 진행되었을 경우 페리부의 트랜지스터 중에서 최소의 선폭으로 형성되되, 트랜지스터의 길이가 길게 형성된 경우 패터닝에 사용 되는 감광막 쓰러짐(Collapse) 현상이 발생하게 된다. Accordingly, when the photo process is weakly formed, the transistor is formed with the smallest line width among the transistors of the ferry part, but when the length of the transistor is long, the photosensitive film collapse phenomenon, which is used for patterning, occurs.

도 1은 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 평면도이다. 1 is a plan view illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1을 참조하면, 활성 영역(10) 및 소자 분리 영역(15)이 구비된 반도체 기판 상부에 게이트가 형성된 모습을 도시한 평면도로서, 게이트용 마스크를 이용한 노광 및 현상 공정을 수행하여 감광막 패턴을 형성한 후 상기 감광막 패턴을 마스크로 게이트 물질층을 식각하여 게이트를 형성한다. Referring to FIG. 1, a plan view illustrating a gate formed on a semiconductor substrate having an active region 10 and an isolation region 15 is performed. An exposure and development process using a gate mask is performed to form a photoresist pattern. After forming, the gate material layer is etched using the photoresist pattern as a mask to form a gate.

여기서, 게이트용 마스크는 활성 영역과 소자 분리 영역 상의 게이트 선폭이 동일한 라인형인 것이 바람직하다. Here, the gate mask is preferably in the form of a line having the same gate line width on the active region and the device isolation region.

상술한 종래 기술에 따른 반도체 소자의 제조 방법에서, 선폭이 작은 게이트용 마스크를 이용하여 감광막 패턴 형성시 포토 공정이 약하게 진행되는 경우 감광막 패턴의 쓰러짐(Collapse) 현상이 발생하여 소자의 특성이 악화되는 문제점이 있다. In the method of manufacturing a semiconductor device according to the related art described above, when the photo process is weakly formed when the photoresist pattern is formed using a gate mask having a small line width, a collapse phenomenon of the photoresist pattern occurs, thereby deteriorating characteristics of the device. There is a problem.

상기 문제점을 해결하기 위하여, 활성 영역 상의 게이트 선폭보다 소자 분리 영역 상의 게이트 선폭이 넓게 형성된 게이트용 마스크를 이용한 노광 및 현상 공정을 수행하여 감광막 패턴을 형성함으로써 감광막의 쓰러짐(Collapse)을 방지하며, 코어(Core) 및 페리(Peri)부의 게이트를 안정적으로 확보하여 생산량을 향상시키는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다. In order to solve the above problem, a photosensitive film pattern is formed by performing an exposure and development process using a gate mask having a wider gate line width on the device isolation region than a gate line width on the active region, thereby preventing the collapsing of the photosensitive film. It is an object of the present invention to provide a method for manufacturing a semiconductor device that stably secures a gate of a core and a ferri part to improve a yield.

본 발명에 따른 반도체 소자의 제조 방법은 Method for manufacturing a semiconductor device according to the present invention

소자 분리 영역 및 활성 영역이 구비된 반도체 기판 상부에 게이트 산화막 및 게이트 물질층 및 감광막을 형성하는 단계와,Forming a gate oxide layer, a gate material layer, and a photoresist layer on the semiconductor substrate including the device isolation region and the active region;

활성 영역 상부의 선폭보다 상기 소자 분리 영역 상부의 선폭이 넓게 형성된 게이트 마스크를 이용한 노광 및 현상 공정으로 상기 게이트 물질층 상에 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern on the gate material layer by an exposure and development process using a gate mask in which the line width of the upper portion of the device isolation region is wider than the line width of the active region;

상기 감광막 패턴을 마스크로 상기 게이트 물질층 및 게이트 산화막을 식각하여 게이트 패턴을 형성하는 단계와,Etching the gate material layer and the gate oxide layer using the photoresist pattern as a mask to form a gate pattern;

상기 게이트 패턴 측벽에 스페이서를 형성하는 단계Forming a spacer on sidewalls of the gate pattern

를 포함하는 것을 특징으로 한다. Characterized in that it comprises a.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 2는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 평면도이다.2 is a plan view illustrating a method of manufacturing a semiconductor device according to the present invention.

도 2를 참조하면, 활성 영역(100) 및 소자 분리 영역(115)이 구비된 반도체 기판 상부에 게이트(110)가 형성된 모습을 도시한 평면도로서, 소자 분리 영역(115) 상의 게이트의 선폭은 활성 영역(100) 상의 게이트의 선폭에 비해 넓게 형성된 것을 알 수 있다. Referring to FIG. 2, a plan view illustrating a gate 110 formed on a semiconductor substrate having an active region 100 and an isolation region 115, the line width of the gate on the isolation region 115 being active. It can be seen that it is formed wider than the line width of the gate on the region (100).

이때, 활성 영역의 트랜지스터 길이에 영향을 미치지 않도록 'A'와 같이 소자 분리 영역 상의 게이트만 넓은 선폭으로 형성하는 것이 바람직하다. In this case, it is preferable to form only the gate on the device isolation region with a wide line width such as 'A' so as not to affect the transistor length of the active region.

도 3a 및 도 3b는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도로서, 도 3a는 활성 영역으로 상기 도 2의 a - a' 의 절단면을 도시한 것이며, 도 3b는 소자 분리 영역으로 상기 도 2의 b - b' 의 절단면을 도시한 것이다.3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention. FIG. 3A is a cutaway view of a-a 'of FIG. 2 as an active region, and FIG. 3B is a device isolation region. The cut surface of b-b 'of FIG. 2 is shown.

도 3a 및 도 3b를 참조하면, 활성 영역(100) 및 소자 분리 영역(115)이 구비된 반도체 기판 상부에 게이트 산화막(120), 게이트 물질층(130, 140) 및 감광막(미도시)을 형성한다. 3A and 3B, the gate oxide layer 120, the gate material layers 130 and 140, and the photoresist layer (not shown) are formed on the semiconductor substrate including the active region 100 and the device isolation region 115. do.

여기서, 게이트 산화막(120)은 20 내지 500 Å의 두께의 TEOS 산화막 또는 HTO 산화막으로 형성한다. Here, the gate oxide film 120 is formed of a TEOS oxide film or an HTO oxide film having a thickness of 20 to 500 GPa.

또한, 게이트 물질층(130, 140)은 게이트 도전층(130) 및 게이트 하드마스크층(140)으로 형성하며, 게이트 도전층(130)은 폴리실리콘층 및 텅스텐 실리사이드층의 적층구조 또는 티타늄층으로 형성하며, 게이트 하드마스크층(140)은 질화막으로 형성하며, 감광막(미도시)은 10 내지 5000 Å 의 두께로 형성한다. In addition, the gate material layers 130 and 140 may be formed of the gate conductive layer 130 and the gate hard mask layer 140, and the gate conductive layer 130 may be formed of a polysilicon layer and a tungsten silicide layer or a titanium layer. The gate hard mask layer 140 is formed of a nitride film, and the photoresist film (not shown) is formed to have a thickness of 10 to 5000 GPa.

다음에, 게이트용 마스크를 이용한 노광 및 현상 공정을 수행하여 감광막 패턴(미도시)을 형성하되, 상기 게이트용 마스크는 활성 영역 상의 게이트 선폭보다 소자 분리 영역 상의 게이트 선폭이 넓게 형성된 것을 사용하는 것이 바람직하다. Next, a photoresist pattern (not shown) is formed by performing an exposure and development process using a gate mask, but it is preferable to use a gate mask having a wider gate line width on an element isolation region than a gate line width on an active region. Do.

이때, 소자 분리 영역 상의 게이트용 마스크는 0.01 내지 1 μm 의 선폭을 가지는 것이 바람직하다. At this time, the gate mask on the device isolation region preferably has a line width of 0.01 to 1 μm.

여기서, 활성 영역(100) 및 소자 분리 영역(115) 상에 형성된 게이트 'B' 및 'C'를 비교하여 보면, 소자 분리 영역(115) 상에 형성된 게이트인 'C'의 선폭이 활성 영역(100) 상에 형성된 게이트 'B'의 선폭보다 넓게 형성된 것을 알 수 있다. Here, when comparing the gates 'B' and 'C' formed on the active region 100 and the device isolation region 115, the line width of the gate “C” formed on the device isolation region 115 is defined as the active region ( It can be seen that it is formed wider than the line width of the gate 'B' formed on 100).

그 다음에, 게이트 패턴 측벽에 스페이서(150)를 형성하여 게이트를 형성하고, 제 1 층간 절연막을 형성한 후 상기 활성 영역 상부의 제 1 층간 절연막을 식 각하여 비트라인 콘택홀(105)을 형성한 후 비트라인 콘택홀(105)과 접속되는 비트라인(160)을 형성한 후 비트라인(160)을 포함한 전체 표면에 제 2 층간 절연막을 형성한다. Next, a gate is formed by forming a spacer 150 on the sidewall of the gate pattern, a first interlayer insulating layer is formed, and the first interlayer insulating layer on the active region is etched to form a bit line contact hole 105. After forming the bit line 160 to be connected to the bit line contact hole 105, a second interlayer insulating film is formed on the entire surface including the bit line 160.

본 발명에 따른 반도체 소자의 제조 방법은 활성 영역 상의 게이트 선폭보다 소자 분리 영역 상의 게이트 선폭이 넓게 형성된 게이트용 마스크를 이용한 노광 및 현상 공정을 수행하여 감광막 패턴을 형성함으로써 감광막 패턴의 쓰러짐(Collapse)을 방지하며, 코어(Core) 및 페리(Peri)부의 게이트를 안정적으로 확보하여 생산량을 향상시키는 효과가 있다. In the method of manufacturing a semiconductor device according to the present invention, the photosensitive film pattern is collapsed by forming a photosensitive film pattern by performing an exposure and development process using a gate mask having a wider gate line width on an isolation region than a gate line width on an active region. It prevents, and stably secures the gates of the core and the ferry, thereby improving the yield.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

소자 분리 영역 및 활성 영역이 구비된 반도체 기판 상부에 게이트 산화 및 게이트 물질층을 형성하는 단계;Forming a gate oxide and a gate material layer over the semiconductor substrate having the device isolation region and the active region; 활성 영역 상의 게이트 선폭보다 상기 소자 분리 영역 상의 게이트 선폭이 넓게 형성된 게이트용 마스크를 이용한 노광 및 현상 공정으로 상기 게이트 물질층 상에 감광막 패턴을 형성하는 단계;Forming a photoresist pattern on the gate material layer by an exposure and development process using a gate mask having a wider gate line width on the device isolation region than a gate line width on an active region; 상기 감광막 패턴을 마스크로 상기 게이트 물질층 및 게이트 산화막을 식각하여 게이트 패턴을 형성하는 단계; 및Etching the gate material layer and the gate oxide layer using the photoresist pattern as a mask to form a gate pattern; And 게이트 패턴 측벽에 스페이서를 형성하는 단계;Forming a spacer on the gate pattern sidewalls; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 게이트 산화막은 20 내지 500 Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The gate oxide film is a manufacturing method of a semiconductor device, characterized in that formed to a thickness of 20 to 500 kPa. 제 1 항에 있어서, The method of claim 1, 상기 게이트 산화막은 TEOS 산화막 또는 HTO 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. And the gate oxide film is formed of a TEOS oxide film or an HTO oxide film. 제 1 항에 있어서, The method of claim 1, 상기 게이트 물질층은 게이트 도전층 및 게이트 하드마스크층으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. Wherein the gate material layer is formed of a gate conductive layer and a gate hard mask layer. 제 1 항에 있어서, The method of claim 1, 상기 감광막 패턴은 10 내지 5000 Å 의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The photosensitive film pattern is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 10 to 5000 kPa. 제 1 항에 있어서, The method of claim 1, 상기 소자 분리 영역 상부의 게이트용 마스크 선폭은 0.01 내지 1μm 인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device, characterized in that the gate mask line width on the device isolation region is 0.01 to 1 μm.
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