KR100671605B1 - Method of manufacturing a capacitor in a semiconductor device - Google Patents

Method of manufacturing a capacitor in a semiconductor device Download PDF

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KR100671605B1
KR100671605B1 KR1019990032597A KR19990032597A KR100671605B1 KR 100671605 B1 KR100671605 B1 KR 100671605B1 KR 1019990032597 A KR1019990032597 A KR 1019990032597A KR 19990032597 A KR19990032597 A KR 19990032597A KR 100671605 B1 KR100671605 B1 KR 100671605B1
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layer
tio
capacitor
bst
temperature
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KR20010017210A (en
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임찬
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2

Abstract

본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, Ta2O5와 TiO2의 혼합층과 BST층으로 적층 구조의 유전체층을 도입하므로써, 캐패시터의 하부전극으로 폴리실리콘을 사용할 수 있게 하여 BST 캐패시터의 하부 전극으로 노블 메탈을 사용함에 의해 발생되는 문제를 방지할 수 있는 반도체 소자의 캐패시터 제조 방법이 개시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and by introducing a dielectric layer having a laminated structure as a mixed layer of Ta 2 O 5 and TiO 2 and a BST layer, it is possible to use polysilicon as a lower electrode of the capacitor, thereby lowering the bottom of the BST capacitor. Disclosed is a method of manufacturing a capacitor of a semiconductor device capable of preventing a problem caused by using a noble metal as an electrode.

Ta2O5, TiO2, BST, 유전체층Ta2O5, TiO2, BST, Dielectric Layer

Description

반도체 소자의 캐패시터 제조 방법{Method of manufacturing a capacitor in a semiconductor device} Method of manufacturing a capacitor in a semiconductor device             

도 1a 내지 1c는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.1A to 1C are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11 : 반도체 기판 12 : 하부전극11 semiconductor substrate 12 lower electrode

13 : 질화막 14 : TiO2가 혼합된 Ta2O5층13: nitride film 14: Ta 2 O 5 layer mixed with TiO 2

15 : BST층 145 : 유전체층15: BST layer 145: dielectric layer

16 : 상부전극16: upper electrode

본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 특히 고유전 특성을 가진 Ta2O5층 및 BST층의 적층 구조를 유전체층으로 이용하는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device using a stacked structure of a Ta 2 O 5 layer and a BST layer having high dielectric properties as a dielectric layer.

일반적으로, 반도체 소자가 고집적화 및 소형화되어감에 따라 캐패시터가 차지하는 면적 또한 줄어들고 있는 추세이다. 캐패시터의 면적이 줄어들고 있음에도 불구하고 소자의 동작에 필요한 캐패시터의 정전 용량은 확보되어야 한다. 정전 용량을 확보하기 위해 하부 전극을 3차원 구조로 형성하여 유효 표면적을 증대시키고 있으나, 이 방법 역시 한계에 도달하여 256M DRAM급 이상의 고집적 반도체 소자에는 적용할 수 없는 실정이다. 정전 용량을 확보하기 위한 다른 방법은 높은 유전율을 갖는 유전체를 사용하여 캐패시터를 제조하는 것이다.In general, as semiconductor devices are highly integrated and miniaturized, the area occupied by capacitors is also decreasing. Although the area of the capacitor is decreasing, the capacitance of the capacitor required for the operation of the device must be secured. In order to secure the capacitance, the lower electrode is formed in a three-dimensional structure to increase the effective surface area, but this method also reaches a limit and cannot be applied to a highly integrated semiconductor device of 256M DRAM or more. Another way to ensure capacitance is to manufacture a capacitor using a dielectric having a high dielectric constant.

최근, 높은 유전율을 갖는 BST를 사용하여 BST 캐패시터를 제조하는 방법이 연구되고 있다. BST 캐패시터는 폴리실리콘 콘택 등과 같은 하부 구조가 형성된 반도체 기판 상에 Pt, Ru, Ir 등과 같은 노블 메탈(noble metal)을 사용하여 하부전극을 형성하고, 노블 메탈 하부전극 상에 BST를 증착 및 열처리하여 BST 유전체층을 형성하고, 노블 메탈을 사용하여 상부전극을 형성하여 제조된다.Recently, a method of manufacturing a BST capacitor using BST having a high dielectric constant has been studied. The BST capacitor forms a lower electrode using a noble metal such as Pt, Ru, Ir, etc. on a semiconductor substrate on which a lower structure such as polysilicon contact is formed, and deposits and heat-treats the BST on the noble metal lower electrode. It is produced by forming a BST dielectric layer and forming an upper electrode using a noble metal.

이와 같은 기존의 캐패시터 제조 방법에 있어서, 노블 메탈 하부전극 상에 BST 유전체층을 형성하기 위해, BST를 증착한 후에 O2나 N2O 분위기에서 열처리를 실시하게 되는데, 이때 폴리실리콘 플러그와 노블 메탈 하부전극과 계면에 실리콘이 석출되는 문제가 발생된다. 폴리실리콘 플러그와 노블 메탈 하부 전극과의 반응 을 억제시키기 위하여, 폴리실리콘 플러그와 노블 메탈 하부 전극 사이에 TiN/Ti을 이용하여 배리어 메탈층을 형성하지만, O2나 N2O 분위기에서의 열처리 공정 동안 배리어 메탈층이 산화될 뿐만 아니라 실리콘의 확산을 완전히 방지할 수 없어 BST 유전체층의 특성이 열화되며, 결과적으로 캐패시터의 정전 용량(capacitance)이 저하되는 문제점이 있다.In such a conventional capacitor manufacturing method, in order to form a BST dielectric layer on the noble metal lower electrode, after the BST is deposited, heat treatment is performed in an O 2 or N 2 O atmosphere, wherein the polysilicon plug and the noble metal lower electrode are used. The problem of precipitation of silicon at the interface with the electrode occurs. In order to suppress the reaction between the polysilicon plug and the noble metal lower electrode, a barrier metal layer is formed between the polysilicon plug and the noble metal lower electrode using TiN / Ti, but the heat treatment process is performed in an O 2 or N 2 O atmosphere. Not only does the barrier metal layer oxidize, but also the diffusion of silicon cannot be completely prevented, which deteriorates the characteristics of the BST dielectric layer, resulting in a decrease in the capacitance of the capacitor.

따라서, 본 발명은 Ta2O5와 TiO2의 혼합층과 BST층으로 적층 구조의 유전체층을 도입하므로써, 캐패시터의 하부전극으로 폴리실리콘을 사용할 수 있게 하여 BST 캐패시터의 하부 전극으로 노블 메탈을 사용함에 의해 발생되는 문제를 방지할 수 있는 반도체 소자의 캐패시터 제조 방법을 제공하는데 그 목적이 있다.
Accordingly, the present invention introduces a multilayered dielectric layer into a mixed layer of Ta 2 O 5 and TiO 2 and a BST layer, thereby making it possible to use polysilicon as the lower electrode of the capacitor and using a noble metal as the lower electrode of the BST capacitor. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device that can prevent a problem from occurring.

이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조 방법은 기판 상에 폴리실리콘을 사용하여 하부 전극을 형성한 후, 세정 및 급속 열 질화 처리하는 단계; 상기 폴리실리콘 하부 전극 상에 TiO2가 혼합된 Ta2O5층을 형성하는 단계; 상기 TiO2가 혼합된 Ta2O5층 상에 BST층을 형성하고, 이로 인하여 상기 TiO2가 혼합된 Ta2O5층과 상기 BST층이 적층된 유전체층이 형성되는 단계; 및 상기 유전체층 상에 노블 메탈을 사용하여 상부 전극을 형성하는 단계를 포함하여 이루 어지는 것을 특징으로 한다.
According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming a lower electrode using polysilicon on a substrate, followed by cleaning and rapid thermal nitriding; Forming a Ta 2 O 5 layer containing TiO 2 mixed on the polysilicon bottom electrode; Steps that form the BST layer on which the TiO 2 mixture of Ta 2 O 5 layer, a TiO 2 which due to the mixing of Ta 2 O 5 layer and the BST layer is laminated to form a dielectric layer; And forming an upper electrode using a noble metal on the dielectric layer.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1a 내지 1c는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1C are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.

도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11) 상에 캐패시터의 하부 전극(12)을 형성한 후, 세정 공정 및 급속 열 질화 처리(rapid thermal nitridation; RTN)를 실시한다. 하부 전극(12) 상에 TiO2가 혼합된 Ta2O5층(14)을 형성한다.Referring to FIG. 1A, after forming a lower electrode 12 of a capacitor on a substrate 11 on which various elements for forming a semiconductor device are formed, a cleaning process and rapid thermal nitridation (RTN) are performed. do. The Ta 2 O 5 layer 14 having TiO 2 mixed thereon is formed on the lower electrode 12.

상기에서, 하부 전극(12)은 도프트 폴리실리콘을 증착하여 형성된다. 세정 공정은 폴리실리콘 하부 전극(12)의 표면에 생성된 자연 산화막을 제거하기 위하여 HF 나 BOE 용액을 사용한다. 급속 열 질화 처리는 후속 캐패시터의 유전체층 증착시나 증착 후에 산소 분위기에서 열처리할 때 폴리실리콘 하부 전극(12)의 표면이 산화되어 캐패시터의 유효 산화막 두께의 증가를 방지하기 위하여 NH3 가스 분위기에서 800 내지 950℃ 온도로 실시하고, 이로 인하여 폴리실리콘 하부 전극(12)의 표면에 질화막(13)이 형성된다.In the above, the lower electrode 12 is formed by depositing doped polysilicon. The cleaning process uses HF or BOE solution to remove the native oxide film formed on the surface of the polysilicon lower electrode 12. The rapid thermal nitriding treatment is performed at 800 to 950 in an NH 3 gas atmosphere to prevent the surface of the polysilicon lower electrode 12 from oxidizing and increasing the effective oxide film thickness of the capacitor when the dielectric layer of the next capacitor is deposited or heat treated in an oxygen atmosphere after deposition. It is carried out at a temperature of ℃, thereby the nitride film 13 is formed on the surface of the polysilicon lower electrode 12.

TiO2가 혼합된 Ta2O5층(14)은 TiO2의 성분이 Ta2O 5의 성분에 대해서 8mol% 정도로 유지되도록 하며, 이후 유전율을 극대화하기 위하여 열처리 공정을 실시하여 형성한다. 열처리 공정은 750 내지 800℃의 온도에서 1시간 동안 실시하는데, 이때 열처리 분위기를 N2나 Ar이 아닌 O2나 N2O를 이용하여 실시하게 되면 TiO 2가 혼합된 Ta2O5층(14) 내의 산소 공핍 결함이나 탄소, 수소 및 수분에 의한 결함도 효과적으로 제거할 수 있다. 이러한 효과를 극대화시키기 위해 열처리 공정 전에 300 내지 400℃의 온도에서 O2나 N2O 플라즈마를 처리하거나, UV/O3 처리를 실시할 수 있다.The TiO 2 is mixed Ta 2 O 5 layer 14, and to maintain the components of TiO 2 so 8mol% with respect to the components of the Ta 2 O 5, is formed by performing the heat treatment process in order to maximize the dielectric constant after. The heat treatment process is carried out for 1 hour at a temperature of 750 to 800 ℃, when the heat treatment atmosphere is carried out using O 2 or N 2 O rather than N 2 or Ar Ta 2 O 5 layer (14) mixed with TiO 2 Oxygen depletion defects in a) and defects due to carbon, hydrogen, and moisture can also be effectively removed. In order to maximize this effect, the O 2 or N 2 O plasma may be treated at a temperature of 300 to 400 ° C. or UV / O 3 may be performed before the heat treatment process.

한편, Ta2O5 자체의 유전율 상수 값은 20 내지 25로 알려져 있으나, 본 발명에서와 같이 혼합 박막으로 형성하는 경우에는 유전율을 50 이상으로 증대시킬 수 있다. 그러나, TiO2의 성분이 8mol% 이상인 경우에는 오히려 TiO2가 혼합된 Ta2O5층(14)의 유전율이 감소하게 되므로 TiO2의 양을 반드시 8mol% 정도로 유지시키는 것이 중요하다. 또한, 열처리 온도를 800℃ 이상으로 할 경우에도 TiO2가 혼합된 Ta2O5층(14)의 유전율이 감소하게 된다.On the other hand, the dielectric constant constant value of Ta 2 O 5 itself is known to be 20 to 25, when forming a mixed thin film as in the present invention can increase the dielectric constant to 50 or more. However, when the TiO 2 component is 8 mol% or more, the dielectric constant of the Ta 2 O 5 layer 14 mixed with TiO 2 is reduced, so it is important to keep the amount of TiO 2 at about 8 mol%. In addition, even when the heat treatment temperature is 800 ° C or higher, the dielectric constant of the Ta 2 O 5 layer 14 in which TiO 2 is mixed is reduced.

도 1b를 참조하면, TiO2가 혼합된 Ta2O5층(14) 상에 BST층(15)을 형성하고, 이로 인하여 TiO2가 혼합된 Ta2O5층(14)과 함께 적층 구조의 유전체층(145)이 형성된다.Referring to Figure 1b, TiO 2 is mixed with Ta 2 O 5 layer 14 a on the multilayer structure with a BST layer 15, a Ta 2 O 5 layer 14, a TiO 2 mixed because of this to form a Dielectric layer 145 is formed.

상기에서, BST층(15)은 Ba(DPM)2, Sr(DPM) 및 TiO2(DPM)2를 이용하여 400 내지 450℃의 온도 조건 및 1 내지 2Torr의 압력 조건에서 리퀴드 소오스(liquid source) CVD 방법으로 증착하거나, 스퍼터법으로 증착한 후, 유전율을 극대화하기 위하여 열처리 공정을 실시하여 형성한다. 열처리 공정은 300 내지 400℃의 온도에서 O2나 N2O 플라즈마를 처리를 실시하거나 UV/O3 처리를 실시하여 불순물을 제거한 후, 600 내지 700℃의 온도에서 산소 분위기로 열처리를 실시한다.In the above, the BST layer 15 is a liquid source at a temperature condition of 400 to 450 ° C. and a pressure condition of 1 to 2 Torr using Ba (DPM) 2 , Sr (DPM) and TiO 2 (DPM) 2 . After the deposition by the CVD method or the deposition by the sputtering method, it is formed by performing a heat treatment process to maximize the dielectric constant. In the heat treatment step, O 2 or N 2 O plasma is treated at a temperature of 300 to 400 ° C. or UV / O 3 is removed to remove impurities, followed by heat treatment in an oxygen atmosphere at a temperature of 600 to 700 ° C.

도 1c를 참조하면, 유전체층(145) 상에 Pt, Ru, Ir 등과 같은 노블 메탈을 사용하여 상부 전극(16)을 형성한 후, 전체 시료를 질소 분위기에서 400 내지 500℃의 온도에서 열처리하여 MIS(Metal-Insulator-Silicon) 구조의 고유전체 캐패시터가 제조된다.Referring to FIG. 1C, after forming the upper electrode 16 using a noble metal such as Pt, Ru, Ir, and the like on the dielectric layer 145, the entire sample is heat-treated at a temperature of 400 to 500 ° C. under a nitrogen atmosphere, and MIS. A high dielectric capacitor of (Metal-Insulator-Silicon) structure is manufactured.

상술한 바와 같이, 본 발명은 Ta2O5와 TiO2의 혼합층과 BST층으로 적층 구조의 유전체층을 도입하므로써, 캐패시터의 하부전극으로 폴리실리콘을 사용할 수 있게 하여 BST 캐패시터의 하부 전극으로 노블 메탈을 사용함에 의해 발생되는 문제를 방지할 수 있을 뿐만 아니라, 장벽금속속층을 형성하지 않고도 열처리 공정에 따른 산화에 의한 캐패시터의 산화 내성을 개선할 수 있고, 캐패시터의 유전율을 향상시킬 수 있으며, BST 유전체막의 하부 전극으로 증착이 용이한 폴리실리콘층을 사용하므로 캐패시터 제조 공정을 단순화할 수 있다.As described above, the present invention introduces a layered dielectric layer into the mixed layer of Ta 2 O 5 and TiO 2 and the BST layer, thereby enabling the use of polysilicon as the lower electrode of the capacitor, thereby making the noble metal the lower electrode of the BST capacitor. In addition to preventing the problems caused by the use, it is possible to improve the oxidation resistance of the capacitor due to oxidation by the heat treatment process without forming a barrier metal layer, improve the dielectric constant of the capacitor, As the lower electrode uses a polysilicon layer that is easy to deposit, the capacitor manufacturing process can be simplified.

Claims (5)

기판 상에 폴리실리콘을 사용하여 하부 전극을 형성하는 단계;Forming a bottom electrode using polysilicon on the substrate; 상기 폴리실리콘 하부 전극 상에 TiO2가 혼합된 Ta2O5층을 형성하는 단계;Forming a Ta 2 O 5 layer containing TiO 2 mixed on the polysilicon bottom electrode; 상기 TiO2가 혼합된 Ta2O5층 상에 BST층을 형성하여 상기 TiO2가 혼합된 Ta2O5층과 상기 BST층을 포함하는 유전체층이 형성되는 단계;및Step in which the dielectric layer containing the TiO 2 is mixed with Ta 2 O 5 layer a BST layer is the TiO 2 mixture of Ta 2 O 5 layer and the BST layer to form a formation; and 상기 유전체층 상에 노블 메탈을 사용하여 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.And forming an upper electrode on the dielectric layer by using a noble metal. 제 1 항에 있어서,The method of claim 1, 상기 TiO2가 혼합된 Ta2O5층은 TiO2의 성분을 Ta2O 5의 성분에 대해서 8mol%로 유지되도록 증착한 후, O2 또는 N2O 분위기에서 750 내지 800℃의 온도로 1시간 동안 열처리를 실시하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The TiO 2 mixed Ta 2 O 5 layer is deposited such that the TiO 2 component is maintained at 8 mol% with respect to the Ta 2 O 5 component, and then at a temperature of 750 to 800 ° C. in an O 2 or N 2 O atmosphere. Capacitor manufacturing method of a semiconductor device, characterized in that formed by performing a heat treatment for a time. 제 1 항에 있어서,The method of claim 1, 상기 TiO2가 혼합된 Ta2O5층은 TiO2의 성분을 Ta2O 5의 성분에 대해서 8mol%로 유지되도록 증착한 후, 300 내지 400℃의 온도에서 O2나 N2O 플라즈마를 처리하거나 UV/O3 처리하고, O2 또는 N2O 분위기에서 750 내지 800℃의 온도로 1시간 동안 열처리를 실시하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The TiO 2 mixed Ta 2 O 5 layer is deposited so that the TiO 2 component is maintained at 8 mol% relative to the Ta 2 O 5 component, and then treated with O 2 or N 2 O plasma at a temperature of 300 to 400 ℃ Or UV / O 3 treatment and heat treatment for 1 hour at a temperature of 750 to 800 ° C. in an O 2 or N 2 O atmosphere to form a capacitor for a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 BST층은 Ba(DPM)2, Sr(DPM) 및 TiO2(DPM)2를 이용하여 400 내지 450℃의 온도 조건 및 1 내지 2Torr의 압력 조건에서 리퀴드 소오스 CVD 방법으로 증착하거나, 스퍼터법으로 증착한 후, 300 내지 400℃의 온도에서 O2나 N2O 플라즈마를 처리하거나 UV/O3 처리하고, 600 내지 700℃의 온도 조건 및 산소 분위기에서 열처리하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The BST layer is deposited by a liquid source CVD method at a temperature of 400 to 450 ° C. and a pressure of 1 to 2 Torr using Ba (DPM) 2 , Sr (DPM), and TiO 2 (DPM) 2 , or by sputtering. After deposition, the O 2 or N 2 O plasma treatment or UV / O 3 treatment at a temperature of 300 to 400 ℃, and a heat treatment in the temperature conditions and oxygen atmosphere of 600 to 700 ℃ characterized in that the Capacitor Manufacturing Method. 제 1 항에 있어서,The method of claim 1, 상기 상부 전극은 Pt, Ru, Ir과 같은 노블 메탈을 증착한 후, 질소 분위기에서 400 내지 500℃의 온도에서 열처리하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The upper electrode is a capacitor manufacturing method of a semiconductor device, characterized in that formed by depositing a noble metal such as Pt, Ru, Ir, heat treatment at a temperature of 400 to 500 ℃ in a nitrogen atmosphere.
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KR100984075B1 (en) * 2009-10-09 2010-09-28 삼성탈레스 주식회사 Variable band pass filter and configuring method therefor

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KR19990048782A (en) * 1997-12-10 1999-07-05 김영환 Capacitor Formation Method of Semiconductor Device

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KR19990048782A (en) * 1997-12-10 1999-07-05 김영환 Capacitor Formation Method of Semiconductor Device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100984075B1 (en) * 2009-10-09 2010-09-28 삼성탈레스 주식회사 Variable band pass filter and configuring method therefor

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