KR100624927B1 - Method of manufacturing a capacitor in a semiconductor device - Google Patents

Method of manufacturing a capacitor in a semiconductor device Download PDF

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KR100624927B1
KR100624927B1 KR1019990032594A KR19990032594A KR100624927B1 KR 100624927 B1 KR100624927 B1 KR 100624927B1 KR 1019990032594 A KR1019990032594 A KR 1019990032594A KR 19990032594 A KR19990032594 A KR 19990032594A KR 100624927 B1 KR100624927 B1 KR 100624927B1
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layer
capacitor
tio
semiconductor device
mixed
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KR20010017207A (en
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임찬
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2

Abstract

본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, TiO2가 혼합된 Ta2O5 혼합물층과 Al2O3층을 적층되게하여 캐패시터의 유전체층을 형성하므로써, 상부 및 하부 전극을 폴리실리콘으로 사용하면서 Ta2O5의 유전율을 증가시켜 유효 산화막의 두께를 감소시킬 수 있는 반도체 소자의 캐패시터 제조 방법이 개시된다.The present invention using as, TiO 2 is mixed with Ta 2 O 5 mixture layer and the Al 2 O to be laminated three-layer By forming the dielectric layer of the capacitor upper and lower electrodes of the capacitor manufacturing method of the semiconductor device of polysilicon While increasing the dielectric constant of Ta 2 O 5 is disclosed a method of manufacturing a capacitor of a semiconductor device capable of reducing the thickness of the effective oxide film.

캐패시터, TiO2가 혼합된 Ta2O5 혼합물층, Al2O3층, Ta2O5/Al2O3 유전체층Capacitor, Ta2O5 mixture layer with TiO2 mixed, Al2O3 layer, Ta2O5 / Al2O3 dielectric layer

Description

반도체 소자의 캐패시터 제조 방법{Method of manufacturing a capacitor in a semiconductor device} Method of manufacturing a capacitor in a semiconductor device             

도 1a 내지 1d는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.1A to 1D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11: 기판 12: 하부 전극11: substrate 12: lower electrode

13: 질화막 14: TiO2가 혼합된 Ta2O5층13: nitride film 14: Ta 2 O 5 layer mixed with TiO 2

15: Al2O3층 145: 캐패시터의 유전체층15: Al 2 O 3 layer 145: dielectric layer of the capacitor

16: 상부 전극16: upper electrode

본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 특히 TiO2가 혼합된 Ta2O5 혼합물층과 Al2O3층을 적층되게하여 캐패시터의 유전체층을 형성하므로써, 상부 및 하부 전극을 폴리실리콘으로 사용하면서 Ta2O5의 유전율을 증가시켜 유효 산화막의 두께를 감소시킬 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and in particular, by stacking a Ta 2 O 5 mixture layer and an Al 2 O 3 layer mixed with TiO 2 to form a dielectric layer of a capacitor, the upper and lower electrodes are made of polysilicon. The present invention relates to a method for manufacturing a capacitor of a semiconductor device which can reduce the thickness of an effective oxide film by increasing the dielectric constant of Ta 2 O 5 during use.

일반적으로, 반도체 소자가 고집적화 및 소형화되어감에 따라 캐패시터가 차지하는 면적 또한 줄어들고 있는 추세이다. 캐패시터의 면적이 줄어들고 있음에도 불구하고 소자의 동작에 필요한 캐패시터의 정전 용량은 확보되어야 한다. 정전 용량을 확보하기 위해 하부 전극을 3차원 구조로 형성하여 유효 표면적을 증대시키고 있으나, 이 방법 역시 한계에 도달하여 256M DRAM급 이상의 고집적 반도체 소자에는 적용할 수 없는 실정이다. 정전 용량을 확보하기 위한 다른 방법은 높은 유전율을 갖는 유전체를 사용하여 캐패시터를 제조하는 것이다.In general, as semiconductor devices are highly integrated and miniaturized, the area occupied by capacitors is also decreasing. Although the area of the capacitor is decreasing, the capacitance of the capacitor required for the operation of the device must be secured. In order to secure the capacitance, the lower electrode is formed in a three-dimensional structure to increase the effective surface area, but this method also reaches a limit and cannot be applied to a highly integrated semiconductor device of 256M DRAM or more. Another way to ensure capacitance is to manufacture a capacitor using a dielectric having a high dielectric constant.

유전율 상수 값이 20 내지 25이면서 높은 절연파괴 전압 특성을 갖는 Ta2O5를 캐패시터의 유전체층으로 사용하고 있으나, 반도체 소자가 고집적화 및 소형화되어 감에 따라 Ta2O5 유전체층이 갖는 유전율로는 충분한 정전 용량을 확보할 수 없어 반도체 소자의 고집적화 실현에 한계가 있다. 또한, 캐패시터의 유전체층으로 Ta2O5를 이용하여 캐패시터를 형성하는 경우에는 하부 전극으로 폴리실리콘을 사용하고 상부 전극으로는 TiN을 사용하는 것이 일반적인 추세인데, Ta2O5 캐패시터는 유효 산화막 두께(TOX)의 한계가 30Å 정도로 두꺼울 뿐만 아니라, 상부 전극으로 TiN을 사용하기 때문에 TiN을 증착한 후에 750℃ 이상의 고온 열공정을 실시하면 유효 산화막 두께가 증가하는 문제점이 있다.Ta 2 O 5 with high dielectric breakdown voltage and dielectric breakdown voltage of 20 to 25 is used as the dielectric layer of the capacitor. However, as the semiconductor device becomes more integrated and smaller, the dielectric constant of the Ta 2 O 5 dielectric layer is sufficient. Since the capacity cannot be secured, there is a limit to the high integration of semiconductor devices. In addition, when a capacitor is formed using Ta 2 O 5 as the dielectric layer of the capacitor, polysilicon is used as the lower electrode and TiN is used as the upper electrode. The Ta 2 O 5 capacitor has an effective oxide film thickness ( T OX ) is not only a thick limit of about 30 μs, but also because TiN is used as the upper electrode, there is a problem that an effective oxide film thickness increases when a high temperature thermal process of 750 ° C. or higher is performed after the deposition of TiN.

한편, 캐패시터의 하부 전극 및 상부 전극을 폴리실리콘을 사용하면서 캐패시터 형성 후 800℃ 이상의 열 공정에서도 캐패시터의 특성이 열화 되지 않는 장점이 있는 Al2O3를 이용하여 캐패시터를 형성하는 방법이 제시되고 있다. Al2O 3 캐패시터는 유효 산화막 두께(TOX)의 한계가 25Å 정도로 Ta2O5 보다 약간 낮지만, Al2O3의 유전율 상수 값이 8 내지 15 정도로 Ta2O5보다 매우 낮아 256M DRAM급 이상의 고집적 반도체 소자에 적용할 수 없는 실정이다.On the other hand, a method of forming a capacitor using Al 2 O 3 has the advantage that the characteristics of the capacitor does not deteriorate even in the thermal process of 800 ℃ or more after the formation of the capacitor using the polysilicon lower electrode and the upper electrode has been proposed. . Al 2 O 3 capacitor has a limit of effective oxide thickness (T OX ) is slightly lower than Ta 2 O 5 at 25Å, but the dielectric constant of Al 2 O 3 is much lower than Ta 2 O 5 at 8-15, which is 256M DRAM class. It is not applicable to the above highly integrated semiconductor device.

따라서, 본 발명은 Ta2O5에 TiO2를 혼합시킨 혼합물층과 Al2O 3층이 적층된 구조를 캐패시터의 유전체층으로 사용하므로, Ta2O5를 단독으로 사용하는 유전체층보다 유전율을 증가시킬 수 있고, Al2O3층으로 인해 캐패시터의 상부 전극으로 폴리실리콘을 사용 가능하게 하여 공정을 단순화할 수 있을 뿐만 아니라 Ta2O5를 단독으로 사용하는 유전체층보다 유효 산화막의 두께를 감소시킬 수 있어 유전율을 더욱 증가시킬 수 있는 반도체 소자의 캐패시터 제조 방법을 제공하는데 그 목적이 있다.
Therefore, the present invention uses a structure in which a mixture layer of TiO 2 mixed with Ta 2 O 5 and an Al 2 O 3 layer is stacked as a dielectric layer of the capacitor, thereby increasing the dielectric constant of the dielectric layer using Ta 2 O 5 alone. Due to the Al 2 O 3 layer, polysilicon can be used as the upper electrode of the capacitor, simplifying the process and reducing the thickness of the effective oxide film than the dielectric layer using Ta 2 O 5 alone. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device which can further increase the dielectric constant.

이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조 방법은 기판 상에 하부 전극을 형성하는 단계; 상기 하부 전극 상에 TiO2가 혼합된 Ta2O5층을 증착하는 단계; 상기 TiO2가 혼합된 Ta2O5층 상에 Al2O3층을 증착하고, 이로 인하여 상기 TiO2가 혼합된 Ta2O5층과 상기 Al2O3층이 적층된 유전체층이 형성되는 단계; 및 상기 유전체층 상에 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.
Capacitor manufacturing method of a semiconductor device according to the present invention for achieving this object comprises the steps of forming a lower electrode on a substrate; Depositing a Ta 2 O 5 layer containing TiO 2 mixed on the lower electrode; Step in which the TiO 2 is deposited a Al 2 O 3 layer on the mixing Ta 2 O 5 layer, a Due to this the TiO 2 has a laminated mixed Ta 2 O 5 layer and said Al 2 O 3 layer dielectric formed ; And forming an upper electrode on the dielectric layer.

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 1d는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.

도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11) 상에 캐패시터의 하부 전극(12)을 형성한 후, 세정 공정 및 급속 열 질화 처리(rapid thermal nitridation; RTN)를 실시한다.Referring to FIG. 1A, after forming a lower electrode 12 of a capacitor on a substrate 11 on which various elements for forming a semiconductor device are formed, a cleaning process and rapid thermal nitridation (RTN) are performed. do.

상기에서, 하부 전극(12)은 도프트 폴리실리콘을 증착하여 형성된다. 세정 공정은 하부 전극(12)의 표면에 생성된 자연 산화막을 제거하기 위하여 HF 나 BOE 용액을 사용한다. 급속 열 질화 처리는 후속 캐패시터의 유전체층 증착시나 증착 후에 산소 분위기에서 열처리할 때 하부 전극(12)의 표면이 산화되어 캐패시터의 유효 산화막 두께의 증가를 방지하기 위하여 NH3 가스 분위기에서 800 내지 950℃ 온도로 실시하고, 이로 인하여 하부 전극(12)의 표면에 질화막(13)이 형성된다.In the above, the lower electrode 12 is formed by depositing doped polysilicon. The cleaning process uses HF or BOE solution to remove the native oxide film formed on the surface of the lower electrode 12. The rapid thermal nitriding treatment is performed at 800 to 950 ° C. in a NH 3 gas atmosphere to prevent the surface of the lower electrode 12 from oxidizing and increasing the effective oxide film thickness of the capacitor during the deposition of the dielectric layer of the next capacitor or during heat treatment in an oxygen atmosphere after deposition. In this way, the nitride film 13 is formed on the surface of the lower electrode 12.

도 1b를 참조하면, 하부 전극(12) 상에 TiO2가 혼합된 Ta2O5층(14)을 증착한다.Referring to FIG. 1B, a Ta 2 O 5 layer 14 having TiO 2 mixed thereon is deposited on the lower electrode 12.

상기에서, TiO2가 혼합된 Ta2O5층(14)은 TiO2의 성분이 Ta2O5의 성분에 대해서 8mol% 정도로 유지되도록 하며, 이후 유전율을 극대화하기 위하여 열처리 공정을 실시한다. 열처리 공정은 750 내지 800℃의 온도에서 1시간 동안 실시하는데, 이때 열처리 분위기를 N2나 Ar이 아닌 O2나 N2O를 이용하여 실시하게 되면 TiO 2가 혼합된 Ta2O5층(14) 내의 산소 공핍 결함이나 탄소, 수소 및 수분에 의한 결함도 효과적으로 제거할 수 있다. 이러한 효과를 극대화시키기 위해 열처리 공정 전에 300 내지 400℃의 온도에서 O2나 N2O 플라즈마를 처리하거나, UV/O3 처리를 실시할 수 있다.In the above, the Ta 2 O 5 layer 14 mixed with TiO 2 is to maintain the TiO 2 component of about 8 mol% relative to the Ta 2 O 5 component, and then performs a heat treatment process to maximize the dielectric constant. The heat treatment process is carried out for 1 hour at a temperature of 750 to 800 ℃, when the heat treatment atmosphere is carried out using O 2 or N 2 O rather than N 2 or Ar Ta 2 O 5 layer (14) mixed with TiO 2 Oxygen depletion defects in a) and defects due to carbon, hydrogen, and moisture can also be effectively removed. In order to maximize this effect, the O 2 or N 2 O plasma may be treated at a temperature of 300 to 400 ° C. or UV / O 3 may be performed before the heat treatment process.

한편, Ta2O5 자체의 유전율 상수 값은 20 내지 25로 알려져 있으나, 본 발명에서와 같이 혼합 박막으로 형성하는 경우에는 유전율을 50 이상으로 증대시킬 수 있다. 그러나, TiO2의 성분이 8mol% 이상인 경우에는 오히려 TiO2가 혼합된 Ta2O5층(14)의 유전율이 감소하게 되므로 TiO2의 양을 반드시 8mol% 정도로 유지시키는 것이 중요하다. 또한, 열처리 온도를 800℃ 이상으로 할 경우에도 TiO2가 혼합된 Ta2O5층(14)의 유전율이 감소하게 된다.On the other hand, the dielectric constant constant value of Ta 2 O 5 itself is known to be 20 to 25, when forming a mixed thin film as in the present invention can increase the dielectric constant to 50 or more. However, when the TiO 2 component is 8 mol% or more, the dielectric constant of the Ta 2 O 5 layer 14 mixed with TiO 2 is reduced, so it is important to keep the amount of TiO 2 at about 8 mol%. In addition, even when the heat treatment temperature is 800 ° C or higher, the dielectric constant of the Ta 2 O 5 layer 14 in which TiO 2 is mixed is reduced.

도 1c를 참조하면, TiO2가 혼합된 Ta2O5층(14) 상에 Al2O3층(15)을 증착하고, 이로 인하여 TiO2가 혼합된 Ta2O5층(14)과 함께 적층 구조의 유전체층(145)이 형성된다.Referring to Figure 1c, TiO 2 is mixed with Ta 2 O 5 layer 14 onto the Al 2 O 3 layer 15 is deposited, and this reason TiO 2 is in conjunction with the mixing Ta 2 O 5 layer 14 to A dielectric layer 145 having a laminated structure is formed.

상기에서 Al2O3층(15)은 TMA(Al(CH3)3)와 H20를 원료 물질로 하여 300 내지 350℃의 온도 조건 및 수백 mTorr 내지 수 Torr 압력 조건에서 원자층증착(Atomic Layer Deposition ; ALD) 방법으로 증착한다. ALD 방법이란 원료 물질을 기판에 교대로 공급해 주면서 박막을 증착하는 방법으로, 원료 물질의 공급과 공급 사이에 퍼징 타임(purging time)을 두어, 증착하고자 하는 박막의 단원자층을 형성하는 기술을 말하며, 일명 디지털 화학기상증착(digital CVD)라 불려진다. 이와 같은 방법으로 형성된 Al2O3층(15)은 유전체막(145)의 캡핑층으로 작용하여 후에 형성될 상부 전극과 TiO2가 혼합된 Ta2O5층(14)과의 반응을 억제하는 역할을 한다. Al2O3층(15)을 형성한 후에는 300 내지 400℃의 온도에서 O2나 N2O 플라즈마를 처리하거나 UV/O3 처리를 추가로 실시하여 Al2O3층(15) 내의 불순물을 제거하는 과정을 도입하는 것도 가능하다.The Al 2 O 3 layer 15 is formed by atomic layer deposition (Atomic) at a temperature of 300 to 350 ° C. and several hundred mTorr to several Torr pressure conditions using TMA (Al (CH 3 ) 3 ) and H 2 0 as raw materials. Layer deposition (ALD). The ALD method is a method of depositing a thin film while alternately supplying a raw material to a substrate, and refers to a technology of forming a monoatomic layer of a thin film to be deposited by providing a purging time between the supply and the supply of the raw material. It is called digital CVD. The Al 2 O 3 layer 15 formed in this manner serves as a capping layer of the dielectric film 145 to suppress the reaction between the upper electrode to be formed later and the Ta 2 O 5 layer 14 mixed with TiO 2. Play a role. Impurity in the Al 2 O 3 layer 15, one after the O 2 or N 2 O by treating the plasma or carried further UV / O 3 treatment Al 2 O 3 layer 15 at a temperature of 300 to 400 ℃ form a It is also possible to introduce a process to remove it.

도 1d를 참조하면, 유전체층(145) 상에 도프트 폴리실리콘을 증착하여 상부 전극(16)을 형성한다.Referring to FIG. 1D, doped polysilicon is deposited on the dielectric layer 145 to form the upper electrode 16.

상술한 바와 같이, 본 발명은 Ta2O5에 TiO2를 혼합시킨 혼합물층과 Al2O3층이 적층된 구조를 캐패시터의 유전체층으로 사용하므로, Ta2O5를 단독으로 사용하는 유전체층보다 유전율을 증가시킬 수 있고, Al2O3층으로 인해 캐패시터의 상부 전극으로 폴리실리콘을 사용 가능하게 하여 공정의 단순화 및 제조 비용을 절감할 수 있을 뿐만 아니라 Ta2O5를 단독으로 사용하는 유전체층보다 유효 산화막의 두께를 감소시킬 수 있어 유전율을 더욱 증가시킬 수 있다.As described above, the present invention uses a structure in which a mixture layer in which TiO 2 is mixed with Ta 2 O 5 and an Al 2 O 3 layer is laminated as the dielectric layer of the capacitor, and thus the dielectric constant is higher than that of the dielectric layer using Ta 2 O 5 alone. The Al 2 O 3 layer allows the use of polysilicon as the upper electrode of the capacitor, which not only simplifies the process and reduces manufacturing costs, but also is more effective than the dielectric layer using Ta 2 O 5 alone. Since the thickness of the oxide film can be reduced, the dielectric constant can be further increased.

Claims (7)

기판 상에 하부 전극을 형성하는 단계;Forming a lower electrode on the substrate; 상기 하부 전극 상에 TiO2가 혼합된 Ta2O5층을 증착한 후, 열처리 공정을 실시하는 단계;Depositing a Ta 2 O 5 layer mixed with TiO 2 on the lower electrode and then performing a heat treatment process; 상기 TiO2가 혼합된 Ta2O5층 상에 Al2O3층을 원자층증착(ALD)법으로 증착하고, 이로 인하여 상기 TiO2가 혼합된 Ta2O5층과 상기 Al2O3층이 적층된 유전체층이 형성되는 단계;Depositing an Al 2 O 3 layer on the Ta 2 O 5 layer mixed with TiO 2 by atomic layer deposition (ALD), and thus the Ta 2 O 5 layer and the Al 2 O 3 layer mixed with TiO 2. Forming the laminated dielectric layer; 상기 유전체층 상에 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.And forming an upper electrode on the dielectric layer. 제 1 항에 있어서,The method of claim 1, 상기 TiO2가 혼합된 Ta2O5층은 TiO2의 성분을 Ta2O 5의 성분에 대해서 8mol%로 유지되도록 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The TiO 2 mixed Ta 2 O 5 layer is a capacitor manufacturing method of the semiconductor device, characterized in that for depositing to maintain the component of TiO 2 to 8 mol% relative to the component of Ta 2 O 5 . 제 1 항에 있어서,The method of claim 1, 상기 열처리 공정을 실시하기 전에 300 내지 400℃의 온도에서 O2나 N2O 플라즈마를 처리하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법,A method of manufacturing a capacitor of a semiconductor device, further comprising the step of treating the O 2 or N 2 O plasma at a temperature of 300 to 400 ℃ before performing the heat treatment process, 제 1 항에 있어서,The method of claim 1, 상기 열처리 공정을 실시하기 전에 300 내지 400℃의 온도에서 UV/O3 처리하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.Capacitor manufacturing method of a semiconductor device further comprising the step of UV / O 3 treatment at a temperature of 300 to 400 ℃ before performing the heat treatment process. 제 1 항에 있어서,The method of claim 1, 상기 Al2O3층은 TMA(Al(CH3)3)와 H20를 원료 물질로 하여 300 내지 350℃의 온도 조건 및 수백 mTorr 내지 수 Torr 압력 조건에서 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.The Al 2 O 3 layer is a semiconductor device characterized in that the deposition is carried out at a temperature condition of 300 to 350 ℃ and several hundred mTorr to several Torr pressure conditions using the TMA (Al (CH 3 ) 3 ) and H 2 0 as a raw material Capacitor Manufacturing Method. 제 1 항에 있어서,The method of claim 1, 상기 Al2O3층을 증착한 후에 300 내지 400℃의 온도에서 O2나 N2O 플라즈마를 처리하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.And depositing the Al 2 O 3 layer and then treating the O 2 or N 2 O plasma at a temperature of 300 to 400 ° C. 2 . 제 1 항에 있어서,The method of claim 1, 상기 Al2O3층을 증착한 후에 300 내지 400℃의 온도에서 UV/O3 처리하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조 방법.And depositing the Al 2 O 3 layer and then performing UV / O 3 treatment at a temperature of 300 to 400 ° C.
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JPS6235562A (en) * 1985-08-08 1987-02-16 Nec Corp Semiconductor device
JPH05259387A (en) * 1992-03-11 1993-10-08 Oki Electric Ind Co Ltd Manufacture of semiconductor device
KR970054073A (en) * 1995-12-27 1997-07-31 김광호 Method of manufacturing capacitors in semiconductor devices
US5688724A (en) * 1992-07-02 1997-11-18 National Semiconductor Corporation Method of providing a dielectric structure for semiconductor devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6235562A (en) * 1985-08-08 1987-02-16 Nec Corp Semiconductor device
JPH05259387A (en) * 1992-03-11 1993-10-08 Oki Electric Ind Co Ltd Manufacture of semiconductor device
US5688724A (en) * 1992-07-02 1997-11-18 National Semiconductor Corporation Method of providing a dielectric structure for semiconductor devices
KR970054073A (en) * 1995-12-27 1997-07-31 김광호 Method of manufacturing capacitors in semiconductor devices

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