KR100626740B1 - Method for forming inter layer dielectric in semiconductor device - Google Patents

Method for forming inter layer dielectric in semiconductor device Download PDF

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KR100626740B1
KR100626740B1 KR1020000036727A KR20000036727A KR100626740B1 KR 100626740 B1 KR100626740 B1 KR 100626740B1 KR 1020000036727 A KR1020000036727 A KR 1020000036727A KR 20000036727 A KR20000036727 A KR 20000036727A KR 100626740 B1 KR100626740 B1 KR 100626740B1
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film
forming
hsq
metal wiring
layer metal
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KR20020002525A (en
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이성은
박성기
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

본 발명은 저유전율 층간절연막의 유전율 감소를 방지하기 위한 층간절연막의 형성 방법에 관한 것으로, 본 발명의 층간절연막의 형성 방법은 반도체 기판 상에 제 1층 금속배선을 형성하는 단계, 상기 제 1층 금속배선 상에 HSQ 박막을 형성하는 단계, 상기 HSQ박막 표면에 수소원자를 주입시켜 수소에 의한 보호화를 실시하는 단계, 감광막을 마스크로 이용하여 상기 HSQ박막을 선택적으로 식각하여 상기 제 1층 금속배선이 노출되는 비아홀을 형성하는 단계, 상기 감광막을 제거하는 단계, 및 상기 비아홀을 통해 상기 제 1층 금속배선과 전기적으로 연결되는 제 2층 금속배선을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method of forming an interlayer insulating film for preventing a decrease in dielectric constant of a low dielectric constant interlayer insulating film, the method of forming an interlayer insulating film of the present invention comprises the steps of forming a first layer metal wiring on a semiconductor substrate, the first layer Forming an HSQ thin film on a metal wiring; implanting a hydrogen atom on the surface of the HSQ thin film to protect it with hydrogen; selectively etching the HSQ thin film using a photosensitive film as a mask to form the first layer metal And forming a via hole through which the wiring is exposed, removing the photoresist film, and forming a second layer metal wire electrically connected to the first layer metal wire through the via hole.

저유전율 층간절연막, 스핀온도포법, 비아홀, 금속배선, HSQ, FSG, MSQLow dielectric constant interlayer insulating film, spin temperature foaming method, via hole, metal wiring, HSQ, FSG, MSQ

Description

반도체 소자의 층간절연막 형성 방법{METHOD FOR FORMING INTER LAYER DIELECTRIC IN SEMICONDUCTOR DEVICE} METHODS FOR FORMING INTER LAYER DIELECTRIC IN SEMICONDUCTOR DEVICE             

도 1 내지 도 4는 본 발명의 실시예에 따른 층간절연막의 형성 방법을 나타낸 공정 단면도.
1 to 4 are cross-sectional views illustrating a method of forming an interlayer insulating film according to an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 실리콘기판 22 : 워드라인21: silicon substrate 22: word line

23 : 불순물접합층 25 : 제 1 층간절연막23 impurity bonding layer 25 first interlayer insulating film

26 : 비트라인 27 : 제 2 층간절연막26 bit line 27 second interlayer insulating film

30 : 캐패시터 31 : 제 3 층간절연막30 capacitor 31 third interlayer insulating film

32 : 티타늄 33 : 제 1 티타늄질화막32: titanium 33: first titanium nitride film

34 : 알루미늄 35 : 제 2 티타늄질화막34: aluminum 35: second titanium nitride film

36 : 제 1 산화막 37 : HSQ막 36: first oxide film 37: HSQ film

38 : 제 2 산화막 39a : 제 1층 금속배선38: second oxide film 39a: first layer metal wiring

39b : 제 2층 금속배선
39b: second layer metal wiring

본 발명은 반도체 메모리 소자의 제조 방법에 관한 것으로, 특히 저유전율을 갖는 층간절연막의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of forming an interlayer insulating film having a low dielectric constant.

최근에 소자의 집적도가 증가함에 따라 금속배선 폭의 감소로 금속배선저항 증가와 금속배선 사이의 간격이 좁아짐에 따라 기생 캐패시터 증가로 소자특성이 열화(전기신호처리 속도 지연문제)되는 문제가 대두되고 있는데, 이를 개선할 수 있는 방법으로 금속배선의 저항을 낮추어 주거나 금속배선 사이의 층간 절연막의 유전율(Dielectric constant)을 낮추는 것이다.Recently, as the integration of devices increases, the width of the metal wiring decreases due to the decrease in the width of the metal wiring, and the gap between the metal wiring becomes narrow, resulting in the deterioration of device characteristics due to the increase of parasitic capacitors. One way to improve this is to lower the resistance of the metal wires or to lower the dielectric constant of the interlayer insulating film between the metal wires.

이 중 금속배선의 저항을 낮추는 방법으로는 구리(Cu)와 같은 재료가 최근 관심이 부각되고 있으나, 실용화에 어려움이 많고, 종래기술의 알루미늄금속배선을 이용할 수 있는 방법으로 층간절연막의 저유전율화가 최근에 연구되고 있다.Among them, a material such as copper (Cu) has recently attracted attention as a method of lowering the resistance of metal wiring, but there are many difficulties in practical use, and low dielectric constant of interlayer insulating film is a method that can use aluminum metal wiring of the prior art. It is being studied recently.

그 대표적인 예로, FSG(Fluorine doped Silicate Glass; FSG)와 MSQ(Methyl SilsesQuioxane), HSQ(Hydrogen SilsesQuioxane) 등이 가장 보편적으로 연구되고 있다. 이 중 FSG는 유전율이 3.5 정도되어 일반적인 산화막(SiO2)의 유전율(3.9)보다 약간 낮고 MSQ는 2.5∼2.7, HSQ는 3.0 정도로 FSG에 비해 훨씬 낮기 때문에 최근 FSG보다도 활발히 연구되고 있다.
For example, Fluorine doped Silicate Glass (FSG), Methyl SilsesQuioxane (MSQ), and Hydrogen SilsesQuioxane (HSQ) are the most commonly studied. Among them, the FSG has a dielectric constant of about 3.5, which is slightly lower than that of the general oxide film (SiO 2 ), and the MSQ is 2.5 to 2.7 and the HSQ is about 3.0, which is much lower than that of the FSG.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로, 저유전율 층간절연막의 유전율 증가를 억제하고, 금속배선저항 및 금속배선 사이의 기생캐패시터의 증가를 방지하는데 적합한 층간절연막의 형성 방법을 제공함에 그 목적이 있다.
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a method of forming an interlayer insulating film suitable for suppressing an increase in dielectric constant of a low dielectric constant interlayer insulating film and preventing an increase in parasitic capacitor between metal wiring resistance and metal wiring. There is a purpose.

상기의 목적을 달성하기 위한 본 발명의 층간절연막 형성 방법은 반도체 기판 상에 제 1층 금속배선을 형성하는 단계, 상기 제 1층 금속배선 상에 HSQ 박막을 형성하는 단계, 상기 HSQ박막 표면에 수소원자를 주입시켜 수소에 의한 보호화를 실시하는 단계, 감광막을 마스크로 이용하여 상기 HSQ박막을 선택적으로 식각하여 상기 제 1층 금속배선이 노출되는 비아홀을 형성하는 단계, 상기 감광막을 제거하는 단계, 및 상기 비아홀을 통해 상기 제 1층 금속배선과 전기적으로 연결되는 제 2층 금속배선을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The interlayer insulating film forming method of the present invention for achieving the above object comprises the steps of forming a first layer metal wiring on a semiconductor substrate, forming an HSQ thin film on the first layer metal wiring, hydrogen on the surface of the HSQ thin film Implanting atoms to protect with hydrogen, selectively etching the HSQ thin film using a photosensitive film as a mask to form via holes through which the first layer metal wiring is exposed, and removing the photosensitive film; And forming a second layer metal wire electrically connected to the first layer metal wire through the via hole.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 1 내지 도 4는 본 발명의 실시예에 따른 메모리 소자의 금속배선 형성 방법을 나타낸 공정 단면도이다.1 to 4 are cross-sectional views illustrating a method of forming metal wirings in a memory device according to an exemplary embodiment of the present invention.

도 1에 도시된 바와 같이, 트랜지스터 및 캐패시터 즉, 실리콘기판(21) 상에 워드라인(22), 불순물접합층(23), 제 1 층간절연막(Inter Level Dielectric; ILD) (24)을 형성하고, 상기 워드라인(22) 양측의 불순물접합층(23)에 접속되는 콘택을 형성하고, 제 1 층간절연막(24) 상에 비트라인(26)을 형성한 다음, 상기 비트라인 (26) 상에 제 2 층간절연막(27)을 형성한다. 이어 상기 제 2 층간절연막(27)과 제 1 층간절연막(24)을 선택적으로 식각하여 상기 불순물접합층(23)과 접속되는 캐패시터콘택(28)을 형성하고, 상기 캐패시터콘택(28)을 포함한 전면에 캐패시터산화막 (29)를 형성한다. 이어 상기 캐패시터산화막(29)을 선택적으로 식각하여 상기 캐패시터콘택(28)을 통해 불순물접합층(23)과 접속되는 캐패시터(30)를 형성한 다음, 상기 캐패시터의 전면에 제 3 층간절연막(31)을 형성한 후, 화학적기계적평탄화 (Chemical Mechanical Polishing; CMP) 공정으로 제 3 층간절연막(31)을 평탄화한다.As shown in FIG. 1, a word line 22, an impurity bonding layer 23, and a first interlevel dielectric (ILD) 24 are formed on a transistor and a capacitor, that is, a silicon substrate 21. And forming a contact connected to the impurity bonding layer 23 on both sides of the word line 22, forming a bit line 26 on the first interlayer insulating film 24, and then forming a contact on the bit line 26. A second interlayer insulating film 27 is formed. Subsequently, the second interlayer insulating layer 27 and the first interlayer insulating layer 24 are selectively etched to form a capacitor contact 28 connected to the impurity bonding layer 23, and the front surface including the capacitor contact 28. A capacitor oxide film 29 is formed in the film. Subsequently, the capacitor oxide film 29 is selectively etched to form a capacitor 30 connected to the impurity bonding layer 23 through the capacitor contact 28, and then a third interlayer insulating film 31 is formed on the entire surface of the capacitor. After forming, the third interlayer insulating film 31 is planarized by a chemical mechanical polishing (CMP) process.

도 2에 도시된 바와 같이, 상기 제 3 층간절연막(31) 상에 알루미늄배선 접착층인 티타늄(32)과 제 1 티타늄질화막(33)을 증착하고, 후속 열처리를 실시한 다음, 상기 제 1 티타늄질화막(33) 상에 알루미늄(34) 및 제 2 티타늄질화막(35)을 증착한다. 이어 노광 공정 및 식각 공정을 실시하여 상기 티타늄(32), 제 1 티타늄질화막(33), 알루미늄(34), 제 2 티타늄질화막(35)으로 이루어진 제 1층 금속배선 (39a)을 형성한다.As shown in FIG. 2, titanium 32 and the first titanium nitride layer 33, which are aluminum wiring adhesive layers, are deposited on the third interlayer insulating layer 31, followed by subsequent heat treatment, and then the first titanium nitride layer ( The aluminum 34 and the second titanium nitride film 35 are deposited on 33. Subsequently, an exposure process and an etching process are performed to form a first layer metal wiring 39a including the titanium 32, the first titanium nitride layer 33, the aluminum 34, and the second titanium nitride layer 35.

도 3에 도시된 바와 같이, 상기 제 1층 금속배선(39a) 상에 제 1 산화막(36)을 형성한 다음, 상기 제 1 산화막(36) 상에 HSQ막(37)을 스핀코우터를 이용하여 코팅한다.As shown in FIG. 3, a first oxide film 36 is formed on the first layer metal wiring 39a, and then a spin coater is used as the HSQ film 37 on the first oxide film 36. To coat.

도 4에 도시된 바와 같이, 상기 HSQ막(37) 상에 수소이온의 이온주입을 실시하거나 큐어링시 N2/H2 분위기에서 큐어링을 실시하여 후속 비아식각시나 감광막제 거시 산소플라즈마에 의한 HSQ 박막(37) 내의 Si-H본드가 파괴되는 것을 방지한다.As shown in FIG. 4, ion implantation of hydrogen ions onto the HSQ membrane 37 or curing in an N 2 / H 2 atmosphere during curing is performed by subsequent via etching or macroscopic oxygen plasma photoresist. Si-H bond in the HSQ thin film 37 is prevented from being destroyed.

이어, 상기 HSQ막(37) 상에 제 2 산화막(38)을 증착하고 상기 제 2 산화막 (38) 상에 감광막을 도포하고 노광 및 현상 공정으로 패터닝한 다음, 상기 패터닝된 감광막을 마스크로 이용하여 상기 제 2 산화막(38), HSQ막(37), 제 1 산화막 (36)을 식각하여 일측 제 1층 금속배선(39a) 상에 비아홀을 형성한다. 여기서, 상기 비아홀 형성시 사용되는 가스는 통상 CF4, C2F6 등의 CF계 가스와 O 2 가스가 사용되고, 또한 감광막 제거시에도 O2 가스가 사용된다. 상기 HSQ막(37)은 Si-H 결합으로 인해 박막의 유전율을 낮추는데, 만약 산소 가스에 노출되면 Si-H 결합이 파괴되어 Si-O 결합을 형성하므로써 유전율이 증가하게 되는데, 상기 수소이온주입이나 N2/H2 분위기에서의 큐어링은 상기 Si-H 결합의 파괴를 방지한다.Subsequently, a second oxide film 38 is deposited on the HSQ film 37, a photoresist film is applied on the second oxide film 38, and patterned by an exposure and development process. Then, the patterned photoresist film is used as a mask. The second oxide film 38, the HSQ film 37, and the first oxide film 36 are etched to form via holes on one side first metal wiring 39a. Here, the via-hole gas used in the formation is usually from CF 4, C 2 F 6, etc. CF-based gas and O 2 gas is used for, and is also used by the O 2 gas, even when the photoresist removed. The HSQ film 37 lowers the dielectric constant of the thin film due to Si-H bonding. If exposed to oxygen gas, the dielectric constant is increased by breaking Si-H bonds to form Si-O bonds. Curing in an N 2 / H 2 atmosphere prevents breakage of the Si—H bonds.

이어 상기 비아홀을 포함한 전면에 알루미늄배선 접착층인 티타늄과 티타늄질화막을 증착하고 후속 열처리 공정을 실시한 다음 알루미늄막 및 티타늄질화막을 증착하여 노광 공정 및 식각 공정을 통하여 제 2층 금속배선(39b)을 형성한다.Subsequently, a titanium and titanium nitride film, which is an aluminum interconnect adhesive layer, is deposited on the entire surface including the via hole, followed by a subsequent heat treatment process, and then an aluminum film and a titanium nitride film are deposited to form a second layer metal wiring 39b through an exposure process and an etching process. .

여기서, 상기 HSQ막(37)의 수소 보호화(H2 Passivation) 방법에 대해 자세히 설명하면, 상기 HSQ막(37) 코팅후 코우터에서 80℃, 120℃, 180℃에서 각각 1∼2분 동안 베이킹한 다음, 노에서 열처리시 N2/H2 의 혼합가스 분위기에서 열처리를 실시한다. 이 때, N2/H2 의 혼합가스의 가스비는 20:1∼5:1이다.Here, the hydrogen protection method (H 2 Passivation) method of the HSQ film 37 will be described in detail, after coating the HSQ film 37 at the coater at 80 ℃, 120 ℃, 180 ℃ 1 to 2 minutes each After baking, the heat treatment is performed in a mixed gas atmosphere of N 2 / H 2 when the heat treatment in the furnace. At this time, the gas ratio of a gas mixture of N 2 / H 2 is 20: 1 to 5: 1.

또한, 다른 방법으로 HSQ막(37) 콘팅 후, 코우터에서의 베이킹을 거친다음, 노에서 질소(N2)가스 분위기에서 열처리하기 전이나 후에 이온주입기를 이용하여 수소(H2)이온을 주입한다. 여기서, 상기 노에서의 열처리시 온도는 350℃∼550℃이고, 10분∼60분 동안 실시되며, 상기 수소이온 주입시 이온주입에너지는 HSQ막(37)의 두께에 따라 30∼160keV 이고, 이온주입농도는 1014 ∼1016cm-3범위이다. In addition, after the HSQ film 37 is contacted by another method, after baking in a coater, hydrogen (H 2 ) ions are injected using an ion implanter before or after heat treatment in a nitrogen (N 2 ) gas atmosphere in a furnace. do. Here, the temperature during the heat treatment in the furnace is 350 ℃ to 550 ℃, it is carried out for 10 minutes to 60 minutes, the ion implantation energy is 30 ~ 160keV depending on the thickness of the HSQ membrane 37, the ion during hydrogen ion injection Injection concentrations range from 10 14 to 10 16 cm -3 .

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 HSQ박막의 실리콘-수소 결합의 파괴를 방지하여 유전율이 저하되는 것을 억제하므로써 층간절연막을 안정화시킬 수 있는 효과가 있다.The present invention described above has the effect of stabilizing the interlayer insulating film by preventing the breakdown of the dielectric constant by preventing the breakdown of the silicon-hydrogen bond of the HSQ thin film.

Claims (13)

반도체 소자의 제조 방법에 있어서,In the manufacturing method of a semiconductor element, 반도체 기판 상에 제 1층 금속배선을 형성하는 단계;Forming a first layer metal wiring on the semiconductor substrate; 상기 제 1층 금속배선 상에 HSQ 박막을 형성하는 단계;Forming an HSQ thin film on the first layer metallization; 상기 HSQ박막 표면에 수소원자를 주입시켜 수소에 의한 보호화를 실시하는 단계;Implanting a hydrogen atom on the surface of the HSQ thin film to perform protection by hydrogen; 감광막을 마스크로 이용하여 상기 HSQ박막을 선택적으로 식각하여 상기 제 1층 금속배선이 노출되는 비아홀을 형성하는 단계; Selectively etching the HSQ thin film using a photosensitive film as a mask to form via holes through which the first layer metal wiring is exposed; 상기 감광막을 제거하는 단계; 및Removing the photosensitive film; And 상기 비아홀을 통해 상기 제 1층 금속배선과 전기적으로 연결되는 제 2층 금속배선을 형성하는 단계Forming a second layer metal wiring electrically connected to the first layer metal wiring through the via hole; 를 포함하는 층간절연막의 형성 방법.Method of forming an interlayer insulating film comprising a. 제 1 항에 있어서,The method of claim 1, 상기 HSQ 박막을 형성하는 단계는,Forming the HSQ thin film, 상기 HSQ 박막을 스핀코팅한 후, 80℃, 120℃, 180℃에서 각각 1∼2분 동안 베이킹하여 이루어지는 것을 특징으로 하는 층간절연막의 형성 방법.And spin-coating the HSQ thin film, followed by baking at 80 ° C., 120 ° C., and 180 ° C. for 1 to 2 minutes, respectively. 제 1 항에 있어서,The method of claim 1, 상기 수소에 의한 보호화를 실시하는 단계는,The step of performing protection by the hydrogen, 수소이온주입에 의해 이루어짐을 특징으로 하는 층간절연막의 형성 방법.A method of forming an interlayer insulating film, which is made by hydrogen ion injection. 제 1 항에 있어서,The method of claim 1, 상기 수소에 의한 보호화를 실시하는 단계는,The step of performing protection by the hydrogen, 수소원자를 포함하는 분위기에서 열처리하여 이루어짐을 특징으로 하는 층간절연막의 형성 방법.A method of forming an interlayer insulating film, characterized in that the heat treatment in an atmosphere containing a hydrogen atom. 제 3 항에 있어서,The method of claim 3, wherein 상기 수소이온주입은 상기 HSQ 박막의 베이킹 전 또는 후에 실시하는 것을 특징으로 하는 층간절연막의 형성 방법.The hydrogen ion implantation is performed before or after baking the HSQ thin film. 제 3 항에 있어서,The method of claim 3, wherein 상기 수소이온의 이온주입에너지는 30keV∼160keV이며, 이온주입농도는 1×1014∼1×1016cm-3인 것을 특징으로 하는 층간절연막의 형성 방법. The ion implantation energy of the hydrogen ion is 30keV ~ 160keV, the ion implantation concentration is 1 × 10 14 ~ 1 × 10 16 cm -3 A method of forming an interlayer insulating film. 제 4 항에 있어서,The method of claim 4, wherein 상기 열처리는 상기 HSQ 박막의 베이킹후, N2/H2 분위기의 노(furnace)에서 이루어짐을 특징으로 하는 층간절연막의 형성 방법.The heat treatment is a method of forming an interlayer insulating film, characterized in that after the baking of the HSQ thin film, in a furnace (furnace) of N 2 / H 2 atmosphere. 제 7 항에 있어서,The method of claim 7, wherein 상기 N2/H2의 가스비는 20:1∼ 5:1인 것을 특징으로 하는 층간절연막의 형성 방법.The gas ratio of N 2 / H 2 is 20: 1 to 5: 1. 제 7 항에 있어서,The method of claim 7, wherein 상기 열처리는 350℃∼550℃에서 10분∼60분동안 실시되는 것을 특징으로 하는 층간절연막의 형성 방법.The heat treatment is performed for 10 to 60 minutes at 350 ° C to 550 ° C. 제 1 항에 있어서,The method of claim 1, 상기 제 1층 금속배선 및 제 2층 금속배선은 각각 티타늄, 제 1 티타늄질화막, 알루미늄 및 제 2 티타늄질화막의 적층구조로 이루어진 것을 특징으로 하는 층간절연막의 형성 방법.And wherein the first layer metal wiring and the second layer metal wiring have a laminated structure of titanium, a first titanium nitride film, aluminum, and a second titanium nitride film, respectively. 반도체 소자의 제조 방법에 있어서,In the manufacturing method of a semiconductor element, 반도체 기판 상에 제 1층 금속배선을 형성하는 단계;Forming a first layer metal wiring on the semiconductor substrate; 상기 제 1층 금속배선 상에 제 1 산화막을 형성하는 단계;Forming a first oxide film on the first layer metal wiring; 상기 제 1 산화막 상에 스핀온도포법으로 HSQ막을 형성하는 단계;Forming an HSQ film on the first oxide film by spin temperature foaming; 상기 HSQ막 상에 상기 HSQ막내의 실리콘-수소 결합의 파괴를 방지하기 위한 수소보호화를 실시하는 단계;Performing hydrogenation protection on the HSQ film to prevent breakage of silicon-hydrogen bonds in the HSQ film; 상기 수소 보호화된 HSQ막 상에 제 2 산화막을 형성하는 단계;Forming a second oxide film on the hydrogen protected HSQ film; 상기 제 2 산화막 상에 감광막을 도포하고 선택적으로 패터닝하는 단계;Applying and selectively patterning a photosensitive film on the second oxide film; 상기 패터닝된 감광막을 마스크로 하여 상기 제 2 산화막, HSQ막, 제 1 산화막을 식각하여 상기 제 1층 금속배선이 노출되는 비아홀을 형성하는 단계; 및Etching the second oxide film, the HSQ film, and the first oxide film using the patterned photoresist as a mask to form a via hole through which the first layer metal wiring is exposed; And 상기 비아홀을 통해 상기 제 1층 금속배선과 전기적으로 연결되는 제 2층 금속배선을 형성하는 단계Forming a second layer metal wiring electrically connected to the first layer metal wiring through the via hole; 를 포함하여 이루어짐을 특징으로 하는 층간절연막의 형성 방법.Method for forming an interlayer insulating film comprising a. 제 11 항에 있어서,The method of claim 11, 상기 HSQ막의 수소 보호화는, N2/H2 의 혼합가스 분위기에서 열처리하여 이루어지는 것을 특징으로 하는 층간절연막의 형성 방법.The hydrogenation protection of the HSQ film is performed by heat treatment in a mixed gas atmosphere of N 2 / H 2 . 제 11 항에 있어서,The method of claim 11, 상기 HSQ막의 수소보호화는, 수소 이온 주입에 의해 이루어지는 것을 특징으로 하는 층간절연막의 형성 방법Hydrogen protection of said HSQ film | membrane is performed by hydrogen ion implantation, The formation method of the interlayer insulation film characterized by the above-mentioned.
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