KR100609557B1 - Method for manufacturing transistor - Google Patents

Method for manufacturing transistor Download PDF

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KR100609557B1
KR100609557B1 KR1020000036917A KR20000036917A KR100609557B1 KR 100609557 B1 KR100609557 B1 KR 100609557B1 KR 1020000036917 A KR1020000036917 A KR 1020000036917A KR 20000036917 A KR20000036917 A KR 20000036917A KR 100609557 B1 KR100609557 B1 KR 100609557B1
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transistors
ions
phenyl
transistor
cell region
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KR20020002677A (en
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이상희
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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Abstract

본 발명은 NMOS 트랜지스터의 에스시이(Short Channel Effect : SCE) 방지와 핫 캐리어(Hot carrier) 발생 저하 및 PMOS 트랜지스터의 펀치 마진(Punch margin) 확보 등과 같은 주변 영역 트랜지스터의 최적화 그리고 셀 영역 트랜지스터의 리프레쉬(Refresh) 특성 증가를 위한 이온을 융합해서 이온 주입하므로 소자의 경제성 및 소자의 특성을 향상시키기 위한 트랜지스터의 제조 방법에 관한 것이다.According to the present invention, optimization of peripheral region transistors such as prevention of short channel effect (SCE) of NMOS transistors, reduction of hot carrier generation and securing of punch margin of PMOS transistors, and refresh of cell region transistors ( The present invention relates to a method of manufacturing a transistor for improving device economics and device characteristics by implanting ions for implantation to increase characteristics.

본 발명의 트랜지스터의 제조 방법은 NMOS 트랜지스터의 SCE 방지와 핫 캐리어 발생 저하 및 PMOS 트랜지스터의 펀치 마진 확보 등과 같은 주변 영역 트랜지스터의 최적화 그리고 셀 영역 트랜지스터의 리프레쉬 특성 증가를 위한 이온을 융합해서 이온 주입하므로, 공정 횟수를 종래보다 감소시키고, 전면의 제 2 페닐(Ph) 이온 주입 공정으로 셀 영역의 트랜지스터의 경우 종래보다 더 두꺼운 질화막에서 더 높은 에너지로 페닐 이온을 주입하기 때문에 전기장의 감소로 리프레쉬 특성을 향상시키고, 주변 영역의 PMOS 트랜지스터의 경우 페닐 이온의 농도를 증가시켜 펀치 마진을 증가시키는 등 소자 수율, 신뢰성 및 특성을 향상시키는 특징이 있다.Since the transistor manufacturing method of the present invention fuses ions for optimizing peripheral region transistors such as preventing SCE of NMOS transistors, reducing hot carrier generation and securing punch margin of PMOS transistors, and increasing refresh characteristics of cell region transistors, The number of processes is reduced compared to the conventional method, and in the case of transistors in the cell region, the phenyl ions are injected with higher energy in a thicker nitride film than in the prior art by the second phenyl (Ph) ion implantation process in the front, thereby improving the refresh characteristics by reducing the electric field. In the case of the PMOS transistor in the peripheral region, the device yield, reliability, and characteristics are improved by increasing the concentration of phenyl ions to increase the punch margin.

Description

트랜지스터의 제조 방법{Method for manufacturing transistor}Method for manufacturing transistor

도 1a 내지 도 1d는 종래 기술에 따른 트랜지스터의 제조 방법을 나타낸 공정 단면도1A to 1D are cross-sectional views illustrating a method of manufacturing a transistor according to the prior art.

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 트랜지스터의 제조 방법을 나타낸 공정 단면도2A through 2D are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

도 3은 NMOS 트랜지스터에서 페닐 이온에 비소 이온을 첨가한 불순물 영역과 비소 이온의 불순물 영역의 라이프 타임을 나타낸 측정 도면3 is a measurement chart showing the lifetimes of impurity regions in which arsenic ions are added to phenyl ions and impurity regions of arsenic ions in an NMOS transistor;

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

31: 반도체 기판 32: 필드 산화막31 semiconductor substrate 32 field oxide film

33: 제 1 p형 웰 34: n형 웰33: first p-type well 34: n-type well

35: 제 2 p형 웰 36: 게이트 산화막35: second p-type well 36: gate oxide film

37: 게이트 전극 38: 패드 산화막37: gate electrode 38: pad oxide film

39: 제 1 페닐 이온 40: 제 2 감광막39: first phenyl ion 40: second photosensitive film

41: 비소 이온 42: 질화막41: arsenic ion 42: nitride film

43: 제 2 페닐 이온43: second phenyl ion

본 발명은 트랜지스터의 제조 방법에 관한 것으로, 특히 각 트랜지스터의 특성을 최적화는 이온을 융합하여 이온 주입하므로 공정 횟수의 감소 및 소자의 수율, 신뢰성 및 특성을 향상시키는 트랜지스터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor, and more particularly, to a method of manufacturing a transistor that optimizes the characteristics of each transistor to fuse ions and implant ions, thereby reducing the number of processes and improving device yield, reliability, and characteristics.

NMOS 트랜지스터의 에스시이(Short Channel Effect : SCE)와 핫 캐리어(Hot carrier) 특성 개선 및 PMOS 트랜지스터의 펀치 마진(Punch margin) 확보 등과 같은 주변 영역 트랜지스터의 최적화 그리고 셀(Cell) 영역 트랜지스터의 리프레쉬(Refresh) 특성 개선은 제품 개발을 위해 필요하다.Optimization of peripheral region transistors such as improvement of short channel effect (SCE) and hot carrier characteristics of NMOS transistors and securing punch margin of PMOS transistors, and refresh of cell region transistors Characteristic improvement is necessary for product development.

상기 셀 영역 트랜지스터의 리프레쉬 특성은 상기 셀 영역 전면에 형성되는 질화막의 두께에 따라 영향을 받는다.The refresh characteristic of the cell region transistor is affected by the thickness of the nitride film formed on the entire cell region.

즉, 40 ∼ 60Å두께의 질화막이 형성된 상태에서 상기 셀 영역 전면에 엘디디(Lightly Doped Drain : LDD) 이온 주입 공정보다 240 ∼ 260Å두께의 질화막이 형성된 상태에서의 LDD 이온 주입 공정이 프로파일(Profile)의 변화에 따른 전기장의 감소로 상기 셀 영역 트랜지스터의 리프레쉬 특성을 향상시킨다.That is, a LDD ion implantation process in which a nitride film having a thickness of 240 to 260 Å is formed over a lightly doped drain (LDD) ion implantation process in a state where a nitride film having a thickness of 40 to 60 Å is formed is a profile. The refreshing characteristic of the cell region transistor is improved by reducing the electric field according to the change of.

그리고, 상기 PMOS 트랜지스터의 펀치 마진은 버리드 채널(Buried Channel)의 한계를 결정한다.In addition, the punch margin of the PMOS transistor determines a limit of a buried channel.

종래의 트랜지스터의 제조 방법은 도 1a에서와 같이, 상기 반도체 기판(11)상의 격리 영역에 일반적인 에스티아이(Shallow Trench Isolation : STI) 방법에 의해 필드 산화막(12)을 형성한다.In the conventional method of manufacturing a transistor, as shown in FIG. 1A, the field oxide film 12 is formed by a typical shallow trench isolation (STI) method in an isolation region on the semiconductor substrate 11.

그리고, 상기 반도체 기판(11) 표면내의 소정 영역에 이온 주입 공정 등을 사용하여 선택적으로 불순물을 주입하고, 드라이브 인 확산을 통해 상기 셀(Cell) 영역의 반도체 기판(11) 표면내에 제 1 n형 웰(13)과 주변 영역의 반도체 기판(11) 표면내에 p형 웰(14)과 제 2 n형 웰(15)을 각각 형성한다.In addition, impurities are selectively implanted into a predetermined region in the surface of the semiconductor substrate 11 using an ion implantation process, and the like, and a first n-type type is formed in the surface of the semiconductor substrate 11 in the cell region through drive-in diffusion. The p-type well 14 and the second n-type well 15 are formed in the well 13 and the surface of the semiconductor substrate 11 in the peripheral region, respectively.

이어 상기 필드 산화막(12)을 포함한 전면에 열 산화 공정으로 제 1 산화막을 성장시킨 후, 상기 제 1 산화막상에 다결정 실리콘층과 제 1 감광막을 형성한 후, 상기 제 1 감광막을 게이트 전극이 형성될 부위에만 남도록 선택적으로 노광 및 현상한 다음, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 사용하여 상기 다결정 실리콘층과 제 1 산화막을 선택적으로 식각하고, 상기 제 1 감광막을 제거한다.Subsequently, after the first oxide film is grown on the entire surface including the field oxide film 12 by a thermal oxidation process, a polycrystalline silicon layer and a first photosensitive film are formed on the first oxide film, and then a gate electrode is formed on the first photosensitive film. After selectively exposing and developing so that only a portion to be left is left, the polycrystalline silicon layer and the first oxide layer are selectively etched using the selectively exposed and developed first photoresist film as a mask, and the first photoresist film is removed.

여기서, 상기 제 1 산화막의 선택적 식각으로 게이트 산화막(16)을 형성하며 상기 다결정 실리콘층의 선택적 식각으로 다수개의 게이트 전극(17)들을 형성한다.Here, the gate oxide layer 16 is formed by selective etching of the first oxide layer, and the plurality of gate electrodes 17 are formed by selective etching of the polycrystalline silicon layer.

도 1b에서와 같이, 상기 게이트 전극(17)과 게이트 산화막(16)을 포함한 전면에 제 2 감광막(18)을 도포한 후, 상기 제 2 감광막(18)을 상기 제 1 n형 웰(13)의 상부에만 제거 되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1B, after the second photosensitive film 18 is coated on the entire surface including the gate electrode 17 and the gate oxide film 16, the second photosensitive film 18 is applied to the first n-type well 13. It is selectively exposed and developed so as to be removed only at the top.

그리고, 상기 선택적으로 노광 및 현상된 제 2 감광막(18)을 마스크로 셀 영역 트랜지스터의 리프레쉬 특성 개선을 위한 이온 주입 공정을 전면에 진행한다.Then, an ion implantation process for improving the refresh characteristics of the cell region transistor is performed on the entire surface by using the selectively exposed and developed second photosensitive film 18 as a mask.

도 1c에서와 같이, 상기 제 2 감광막(18)을 제거하고, 상기 게이트 전극(17)을 포함한 전면에 제 3 감광막(19)을 도포한 후, 상기 제 3 감광막(19)을 상기 p형 웰(14)의 상부에만 제거 되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1C, after removing the second photoresist film 18 and applying a third photoresist film 19 to the entire surface including the gate electrode 17, the third photoresist film 19 is applied to the p-type well. It is selectively exposed and developed so as to be removed only on the upper portion of (14).

그리고, 상기 선택적으로 노광 및 현상된 제 3 감광막(19)을 마스크로 주변 영역의 트랜지스터 중 NMOS 트랜지스터의 SCE 또는 핫 캐리어 특성 개선을 위한 이온 주입 공정을 전면에 진행한다.In addition, an ion implantation process for improving SCE or hot carrier characteristics of the NMOS transistor among the transistors in the peripheral area is performed on the entire surface using the selectively exposed and developed third photoresist layer 19 as a mask.

도 1d에서와 같이, 상기 제 3 감광막(19)을 제거하고, 상기 게이트 전극(17)을 포함한 전면에 제 4 감광막(20)을 도포한 후, 상기 제 4 감광막(20)을 상기 제 2 n형 웰(15)의 상부에만 제거 되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1D, after removing the third photoresist film 19 and applying the fourth photoresist film 20 to the entire surface including the gate electrode 17, the fourth photoresist film 20 is applied to the second n. It is selectively exposed and developed to be removed only on the upper part of the mold well 15.

그리고, 상기 선택적으로 노광 및 현상된 제 4 감광막(20)을 마스크로 주변 영역의 트랜지스터 중 PMOS 트랜지스터의 펀치 마진 확보를 위한 이온 주입 공정을 전면에 진행한다.Then, the ion implantation process for securing the punch margin of the PMOS transistor among the transistors in the peripheral area is performed on the entire surface by using the selectively exposed and developed fourth photoresist film 20 as a mask.

그러나 종래의 트랜지스터의 제조 방법은 셀 영역과 주변 영역의 트랜지스터들을 각각 최적화 하여 주변 영역 트랜지스터의 최적화 그리고 셀 영역 트랜지스터의 리프레쉬 특성을 개선하므로 다음과 같은 문제점이 있었다.However, the conventional transistor manufacturing method has the following problems because the transistors in the cell region and the peripheral region are optimized to improve the optimization of the peripheral region transistor and the refresh characteristics of the cell region transistor.

첫째, 감광막 공정 및 주입 공정 횟수의 증가와 같이 공정이 복잡하여 소자의 경제성이 저하된다.First, the process is complicated, such as the increase in the number of photoresist process and implantation process, and the economic efficiency of the device is lowered.

둘째, 주변 영역의 NMOS 트랜지스터는 먼저 비소(As) 이온만으로 LDD 이온 주입 공정을 할 경우 형성되는 샤프(Sharp)한 불순물 영역으로 핫 캐리어 특성이 증가되고 또한 페닐(Ph) 이온만으로 LDD 이온 주입 공정을 할 경우 불순물 영역의 면적이 증가하여 SCE에 의한 펀치 마진이 저하되기 때문에, 주변 영역의 NMOS 트랜지스터 경우 SCE와 핫 캐리어 특성을 동시에 최적화 할 수 없어 소자의 특성이 저하된다. Second, the NMOS transistor in the peripheral region is a sharp impurity region formed when the LDD ion implantation process is performed only with arsenic (As) ions, and the hot carrier characteristics are increased, and the LDD ion implantation process is performed only with phenyl (Ph) ions. In this case, since the area of the impurity region is increased and the punch margin is reduced by SCE, the characteristics of the device are deteriorated because the NMOS transistors in the peripheral region cannot simultaneously optimize the SCE and hot carrier characteristics.                         

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 NMOS 트랜지스터의 SCE 방지와 핫 캐리어 발생 저하 및 PMOS 트랜지스터의 펀치 마진 확보 등과 같은 주변 영역 트랜지스터의 최적화 그리고 셀 영역 트랜지스터의 리프레쉬 특성 증가를 위한 이온을 융합해서 이온 주입하므로 소자의 경제성 및 소자의 특성을 향상시키는 트랜지스터의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. Fusion of ions for optimizing peripheral region transistors such as preventing SCE of NMOS transistors, reducing hot carrier generation and securing punch margins for PMOS transistors, and increasing the refresh characteristics of cell region transistors. Therefore, the object of the present invention is to provide a method for manufacturing a transistor that improves the economics and characteristics of the device because of ion implantation.

본 발명의 트랜지스터의 제조 방법은 셀 영역과 주변 영역이 각각 정의된 기판을 마련하는 단계, 상기 셀 영역의 기판 표면내에 제 1 도전형 제 1 웰을 형성하고, 상기 주변 영역의 기판 표면내에 제 2 도전형 제 2 웰과 제 1 도전형 제 3웰을 이웃하여 형성하는 단계, 상기 각각의 제 1, 제 2, 제 3 웰의 기판상에 게이트 절연막을 개재한 게이트 전극들을 형성하는 단계, 상기 게이트 전극들을 포함한 반도체 기판상에 제 1 절연막을 형성하고 제 1 페닐 이온을 주입하는 단계, 상기 제 2 웰의 기판에 비소 이온을 주입하는 단계, 상기 제 1 절연막을 제거하는 단계 및 상기 게이트 전극을 포함한 반도체 기판상에 상기 제 1 절연막보다 두께가 두꺼운 제 2 절연막을 형성하고 제 2 페닐 이온을 상기 제 1 페닐 이온(39) 주입 공정보다 높은 에너지로 주입하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a transistor of the present invention comprises the steps of providing a substrate having a cell region and a peripheral region defined therein, forming a first conductivity type first well in a substrate surface of the cell region, and a second in the substrate surface of the peripheral region. Forming a conductive second well and a first conductive third well adjacent to each other, forming gate electrodes on a substrate of each of the first, second, and third wells through a gate insulating film; Forming a first insulating film on a semiconductor substrate including electrodes and implanting first phenyl ions, implanting arsenic ions into the substrate of the second well, removing the first insulating film, and including the gate electrode Forming a second insulating film thicker than the first insulating film on the semiconductor substrate and injecting second phenyl ions with a higher energy than the first phenyl ion 39 implantation process; It is characterized by consisting of.

상기와 같은 본 발명에 따른 트랜지스터의 제조 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a transistor according to the present invention as follows.

도 2a 내지 도 2d는 본 발명의 실시 예에 따른 트랜지스터의 제조 방법을 나타낸 공정 단면도이거, 도 3은 NMOS 트랜지스터에서 페닐 이온에 비소 이온을 첨가 한 불순물 영역과 비소 이온의 불순물 영역의 라이프 타임을 나타낸 측정 도면이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a transistor according to an exemplary embodiment of the present invention, and FIG. 3 illustrates a lifetime of impurity regions in which arsenic ions are added to phenyl ions and impurity regions of arsenic ions in an NMOS transistor. It is a measurement drawing.

본 발명의 실시 예에 따른 트랜지스터의 제조 방법은 도 2a에서와 같이, 반도체 기판(31)상의 격리 영역에 일반적인 STI 방법에 의해 필드 산화막(32)을 형성한다.In the method of manufacturing a transistor according to the exemplary embodiment of the present invention, as shown in FIG. 2A, the field oxide layer 32 is formed in the isolation region on the semiconductor substrate 31 by a general STI method.

그리고, 상기 반도체 기판(31) 표면내의 셀 영역에 이온 주입 공정을 이용하여 선택적으로 불순물을 주입하고, 드라이브 인 확산을 통해 제 1 n형 웰(33) 및 상기 반도체 기판(31) 표면내의 주변 영역에 p형 웰(34)과 제 2 n형 웰(35)을 각각 형성한다.In addition, impurities are selectively implanted into a cell region within the surface of the semiconductor substrate 31 using an ion implantation process, and a peripheral region within the surface of the first n-type well 33 and the semiconductor substrate 31 through drive-in diffusion. The p-type wells 34 and the second n-type wells 35 are formed in each.

이어 상기 필드 산화막(32)을 포함한 전면에 열 산화 공정으로 제 1 산화막을 성장시킨 후, 상기 제 1 산화막상에 다결정 실리콘층과 제 1 감광막을 형성한 후, 상기 제 1 감광막을 게이트 전극이 형성될 부위에만 남도록 선택적으로 노광 및 현상한 다음, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 사용하여 상기 다결정 실리콘층과 제 1 산화막을 선택적으로 식각하고, 상기 제 1 감광막을 제거한다.Subsequently, after the first oxide film is grown on the entire surface including the field oxide film 32 by a thermal oxidation process, a polycrystalline silicon layer and a first photosensitive film are formed on the first oxide film, and then a gate electrode is formed on the first photosensitive film. After selectively exposing and developing so that only a portion to be left is left, the polycrystalline silicon layer and the first oxide layer are selectively etched using the selectively exposed and developed first photoresist film as a mask, and the first photoresist film is removed.

여기서, 상기 제 1 산화막의 선택적 식각으로 게이트 산화막(36)을 형성하며 상기 다결정 실리콘층의 선택적 식각으로 다수개의 게이트 전극(37)들을 형성한다.Here, the gate oxide layer 36 is formed by selective etching of the first oxide layer, and the plurality of gate electrodes 37 are formed by selective etching of the polycrystalline silicon layer.

도 2b에서와 같이, 상기 게이트 전극(37)들을 포함한 전면에 40 ∼ 50Å 두께의 패드(Pad) 산화막(38)을 형성한 후, 제 1 페닐 이온(39)을 주입한다.As shown in FIG. 2B, after forming a pad oxide film 38 having a thickness of 40 to 50 에 on the entire surface including the gate electrodes 37, the first phenyl ion 39 is implanted.

이때, 상기 패드 산화막(38) 대신에 질화막으로 형성할 수 있으며, 상기 제 1 페닐 이온(39)은 PMOS 트랜지스터의 펀치 마진용 이온으로서 상기 셀 영역에 형성될 NMOS 트랜지스터의 리프레쉬 특성 저하 방지와 상기 주변 영역에 형성될 NMOS 트랜지스터의 숏 채널 효과 방지를 위해 저농도로 주입한다.In this case, the pad oxide layer 38 may be formed of a nitride layer, and the first phenyl ion 39 may be a punch margin ion of a PMOS transistor, thereby preventing a decrease in refresh characteristics of an NMOS transistor to be formed in the cell region and the peripheral area. In order to prevent the short channel effect of the NMOS transistor to be formed in the region is injected at a low concentration.

특히, 상기 주변 영역에 형성될 NMOS 트랜지스터에서 비소(As) 이온만으로 LDD 이온 주입 공정을 한 경우의 문턱 전압의 롤-오프(Roll-off) 특성이 되도록 채널 영역에 영향을 미치지 않는 범위에서 상기 제 1 페닐 이온(39)을 주입하므로 도 3에서와 같이 상기 제 1 페닐 이온(39)에 비소 이온을 첨가한 불순물 영역이 비소 이온만의 불순물 영역보다 라이프 타임(Hot carrier life time)이 커지게 된다.Particularly, in the NMOS transistor to be formed in the peripheral region, the first voltage is formed in a range that does not affect the channel region so as to become a roll-off characteristic of the threshold voltage when the LDD ion implantation process is performed using only arsenic (As) ions. Since one phenyl ion 39 is implanted, as shown in FIG. 3, the impurity region in which arsenic ions are added to the first phenyl ion 39 becomes longer than the impurity region of only arsenic ions. .

도 2c에서와 같이, 상기 게이트 전극(37)을 포함한 전면에 제 2 감광막(40)을 도포한 후, 상기 제 2 감광막(40)을 상기 n형 웰(34)의 상부에만 제거되도록 선택적으로 노광 및 현상한 다음, 상기 선택적으로 노광 및 현상된 제 2 감광막(40)을 마스크로 이용하여 숏 채널 효과 방지를 위한 비소(As) 이온(41)을 주입한다.As shown in FIG. 2C, after applying the second photoresist film 40 to the entire surface including the gate electrode 37, the second photoresist film 40 is selectively exposed to be removed only on the n-type well 34. And developing, and then implanting arsenic (As) ions 41 to prevent the short channel effect by using the selectively exposed and developed second photoresist layer 40 as a mask.

도 2d에서와 같이, 상기 제 2 감광막(40)과 패드 산화막(38)을 제거하고, 게이트 전극(37)을 포함한 반도체 기판(31)상에 100 ∼ 200Å 두께의 질화막(42)을 형성하고, 상기 제 1 페닐 이온(39) 주입 공정보다 높은 에너지로 제 2 페닐 이온(43)을 주입한다.As shown in FIG. 2D, the second photosensitive film 40 and the pad oxide film 38 are removed, and a nitride film 42 having a thickness of 100 to 200 Å is formed on the semiconductor substrate 31 including the gate electrode 37. The second phenyl ion 43 is implanted with higher energy than the first phenyl ion 39 implantation process.

이때, 상기 제 2 페닐 이온(43)의 이온 주입 공정으로 상기 제 1 페닐 이온(39)의 주입 공정 시 상기 주변 영역에 형성될 PMOS 트랜지스터의 페닐 이온 도즈(Dose) 량의 부족을 보상하여 펀치 마진을 확보한다.At this time, a punch margin is compensated for the lack of the amount of phenyl ion dose of the PMOS transistor to be formed in the peripheral region during the implantation process of the first phenyl ions 39 by the ion implantation process of the second phenyl ions 43. To secure.

또한, 종래 기술보다 더 두꺼운 두께의 질화막(42)에서 높은 이온 주입 에너 지(Energy)로 상기 제 2 페닐 이온(43)을 이온 주입하므로 전기장이 감소하여 상기 셀 영역에 형성될 NMOS 트랜지스터의 리프레쉬 특성 저하 방지를 방지한다.In addition, since the second phenyl ions 43 are implanted with a high ion implantation energy in the nitride film 42 having a thicker thickness than that of the related art, an electric field is reduced to refresh the NMOS transistors to be formed in the cell region. To prevent degradation.

상술한 본 발명에 있어서 상기 제 2 페닐 이온(43)의 이온 주입 공정으로 상기 주변 영역에 형성될 PMOS 트랜지스터의 펀치 마진이 확보될 경우에는 상기 제 1 페닐 이온(39)의 이온 주입 공정을 생략한다.In the present invention described above, when the punch margin of the PMOS transistor to be formed in the peripheral region is secured by the ion implantation process of the second phenyl ion 43, the ion implantation process of the first phenyl ion 39 is omitted. .

그리고, 상기 주변 영역에 형성될 NMOS 트랜지스터의 SCE를 저하시키기 위해 Ph+As+Ph LDD 대신에 Ph+Ge+Ph LDD 또는 Ph+Sn+Ph LDD로 형성할 수 있다.In addition, in order to lower the SCE of the NMOS transistor to be formed in the peripheral region, Ph + Ge + Ph LDD or Ph + Sn + Ph LDD may be formed instead of Ph + As + Ph LDD.

본 발명의 트랜지스터의 제조 방법은 NMOS 트랜지스터의 SCE 방지와 핫 캐리어 발생 저하 및 PMOS 트랜지스터의 펀치 마진 확보 등과 같은 주변 영역 트랜지스터의 최적화 그리고 셀 영역 트랜지스터의 리프레쉬 특성 증가를 위한 이온을 융합해서 이온 주입하므로, 공정 횟수를 종래보다 감소시키고, 전면의 제 2 페닐 이온 주입 공정으로 셀 영역의 트랜지스터의 경우 종래보다 더 두꺼운 질화막에서 더 높은 에너지로 페닐 이온을 주입하기 때문에 전기장의 감소로 리프레쉬 특성을 향상시키고, 주변 영역의 PMOS 트랜지스터의 경우 페닐 이온의 농도를 증가시켜 펀치 마진을 증가시키는 등 소자 수율, 신뢰성 및 특성을 향상시키는 효과가 있다.
Since the transistor manufacturing method of the present invention fuses ions for optimizing peripheral region transistors such as preventing SCE of NMOS transistors, reducing hot carrier generation and securing punch margin of PMOS transistors, and increasing refresh characteristics of cell region transistors, The number of processes is reduced compared to the conventional method, and in the case of transistors in the cell region, the phenyl ions are injected with higher energy in a thicker nitride film than in the case of the transistors in the cell region, thereby improving the refresh characteristics by reducing the electric field. In the case of the PMOS transistors in the region, there is an effect of improving device yield, reliability, and characteristics such as increasing the punch margin by increasing the concentration of phenyl ions.

Claims (3)

셀 영역과 주변 영역이 각각 정의된 기판을 마련하는 단계;Providing a substrate in which a cell region and a peripheral region are defined respectively; 상기 셀 영역의 기판 표면내에 제 1 도전형 제 1 웰을 형성하고, 상기 주변 영역의 기판 표면내에 제 2 도전형 제 2 웰과 제 1 도전형 제 3웰을 이웃하여 형성하는 단계;Forming a first conductivity type first well in a substrate surface of the cell region, and forming a second conductivity type second well and a first conductivity type third well adjacent to the substrate surface of the peripheral region; 상기 각각의 제 1, 제 2, 제 3 웰의 기판상에 게이트 절연막을 개재한 게이트 전극들을 형성하는 단계;Forming gate electrodes on the substrate of each of the first, second, and third wells with a gate insulating film interposed therebetween; 상기 게이트 전극들을 포함한 반도체 기판상에 제 1 절연막을 형성하고 제 1 페닐 이온을 주입하는 단계;Forming a first insulating film on the semiconductor substrate including the gate electrodes and implanting first phenyl ions; 상기 제 2 웰의 기판에 비소 이온을 주입하는 단계;Implanting arsenic ions into the substrate of the second well; 상기 제 1 절연막을 제거하는 단계;Removing the first insulating film; 상기 게이트 전극을 포함한 반도체 기판상에 상기 제 1 절연막보다 두께가 두꺼운 제 2 절연막을 형성하고 제 2 페닐 이온을 상기 제 1 페닐 이온(39) 주입 공정보다 높은 에너지로 주입하는 단계를 포함하여 이루어짐을 특징으로 하는 트랜지스터의 제조 방법.Forming a second insulating film thicker than the first insulating film on the semiconductor substrate including the gate electrode and implanting second phenyl ions with a higher energy than the first phenyl ion 39 implantation process. A method of manufacturing a transistor. 제 1 항에 있어서,The method of claim 1, 상기 제 1 절연막을 40 ∼ 50Å 두께로 형성함을 특징으로 하는 트랜지스터의 제조 방법.The first insulating film is formed to a thickness of 40 to 50 kHz, the transistor manufacturing method. 제 1 항에 있어서,The method of claim 1, 상기 제 2 절연막을 100 ∼ 200Å 두께로 형성함을 특징으로 하는 트랜지스터의 제조 방법.And the second insulating film is formed to a thickness of 100 to 200 kHz.
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