KR100608367B1 - Method for fabricating metal line - Google Patents

Method for fabricating metal line Download PDF

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KR100608367B1
KR100608367B1 KR1020040057316A KR20040057316A KR100608367B1 KR 100608367 B1 KR100608367 B1 KR 100608367B1 KR 1020040057316 A KR1020040057316 A KR 1020040057316A KR 20040057316 A KR20040057316 A KR 20040057316A KR 100608367 B1 KR100608367 B1 KR 100608367B1
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South Korea
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film
forming
metal
metal wiring
contact hole
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KR1020040057316A
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Korean (ko)
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KR20060008432A (en
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김춘환
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

본 발명은 금속배선의 형성방법에 관해 개시한 것으로서, 제 1금속배선을 구비한 반도체기판을 제공하는 단계와, 기판 상에 상기 제 1금속배선의 일부위를 노출시키는 제 1콘택홀을 가진 제 1절연막을 형성하는 단계와, 제 1콘택홀을 포함한 기판 전면에 제 1베리어금속막 및 제 1금속막을 차례로 형성하는 단계와, 제 1절연막이 노출되는 시점까지 상기 제 2금속막 및 제 2베리어금속막을 전면 식각하여 제 1콘택홀을 매립시키는 제 1플러그를 형성하는 단계와, 제 1층간절연막 상에 상기 제 1플러그와 연결되는 제 2금속배선을 형성하는 단계와, 제 2금속배선을 포함한 기판 전면에 충전막을 형성하는 단계와, 충전막에 열처리를 실시하여 평탄화하는 단계와, 평탄화된 충전막을 선택식각하여 상기 제 2금속배선의 일부위를 노출시키는 제 2콘택홀을 형성하는 단계와, 제 2콘택홀을 포함한 기판 전면에 제 2베리어금속막 및 제 2금속막을 차례로 형성하는 단계와, 충전막이 노출되는 시점까지 상기 제 2금속막 및 제 2베리어금속막을 전면 식각하여 제 2콘택홀을 매립시키는 제 2플러그를 형성하는 단계와, 충전막 상에 상기 제 2플러그와 연결되는 제 3금속배선을 형성하는 단계를 포함한다.Disclosed is a method of forming a metal wiring, comprising: providing a semiconductor substrate having a first metal wiring; and having a first contact hole exposing a portion of the first metal wiring on the substrate. Forming an insulating film, sequentially forming a first barrier metal film and a first metal film on the entire surface of the substrate including the first contact hole, and forming the second metal film and the second barrier until the first insulating film is exposed. Forming a first plug to fill the first contact hole by etching the metal layer on the entire surface, forming a second metal wiring connected to the first plug on the first interlayer insulating film, and including the second metal wiring; Forming a filling film on the entire surface of the substrate, performing a heat treatment on the filling film to planarize, and forming a second contact hole exposing a portion of the second metal wiring by selectively etching the planarized filling film. Forming a second barrier metal film and a second metal film on the entire surface of the substrate including the second contact hole; and sequentially etching the second metal film and the second barrier metal film until the filling film is exposed. Forming a second plug to fill the contact hole; and forming a third metal wiring connected to the second plug on the filling layer.

Description

금속배선의 형성방법{METHOD FOR FABRICATING METAL LINE}METHOD FOR FABRICATING METAL LINE}

도 1은 종래기술에 따른 문제점을 설명하기 위한 사진.1 is a photograph for explaining the problem according to the prior art.

도 2a 내지 도 2e는 본 발명에 따른 금속배선의 형성방법을 설명하기 위한 공정단면도.2A through 2E are cross-sectional views illustrating a method of forming a metal wiring according to the present invention.

본 발명은 금속배선의 형성방법에 관한 것으로서, 보다 구체적으로는 다층 배선의 평탄도를 향상시켜 금속배선 간의 브릿지(bridge)를 방지할 수 있는 금속배선의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming metal wirings, and more particularly, to a method of forming metal wirings that can improve the flatness of a multilayer wiring to prevent bridges between metal wirings.

디램(DRAM)소자가 고집적화됨에 따라 소자의 속도(speed)를 향상시키기 위해서는 2층 금속배선 구조에서 3층 또는 그 이상의 다층 금속배선 구조로의 전환이 필요하다. 일반적으로 다층 금속배선 구조에서는 속도 개선을 위하여 일정 수치 이하의 면저항을 가져야 하며, 특히 최하층의 제 1금속배선의 면저항이 제 2및 제 3금속배선의 면저항보다도 커야 한다. 또한, 제 1금속배선의 두께보다는 제 2및 제 3금속배선의 증착두께를 증가시켜야 한다. As DRAM devices are highly integrated, it is necessary to switch from a two-layer metal wiring structure to a three-layer or more multilayer metal wiring structure in order to improve the speed of the device. In general, the multilayer metal wiring structure should have a sheet resistance of less than a certain value in order to improve the speed, and in particular, the sheet resistance of the first metal wiring of the lowermost layer should be larger than the sheet resistance of the second and third metal wirings. In addition, it is necessary to increase the deposition thickness of the second and third metal wirings rather than the thickness of the first metal wirings.

도 1은 종래기술에 따른 문제점을 설명하기 위한 사진이다.1 is a photograph for explaining the problem according to the prior art.

따라서, 종래의 기술에서는 층간절연막 상에 베리어금속막을 개재시켜 제 2금속배선(b)을 형성함으로써, 결과적으로 제 2금속배선(b)의 증착두께가 두껍게 되어 금속배선 간의 단차가 증가되며, 후속의 공정에서 진행되는 층간절연막 평탄화 공정이 불량해지게 된다.(B참조) 여기서, 제 2금속배선(b)과 제 3금속배선(c) 간의 층간절연막으로는 SOG(Spin On Glass)막을 사용하여 평탄도를 개선하나, SOG막의 두께를 6000Å이상으로 증가할 경우 크랙(crack)이 발생된다.Therefore, in the related art, the second metal wiring b is formed by interposing a barrier metal film on the interlayer insulating film, and as a result, the deposition thickness of the second metal wiring b becomes thick, resulting in an increase in the step height between the metal wirings. The planarization of the interlayer insulating film, which is performed in the process of, becomes poor (see B). Here, a SOG (Spin On Glass) film is used as the interlayer insulating film between the second metal wiring (b) and the third metal wiring (c). Although flatness is improved, cracks are generated when the thickness of the SOG film is increased to 6000 GPa or more.

한편, 상기 층간절연막의 평탄화 불량은 후속에 진행되는 금속배선 형성 공정 중 전면식각 공정 시에 레지듀(residue)(A)가 발생하여 금속배선 간의 브릿지를 유발시키는 문제점이 있다.On the other hand, the planarization failure of the interlayer insulating film has a problem that a residue (A) occurs during the entire surface etching process during the subsequent metal wiring forming process to cause a bridge between the metal wiring.

따라서, 상기 문제점을 해결하고자, 본 발명의 목적은 다중 금속배선의 평탄화도를 향상시켜 금속배선 간의 브릿지를 방지할 수 있는 금속배선의 형성방법을 제공하려는 것이다.Accordingly, to solve the above problems, an object of the present invention is to provide a method for forming a metal wiring that can prevent the bridge between the metal wiring by improving the flattening degree of the multiple metal wiring.

(실시예)(Example)

상기 목적을 달성하고자, 본 발명에 따른 금속배선의 형성방법은 제 1금속배선을 구비한 반도체기판을 제공하는 단계와, 기판 상에 상기 제 1금속배선의 일부위를 노출시키는 제 1콘택홀을 가진 제 1절연막을 형성하는 단계와, 제 1콘택홀을 포함한 기판 전면에 제 1베리어금속막 및 제 1금속막을 차례로 형성하는 단계와, 제 1절연막이 노출되는 시점까지 상기 제 1금속막 및 제 1베리어금속막을 전면 식각하여 제 1콘택홀을 매립시키는 제 1플러그를 형성하는 단계와, 제 1층간절연막 상에 상기 제 1플러그와 연결되는 제 2금속배선을 형성하는 단계와, 제 2금속배선을 포함한 기판 전면에 충전막을 형성하는 단계와, 충전막에 열처리를 실시하여 평탄화하는 단계와, 평탄화된 충전막을 선택식각하여 상기 제 2금속배선의 일부위를 노출시키는 제 2콘택홀을 형성하는 단계와, 제 2콘택홀을 포함한 기판 전면에 제 2베리어금속막 및 제 2금속막을 차례로 형성하는 단계와, 충전막이 노출되는 시점까지 상기 제 2금속막 및 제 2베리어금속막을 전면 식각하여 제 2콘택홀을 매립시키는 제 2플러그를 형성하는 단계와, 충전막 상에 상기 제 2플러그와 연결되는 제 3금속배선을 형성하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, a method of forming a metal wiring according to the present invention comprises the steps of providing a semiconductor substrate having a first metal wiring, and a first contact hole for exposing a portion of the first metal wiring on the substrate; Forming a first insulating film having a first insulating film, sequentially forming a first barrier metal film and a first metal film on the entire surface of the substrate including the first contact hole, and forming the first metal film and the first metal film until the first insulating film is exposed. Etching the first barrier metal layer to form a first plug to fill the first contact hole; forming a second metal wiring connected to the first plug on the first interlayer insulating layer; Forming a filling film on the entire surface of the substrate, and performing planarization by performing heat treatment on the filling film, and selectively etching the planarized filling film to expose a portion of the second metal wiring. Forming a second barrier metal film and a second metal film on the entire surface of the substrate including the second contact hole, and etching the entire surface of the second metal film and the second barrier metal film until the charge film is exposed. And forming a second plug to fill the second contact hole, and forming a third metal wiring connected to the second plug on the filling film.

상기 충전막은 SOG를 이용하여 4000∼5000Å두께로 형성한다.The said filling film is formed in 4000-5000 micrometers thickness using SOG.

상기 열처리공정은 400∼500℃ 온도에서 30분∼1시간동안 진행한다.The heat treatment process is performed for 30 minutes to 1 hour at 400 ~ 500 ℃ temperature.

이하, 첨부된 도면을 참고로 하여 본 발명에 따른 금속배선의 형성방법을 설명하기로 한다.Hereinafter, a method of forming a metal wiring according to the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명에 따른 금속배선의 형성방법을 설명하기 위한 공정단면도이다.2A through 2E are cross-sectional views illustrating a method of forming a metal wiring according to the present invention.

본 발명에 따른 금속배선의 형성방법은, 도 2a에 도시된 바와 같이, 소정의 하부구조를 가진 반도체기판(1) 상에 제 1층간절연막(3)을 형성하고 나서, 상기 제 1층간절연막을 선택 식각하여 상기 기판의 일부위를 노출시키는 제1콘택홀(4)을 형성한다. 이어, 상기 제1콘택홀(4)을 포함한 기판 전면에 제 1금속막(미도시)을 형성하고 나서, 상기 제 1금속막을 식각하여 제 1콘택홀(4)을 덮는 제 1금속배선(7) 을 형성한다. 그런다음, 상기 제 1금속배선(7)을 포함한 기판 상에 제 2층간절연막(9)을 형성하고 나서, 상기 제 2층간절연막(9)을 식각하여 상기 금속배선(7)의 일부위를 노출시키는 제 2콘택홀(10)을 형성한다. 이후, 제 2콘택홀(10)을 포함한 기판 전면에 제 1베리어금속막(11) 및 제 2금속막(13)을 차례로 형성한다. 이때, 상기 제 1베리어금속막(11)으로는 Ti/TiN막을 사용하고, 제 2금속막(13)으로는 텅스텐막을 이용한다. In the method of forming the metal wiring according to the present invention, as shown in FIG. 2A, after forming the first interlayer insulating film 3 on the semiconductor substrate 1 having a predetermined substructure, the first interlayer insulating film is formed. Selectively etching to form a first contact hole 4 to expose a portion of the substrate. Subsequently, after forming a first metal film (not shown) on the entire surface of the substrate including the first contact hole 4, the first metal wire 7 covering the first contact hole 4 by etching the first metal film 7. ). Then, after forming the second interlayer insulating film 9 on the substrate including the first metal wiring 7, the second interlayer insulating film 9 is etched to expose a portion of the metal wiring 7. The second contact hole 10 is formed. Thereafter, the first barrier metal film 11 and the second metal film 13 are sequentially formed on the entire surface of the substrate including the second contact hole 10. In this case, a Ti / TiN film is used as the first barrier metal film 11 and a tungsten film is used as the second metal film 13.

그런 다음, 도 2b에 도시된 바와 같이, 제 2층간절연막이 노출되는 시점까지 제 2금속막 및 제 1베리어금속막을 전면식각하여 제 2콘택홀을 매립시키는 제 1플러그(14)를 형성한다. 이때, 도 2b에서 미설명된 도면부호 12는 제 2콘택홀 내부에 잔류된 베리어금속막을 나타낸 것이다.Then, as illustrated in FIG. 2B, the first plug 14 may be formed by completely etching the second metal film and the first barrier metal film until the second interlayer insulating film is exposed to fill the second contact hole. In this case, reference numeral 12, which is not described in FIG. 2B, indicates the barrier metal film remaining inside the second contact hole.

이후, 도 2c에 도시된 바와 같이, 상기 제 1 플러그(14)를 포함한 기판 전면에 제 2금속막(미도시)을 형성하고 나서, 상기 제 2금속막을 선택 식각하여 상기 제 1플러그(14)와 연결되는 제 2금속배선(15)을 형성한다.Thereafter, as shown in FIG. 2C, a second metal film (not shown) is formed on the entire surface of the substrate including the first plug 14, and then the second metal film is selectively etched to form the first plug 14. A second metal wiring 15 is formed to be connected to the metal wire.

이어, 도 2d에 도시된 바와 같이, 상기 제 2금속배선(15)을 포함한 기판 전면에 제 3층간절연막(17)을 형성한다. 이때, 제 3층간절연막(17)은 다중층이 적층된 구조를 가지며, 화학기상증착공정으로 절연막을 형성하고 나서, 그 위에 충전력(step coverage)이 우수한 SOG(Spin On Glass)를 4000∼5000Å두께로 형성하고, 다시 화학기상증착공정으로 절연막을 형성한다. 그런다음, 상기 제 3층간절연막(17)에 열처리(31)를 진행하여 평탄화시킨다. 여기서, 상기 열처리(31)공정은 400∼500℃ 온도에서 30분∼1시간동안 진행한다.Next, as shown in FIG. 2D, a third interlayer insulating film 17 is formed on the entire surface of the substrate including the second metal wiring 15. At this time, the third interlayer insulating film 17 has a structure in which multiple layers are stacked, and after forming an insulating film by chemical vapor deposition, a SOG (Spin On Glass) having excellent step coverage is formed thereon. It is formed to a thickness, and then an insulating film is formed by chemical vapor deposition. Then, heat treatment 31 is performed to planarize the third interlayer insulating film 17. Here, the heat treatment step 31 is performed for 30 minutes to 1 hour at 400 ~ 500 ℃ temperature.

이후, 도 2e에 도시된 바와 같이, 제 3층간절연막(17)을 선택 식각하여 상기 제 2금속배선(15)의 일부위를 노출시키는 제 3콘택홀(18)을 형성한다. 이어, 상기 결과물 상에 제 2베리어금속막(19) 및 제 3금속막을 차례로 형성한 후, 제 3층간절연막(17)이 노출되는 시점까지 상기 제 3금속막 및 제 2베리어금속막(19)을 전면 식각하여 제 3콘택홀(18)을 매립시키는 제 2플러그(21)를 형성한다. 이때, 상기 제 2베리어금속막(19)으로는 Ti/TiN막을 사용하고, 제 3금속막으로는 텅스텐막을 이용한다.Thereafter, as shown in FIG. 2E, the third interlayer insulating layer 17 is selectively etched to form a third contact hole 18 exposing a portion of the second metal wiring 15. Subsequently, after the second barrier metal film 19 and the third metal film are sequentially formed on the resultant material, the third metal film and the second barrier metal film 19 are formed until the third interlayer insulating film 17 is exposed. The entire surface is etched to form a second plug 21 to fill the third contact hole 18. In this case, a Ti / TiN film is used as the second barrier metal film 19, and a tungsten film is used as the third metal film.

그런다음, 상기 결과의 제 3층간절연막(17) 위에 제 4금속막을 형성하고 나서, 상기 제 4금속막을 선택 식각하여 제 2플러그(21)와 연결되는 제 3금속배선(23)을 형성한다.Then, a fourth metal film is formed on the resultant third interlayer insulating film 17, and then the fourth metal film is selectively etched to form a third metal wiring 23 connected to the second plug 21.

본 발명에 따르면, 제 1금속배선을 포함한 층간절연막 위에 상기 제 1금속배선의 일부위를 노출시키는 콘택홀을 형성한 후, 베리어금속막을 개재시켜 상기 콘택홀을 매립시키는 플러그를 형성하고, 플러그와 연결되는 제 2금속배선을 형성함으로써, 층간절연막 상에 베리어금속막이 존재하지 않게 되어 다중 금속배선의 전체 두께를 감소시켜 단차 감소 및 층간절연막의 평탄화도를 개선할 수 있다. According to the present invention, after forming a contact hole exposing a portion of the first metal wiring on the interlayer insulating film including the first metal wiring, a plug for embedding the contact hole is formed through a barrier metal film, and the plug and By forming the second metal wiring to be connected, the barrier metal film does not exist on the interlayer insulating film, thereby reducing the overall thickness of the multi-metal wiring, thereby reducing the level difference and improving the planarization of the interlayer insulating film.

상술한 바와 같이, 본 발명은 층간절연막 내에 베리어금속막을 개재시켜 플러그를 형성한 후, 플러그와 연결되는 금속배선을 형성함으로써, 층간절연막 상에 베리어금속막이 존재하지 않게 되어 결과적으로 다중 금속배선의 전체 두께를 감소 시킬 수 있다. 따라서, 단차감소로 인해 층간절연막의 평탄도가 개선되며, 후속의 제 3금속배선용 금속막을 전면식각하는 공정에서 레지듀가 발생되지 않아 브릿지 현상이 개선된다.As described above, the present invention forms a plug by interposing a barrier metal film in the interlayer insulating film, and then forms a metal wiring connected to the plug, so that the barrier metal film does not exist on the interlayer insulating film. The thickness can be reduced. Therefore, the flatness of the interlayer insulating film is improved due to the step difference reduction, and the bridge phenomenon is improved because no residue is generated in the subsequent etching of the third metal wiring metal film.

또한, 본 발명은 베리어금속막을 개재시켜 플러그를 형성하고 나서, 플러그와 연결되도록 제 2금속배선을 형성함으로써, 베리어금속막 식각에 따른 제2금속배선의 면저항의 저하가 없기 때문에 디바이스의 속도 특성은 영향을 받지 않으며, 이로써 디바이스의 신뢰성이 향상된 이점이 있다.In addition, the present invention forms the plug through the barrier metal film, and then forms the second metal wiring so as to be connected to the plug, so that there is no decrease in the sheet resistance of the second metal wiring due to the etching of the barrier metal film. It is not affected, and this improves the reliability of the device.

Claims (4)

제 1금속배선을 구비한 반도체기판을 제공하는 단계와,Providing a semiconductor substrate having a first metal wiring; 상기 기판 상에 상기 제 1금속배선의 일부위를 노출시키는 제 1콘택홀을 가진 제 1절연막을 형성하는 단계와,Forming a first insulating film having a first contact hole exposing a portion of the first metal wiring on the substrate; 상기 제 1콘택홀을 포함한 기판 전면에 제 1베리어금속막 및 제 1금속막을 차례로 형성하는 단계와,Sequentially forming a first barrier metal film and a first metal film on the entire surface of the substrate including the first contact hole; 상기 제 1절연막이 노출되는 시점까지 상기 제 1금속막 및 제 1베리어금속막을 전면 식각하여 제 1콘택홀을 매립시키는 제 1플러그를 형성하는 단계와,Forming a first plug to bury the first contact hole by etching the first metal layer and the first barrier metal layer to the entire surface until the first insulating layer is exposed; 상기 제 1층간절연막 상에 상기 제 1플러그와 연결되는 제 2금속배선을 형성하는 단계와,Forming a second metal wiring connected to the first plug on the first interlayer insulating film; 상기 제 2금속배선을 포함한 기판 전면에 충전막을 형성하는 단계와,Forming a filling film on the entire surface of the substrate including the second metal wiring; 상기 충전막에 열처리를 실시하여 평탄화하는 단계와,Performing heat treatment to the filling film to planarize; 상기 평탄화된 충전막을 선택식각하여 상기 제 2금속배선의 일부위를 노출시키는 제 2콘택홀을 형성하는 단계와,Selectively etching the planarized filling film to form a second contact hole exposing a portion of the second metal wiring; 상기 제 2콘택홀을 포함한 기판 전면에 제 2베리어금속막 및 제 2금속막을 차례로 형성하는 단계와,Sequentially forming a second barrier metal film and a second metal film on the entire surface of the substrate including the second contact hole; 상기 충전막이 노출되는 시점까지 상기 제 2금속막 및 제 2베리어금속막을 전면 식각하여 제 2콘택홀을 매립시키는 제 2플러그를 형성하는 단계와,Forming a second plug to completely etch the second metal layer and the second barrier metal layer to fill the second contact hole until the charge layer is exposed; 상기 충전막 상에 상기 제 2플러그와 연결되는 제 3금속배선을 형성하는 단계를 포함한 것을 특징으로 하는 금속배선의 형성방법.And forming a third metal wiring connected to the second plug on the filling film. 제 1항에 있어서, 상기 충전막은 SOG를 이용하는 것을 특징으로 하는 금속배선의 형성방법.The method of claim 1, wherein the filling film is made of SOG. 제 2항에 있어서, 상기 SOG는 4000∼5000Å두께로 형성하는 것을 특징으로 하는 금속배선의 형성방법.The method of claim 2, wherein the SOG is formed to a thickness of 4000 to 5000 kPa. 제 1항에 있어서, 상기 열처리공정은 400∼500℃ 온도에서 30분∼1시간동안 진행하는 것을 특징으로 하는 금속배선의 형성방법.The method of claim 1, wherein the heat treatment is performed at 400 to 500 ° C. for 30 minutes to 1 hour.
KR1020040057316A 2004-07-22 2004-07-22 Method for fabricating metal line KR100608367B1 (en)

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