KR100600261B1 - Method of forming a capacitor in a semiconductor device - Google Patents

Method of forming a capacitor in a semiconductor device Download PDF

Info

Publication number
KR100600261B1
KR100600261B1 KR1019990065173A KR19990065173A KR100600261B1 KR 100600261 B1 KR100600261 B1 KR 100600261B1 KR 1019990065173 A KR1019990065173 A KR 1019990065173A KR 19990065173 A KR19990065173 A KR 19990065173A KR 100600261 B1 KR100600261 B1 KR 100600261B1
Authority
KR
South Korea
Prior art keywords
film
capacitor
forming
semiconductor device
temperature
Prior art date
Application number
KR1019990065173A
Other languages
Korean (ko)
Other versions
KR20010065300A (en
Inventor
송한상
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019990065173A priority Critical patent/KR100600261B1/en
Publication of KR20010065300A publication Critical patent/KR20010065300A/en
Application granted granted Critical
Publication of KR100600261B1 publication Critical patent/KR100600261B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로, Ta2O5를 유전체막으로 사용하는 캐패시터의 하부 전극에 귀금속인 Pt 막을 이용하고, 산소 확산방지막으로 Ru막 및 산화물 전극인 RuOx막을 이용하므로 산소확산으로 인한 유효 산화막 두께의 증가 및 누설전류가 발생을 방지할 수 있으며 폴리실리콘을 전극물질로 이용하는 경우와 비교하여 캐패시터의 전하저장용량의 변화를 감소 시킬 수 있는 반도체 소자의 캐패시터 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device. The Pt film, which is a noble metal, is used as the lower electrode of a capacitor that uses Ta 2 O 5 as a dielectric film, and the Ru film and the RuO x film, which is an oxide electrode, are used as an oxygen diffusion barrier. A method of forming a capacitor in a semiconductor device that can prevent an increase in effective oxide film thickness and leakage current due to oxygen diffusion and can reduce a change in charge storage capacity of a capacitor as compared with the case of using polysilicon as an electrode material. will be.

캐패시터, RuO2막, Ta2O5막Capacitor, RuO2 Film, Ta2O5 Film

Description

반도체 소자의 캐패시터 형성방법{Method of forming a capacitor in a semiconductor device} Method of forming a capacitor in a semiconductor device             

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 캐패시터 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a capacitor of a semiconductor device according to the present invention.

〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>

10 : 반도체 기판 11 : 산화막10 semiconductor substrate 11 oxide film

12 : 폴리실리콘막 13 : 베리어막12 polysilicon film 13 barrier film

14 : Ru막 15 : RuO2막14: Ru film 15: RuO 2 film

16 : 금속층 17 : Ta2O5막16: metal layer 17: Ta 2 O 5 film

18 : 상부전극18: upper electrode

본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로, 특히 Ta2O5를 유전체막으로 사용하여 누설전류를 개선 시킬 수 있는 반도체 소자의 캐패시터 형성방법에 관한 것이다.The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly to a method of forming a capacitor of a semiconductor device that can improve the leakage current by using Ta 2 O 5 as a dielectric film.

최근에 질화막/산화막 구조의 전하저장전극의 한계를 극복하고자 Ta2O5 유전체막 전하저장전극의 개발이 이루어지고 있다. 그러나, Ta2O5 유전체막은 불안정한 화학양론비를 갖고 있기 때문에 Ta와 O의 조성비 차이에 기인한 치환형 Ta원자(Vacancy atom)가 유전체 내에 존재하게 된다. Recently, Ta 2 O 5 dielectric film charge storage electrodes have been developed to overcome the limitations of the charge storage electrodes of nitride / oxide structures. However, since the Ta 2 O 5 dielectric film has an unstable stoichiometric ratio, substitutional Ta atoms (Vacancy atoms) due to the difference in the composition ratio of Ta and O are present in the dielectric.

Ta2O5은 물질 자체의 불안정한 화학적 조성비 때문에 유전체 박막 내에 산소 공공(Oxygen vacancy) 상태의 치환형 Ta원자가 항시 국부적으로 존재할 수 밖에 없다. 특히, Ta2O5 유전체 박막의 산소공공의 수는 성분들의 함량과 결합정도에 따라 다소의 차이는 있을 수 있지만 완전하게 제거할 수 없다. 결과적으로 Ta2O5 유전체 박막의 불안정한 화학양론비를 안정화 시켜 누설전류를 방지하기 위하여 유전체 박막내에 잔존해 있는 치환형 Ta원자를 산화시키려는 별도의 산화공정이 필요하다. 그리고, 박막 형상시 Ta2O5 유전체 박막의 전구체(Precusor)인 Ta(OC2H 5)5의 유기물과 O2 또는 N2O 가스의 반응으로 인해서 불순물인 탄소원자와 탄소화합물(C, CH4, C2H4 등) 및 물(H2O)이 함께 존재하게 된다. 결국 Ta2O5 유전체 박막내에 불순물로 존재하는 탄소원자, 이온과 라디칼(Radical)로 인해서 전하저장전극에 누설 전류가 증가 하게 되고 유전 특성이 열화되는 문제점이 발생된다. Ta 2 O 5 is always localized in the substitutional Ta atoms in the oxygen vacancy state in the dielectric thin film due to the unstable chemical composition ratio of the material itself. In particular, the number of oxygen vacancies in the Ta 2 O 5 dielectric thin film may vary slightly depending on the content of the components and the degree of bonding, but cannot be completely removed. As a result, in order to stabilize the unstable stoichiometry of the Ta 2 O 5 dielectric thin film and prevent leakage current, a separate oxidation process is needed to oxidize the substituted Ta atoms remaining in the dielectric thin film. In addition, in the form of a thin film, carbon atoms and carbon compounds (C, CH, which are impurities) are formed due to the reaction of O 2 or N 2 O gas with an organic material of Ta (OC 2 H 5 ) 5 , which is a precursor of the Ta 2 O 5 dielectric thin film. 4 , C 2 H 4, etc.) and water (H 2 O) will be present together. As a result, the leakage current increases in the charge storage electrode and the dielectric property deteriorates due to the carbon atoms, ions, and radicals present as impurities in the Ta 2 O 5 dielectric thin film.

또한, 메모리 소자의 Ta2O5를 포함한 캐패시터 제조공정시 전하저장전극 물질로 폴리실리콘을 사용할 경우 유효산화막 두께를 30Å 이하로 감소시키는 것은 어렵다. 그러나, 금속을 전하저장전극의 재료로 사용할 경우 폴리실리콘과의 전기적 에너지 베리어(Energy barrier)가 크므로 누설 전류가 감소되며 유효산화막 두께를 감소시킬 수 있고, 바이어스 전압에 따른 전하저장용량 값의 변화가 작은 장점이 있다. In addition, when polysilicon is used as the charge storage electrode material in the capacitor manufacturing process including Ta 2 O 5 of the memory device, it is difficult to reduce the effective oxide film thickness to 30 占 Å or less. However, when metal is used as the material of the charge storage electrode, the leakage current is reduced and the effective oxide film thickness can be reduced since the electrical energy barrier with polysilicon is large. Has a small advantage.

귀금속(Noble metal)인 Pt를 전하저장전극으로 사용하는 경우 일반적으로 실리콘과 귀금속 사이에 Ti와 산소 확산 방지막인 TiN을 사용하게 된다. 그러나, 후속 열공정시 Pt를 통하여 산소확산이 발생하며 산소와 TiN이 반응하여 TiO 또는 TiON을 형성하고, 또한 하부의 폴리실리콘과 반응하여 SiO2 막을 형성하게 된다. 이러한 SiO2 막은 Ta2O5막과 함께 유전체 역할을 하게 되므로 전하저장용량을 크게 감소 시키는 문제점이 있다.When Pt, a noble metal, is used as a charge storage electrode, Ti and oxygen diffusion barrier TiN are generally used between silicon and the noble metal. However, in the subsequent thermal process, oxygen diffusion occurs through Pt, and oxygen and TiN react to form TiO or TiON, and also react with polysilicon below to form SiO 2 film. Since the SiO 2 film serves as a dielectric along with the Ta 2 O 5 film, there is a problem of greatly reducing the charge storage capacity.

따라서, 본 발명은 Ta2O5를 유전체 박막으로 하고 귀금속을 전하저장전극으로 이용할 경우 후속 열공정시 귀금속을 통한 산소의 확산을 방지하고 유효 산화막 두께를 감소시키며 누설 전류 등 전기적 특성을 개선 시킬 수 있는 반도체 소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다. Therefore, in the present invention, when Ta 2 O 5 is used as the dielectric thin film and the precious metal is used as the charge storage electrode, it is possible to prevent the diffusion of oxygen through the precious metal during the subsequent thermal process, to reduce the effective oxide thickness, and to improve the electrical characteristics such as leakage current. It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device.

상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 형성방법은 반도체 기판 상에 산화막을 형성한 후 상기 산화막 상에 폴리실리콘막, 베리어막 및 Ru막을 순차적으로 형성하는 단계; 상기 Ru막 상부면에 RuO2막 및 금속층을 순차적으로 형성하여 하부전극을 형성하는 단계; 상기 금속층 상부면에 유전체막을 형성한 후 1차 및 2 차 열공정을 실시하는 단계; 및 상기 유전체막인 상부면에 상부전극을 형성하는 단계를 포함하는 것을 특징으로 한다.
A method of forming a capacitor of a semiconductor device according to the present invention for achieving the above object comprises the steps of sequentially forming a polysilicon film, a barrier film and a Ru film on the oxide film after forming an oxide film on the semiconductor substrate; Sequentially forming a RuO 2 film and a metal layer on an upper surface of the Ru film to form a lower electrode; Performing a first and second thermal process after forming a dielectric film on the upper surface of the metal layer; And forming an upper electrode on an upper surface of the dielectric film.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 캐패시터 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for explaining a method of forming a capacitor of a semiconductor device according to the present invention.

도 1a를 참조하면, 반도체 기판(10) 상에 산화막(11)을 형성한 후 산화막(11) 상에 폴리실리콘막(12), 베리어막(13) 및 Ru막(14)을 순차적으로 형성한다.Referring to FIG. 1A, after the oxide film 11 is formed on the semiconductor substrate 10, the polysilicon film 12, the barrier film 13, and the Ru film 14 are sequentially formed on the oxide film 11. .

상기에서, 베리어막(13)은 Ti/TiN막으로 이루어진다. Ru막(14)은 플라즈마 기상증착방법으로 Ar가스분위기의 반응로에서 500 내지 2000Å 두께로 증착한다. 이때, 반응로 내에서 50 내지 200sccm의 Ar가스와, 2 내지 10 mtorr의 압력 및 250 내지 350℃의 온도에서 Ru막(14)을 증착하고, 플라즈마 전력은 500 내지 2000W를 유지한다.In the above, the barrier film 13 is made of a Ti / TiN film. The Ru film 14 is deposited to a thickness of 500 to 2000 kPa in an Ar gas atmosphere reactor by a plasma vapor deposition method. At this time, an Ar gas of 50 to 200 sccm, a pressure of 2 to 10 mtorr, and a Ru film 14 are deposited at a temperature of 250 to 350 ° C. in the reactor, and plasma power is maintained at 500 to 2000 W.

도 1b를 참조하면, Ru막(14) 상부면에 RuO2막(15) 및 금속층(16)을 형성하여 하부전극을 형성한다.Referring to FIG. 1B, a RuO 2 film 15 and a metal layer 16 are formed on an upper surface of the Ru film 14 to form a lower electrode.

상기에서, RuO2막(15)은 플라즈마 기상증착방법으로 50 내지 200sccm 유량의 O2가스 분위기의 반응로에서 1500 내지 2500Å 두께로 증착한다. 이때, 반응로 내는 2 내지 10 mtorr의 압력 및 200 내지 250℃의 온도를 유지하고, 플라즈마 전력은 500 내지 2000W 로 설정한다.In the above, the RuO 2 film 15 is deposited to a thickness of 1500 to 2500 kPa in an O 2 gas atmosphere at a flow rate of 50 to 200 sccm by a plasma vapor deposition method. At this time, the inside of the reactor maintains a pressure of 2 to 10 mtorr and a temperature of 200 to 250 ℃, the plasma power is set to 500 to 2000W.

금속층(16)은 플라즈마 기상증착방법으로 Ar가스 분위기의 반응로에서 Pt 막을 1000 내지 2000Å 두께로 증착한다. 이때, 반응로 내는 10 내지 100sccm 유량의 Ar가스를 주입하고, 1 내지 5 mtorr의 압력 및 400 내지 550℃의 온도를 유지하고, 플라즈마 전력은 1000 내지 2000W로 설정한다.The metal layer 16 is deposited to a thickness of 1000 to 2000 kPa in a Pt film in an Ar gas atmosphere by a plasma vapor deposition method. At this time, the inside of the reactor is injected with Ar gas at a flow rate of 10 to 100 sccm, maintaining a pressure of 1 to 5 mtorr and a temperature of 400 to 550 ° C, and plasma power is set to 1000 to 2000W.

도 1c를 참조하면, 금속층(16) 상부면에 유전체막인 Ta2O5막(17)을 형성한 후 1 차 및 2 차 열공정을 실시한다. 그후 유전체막인 Ta2O5막(17) 상부면에 상부전극(18)을 형성한다.Referring to FIG. 1C, after forming a Ta 2 O 5 film 17 as a dielectric film on an upper surface of the metal layer 16, primary and secondary thermal processes are performed. After that, the upper electrode 18 is formed on the upper surface of the Ta 2 O 5 film 17 which is a dielectric film.

상기에서, Ta2O5막(17)은 원료물질로 Ta(C2H5O)5 (tantalum etoxide)를 사용하고, 반응로에서 반응원료의 운반가스로 350 내지 450 sccm 유량의 N2가스를, 산화제로는 20 내지 50sccm 유량의 O2가스를 이용한다. 이때, 반응로 내는 0.1 내지 0.6 torr 의 압력 및 350 내지 450℃의 온도를 유지한다.In the above, the Ta 2 O 5 membrane 17 uses Ta (C 2 H 5 O) 5 (tantalum etoxide) as a raw material, and a N 2 gas at a flow rate of 350 to 450 sccm as a carrier gas of the reaction raw material in the reactor. As the oxidant, O 2 gas at a flow rate of 20 to 50 sccm is used. At this time, the reaction furnace maintains a pressure of 0.1 to 0.6 torr and a temperature of 350 to 450 ℃.

유전체막인 Ta2O5막(17) 대신에 (BaxSr1-x)TiO3(BST) 또는 (PbxZr1-x)TiO3(PZT) 와 같은 강유전체를 이용할 수 있다.Instead of the Ta 2 O 5 film 17 serving as the dielectric film, a ferroelectric such as (Ba x Sr 1-x ) TiO 3 (BST) or (Pb x Zr 1-x ) TiO 3 (PZT) may be used.

1차 열공정은 N2O 플라즈마를 이용하여 300 내지 400℃에서 실시하고, 2차 열공정은 N2 가스 반응로를 이용하여 500 내지 650℃에서 실시한다.The primary thermal process is performed at 300 to 400 ° C using N 2 O plasma, and the secondary thermal process is performed at 500 to 650 ° C using N 2 gas reactor.

상부 전극(18)은 플라즈마 기상증착방법으로 Ar가스 분위기의 반응로에서 Pt막을 1000 내지 2000Å 두께로 증착한다. 이때, 반응로 내는 10 내지 100sccm 유량의 Ar가스를 주입하고, 1 내지 5 mtorr의 압력 및 400 내지 550℃의 온도를 유지하고, 플라즈마 전력은 1000 내지 2000W로 설정한다.The upper electrode 18 is a plasma vapor deposition method to deposit a Pt film in a thickness of 1000 to 2000 kPa in an Ar gas atmosphere reactor. At this time, the inside of the reactor is injected with Ar gas at a flow rate of 10 to 100 sccm, maintaining a pressure of 1 to 5 mtorr and a temperature of 400 to 550 ° C, and plasma power is set to 1000 to 2000W.

상술한 바와같이 본 발명은 하부 전극으로 귀금속인 Pt 막을 이용하고, 산소 확산방지막으로 Ru막 및 산화물 전극인 RuOx막을 이용하므로 산소확산으로 인한 유효 산화막 두께의 증가 및 누설전류가 발생을 방지할 수 있으며 폴리실리콘을 전극물질로 이용하는 경우와 비교하여 캐패시터의 전하저장용량의 변화값이 감소 되는 효과가 있다.


As described above, the present invention uses a Pt film, a precious metal, as the lower electrode, and a Ru film and a RuO x film, an oxide electrode, to prevent an increase in effective oxide film thickness and leakage current due to oxygen diffusion. Compared with the case of using polysilicon as an electrode material, the change value of the charge storage capacity of the capacitor is reduced.


Claims (8)

반도체 기판 상에 산화막, 폴리실리콘막, 베리어막을 순차적으로 형성하는 단계;Sequentially forming an oxide film, a polysilicon film, and a barrier film on the semiconductor substrate; 상기 베리어막 상부에 플라즈마 기상증착법을 이용하여 Ru막, RuO2막 및 금속층을 순차적으로 형성하여 하부전극을 형성하는 단계;Forming a lower electrode by sequentially forming a Ru film, a RuO 2 film, and a metal layer on the barrier film by using a plasma vapor deposition method; 상기 금속층 상부면에 유전체막을 형성한 후, N2O 플라즈마를 이용한 1차 열공정 및 N2 가스를 이용한 2 차 열공정을 실시하는 단계; 및Forming a dielectric film on the upper surface of the metal layer, and then performing a first thermal process using N 2 O plasma and a second thermal process using N 2 gas; And 상기 유전체막인 상부면에 상부전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.And forming an upper electrode on an upper surface of the dielectric film. 제 1 항에 있어서,The method of claim 1, 상기 베리어막은 Ti/TiN막으로 이루어진 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.And the barrier film is formed of a Ti / TiN film. 제 1 항에 있어서,The method of claim 1, 상기 Ru막은 50 내지 200sccm의 Ar가스 분위기와 2 내지 10 mtorr의 압력 및 250 내지 350℃의 온도의 반응로에서 500 내지 2000W의 전력하에서 500 내지 2000Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법. The Ru film is formed of a capacitor of a semiconductor device, characterized in that the thickness of 500 to 2000 kW under a power of 500 to 2000W in a reactor of Ar gas atmosphere of 50 to 200sccm, pressure of 2 to 10 mtorr and temperature of 250 to 350 ℃ Way. 제 1 항에 있어서,The method of claim 1, 상기 RuO2막은 2 내지 10 mtorr의 압력 및 200 내지 250℃의 온도와 50 내지 200sccm 유량의 O2가스 분위기의 반응로에서 500 내지 2000W 전력하에서 1500 내지 2500Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The RuO 2 film is formed at a thickness of 1500 to 2500 kW under a power of 500 to 2000 W in a reactor at a pressure of 2 to 10 mtorr, a temperature of 200 to 250 ° C., and an O 2 gas atmosphere at a flow rate of 50 to 200 sccm. Capacitor Formation Method. 제 1 항에 있어서,The method of claim 1, 상기 금속층 및 상부전극은 1 내지 5 mtorr의 압력 및 400 내지 550℃의 온도와 10 내지 100sccm 유량의 Ar가스 분위기의 반응로에서 1000 내지 2000W 전력하에서 Pt막을 1000 내지 2000Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The metal layer and the upper electrode is characterized in that to form a Pt film 1000 to 2000 kW thick under a power of 1000 to 2000W in a reactor of Ar gas atmosphere at a pressure of 1 to 5 mtorr, a temperature of 400 to 550 ℃ and a flow rate of 10 to 100 sccm A method for forming a capacitor of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 유전체막은 Ta2O5막, (BaxSr1-x)TiO3(BST)막 또는 (PbxZr1-x)TiO3(PZT)막 중 어느 하나인 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The dielectric film may be a Ta 2 O 5 film, a (Ba x Sr 1-x ) TiO 3 (BST) film, or a (Pb x Zr 1-x ) TiO 3 (PZT) film. Formation method. 제 1 항에 있어서,The method of claim 1, 상기 1차 열공정은 300 내지 400℃ 의 온도하에서 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The first thermal process is a capacitor forming method of a semiconductor device, characterized in that performed at a temperature of 300 to 400 ℃. 제 1 항에 있어서,The method of claim 1, 상기 2차 열공정은 500 내지 650℃ 의 온도하에서 실시하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The secondary thermal process is a capacitor forming method of a semiconductor device, characterized in that performed at a temperature of 500 to 650 ℃.
KR1019990065173A 1999-12-29 1999-12-29 Method of forming a capacitor in a semiconductor device KR100600261B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990065173A KR100600261B1 (en) 1999-12-29 1999-12-29 Method of forming a capacitor in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990065173A KR100600261B1 (en) 1999-12-29 1999-12-29 Method of forming a capacitor in a semiconductor device

Publications (2)

Publication Number Publication Date
KR20010065300A KR20010065300A (en) 2001-07-11
KR100600261B1 true KR100600261B1 (en) 2006-07-13

Family

ID=19632377

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990065173A KR100600261B1 (en) 1999-12-29 1999-12-29 Method of forming a capacitor in a semiconductor device

Country Status (1)

Country Link
KR (1) KR100600261B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100798788B1 (en) * 2001-12-14 2008-01-29 주식회사 하이닉스반도체 Method for forming ruthenium storage node of semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997003468A1 (en) * 1995-07-07 1997-01-30 Rohm Co., Ltd. Dielectric capacitor and process for preparing the same
KR100200755B1 (en) * 1996-11-13 1999-06-15 윤종용 Structure of multiple layer electrode
KR19990042449A (en) * 1997-11-26 1999-06-15 김영환 Capacitor Manufacturing Method of Semiconductor Device
KR100228355B1 (en) * 1996-12-30 1999-11-01 김영환 Manufacturing method for memory cell

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997003468A1 (en) * 1995-07-07 1997-01-30 Rohm Co., Ltd. Dielectric capacitor and process for preparing the same
KR100200755B1 (en) * 1996-11-13 1999-06-15 윤종용 Structure of multiple layer electrode
KR100228355B1 (en) * 1996-12-30 1999-11-01 김영환 Manufacturing method for memory cell
KR19990042449A (en) * 1997-11-26 1999-06-15 김영환 Capacitor Manufacturing Method of Semiconductor Device
KR100275332B1 (en) * 1997-11-26 2000-12-15 김영환 Manufacturing method of capacitor of the semicondutor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
1002753320000
1019990042449

Also Published As

Publication number Publication date
KR20010065300A (en) 2001-07-11

Similar Documents

Publication Publication Date Title
EP1368822B1 (en) Rhodium-rich oxygen barriers
KR100351056B1 (en) Method of manufacturing semiconductor device including step of selectively forming metal oxide layer
TW517330B (en) Capacitor of semiconductor device and its manufacturing method
KR100422565B1 (en) Method of forming a capacitor of a semiconductor device
JP2001237400A (en) Method of manufacturing capacitor of semiconductor device
JP2001203330A (en) Method of making capacitor in semiconductor device
KR100390938B1 (en) Method of manufacturing a capacitor in a semiconductor device
JP2004056142A (en) Substance forming method using atomic layer deposition method and semiconductor device capacitor forming method using the above method
KR100494322B1 (en) Method of manufacturing a capacitor in a semiconductor device
KR100497142B1 (en) Method of manufacturing a capacitor in a semiconductor device
KR100373159B1 (en) Method of manufacturing a capacitor in a semiconductor device
KR20020083772A (en) capacitor of semiconductor device and method for fabricating the same
KR20040008527A (en) Method of semiconductor device
KR100424710B1 (en) Fabricating method of semiconductor device
KR100600261B1 (en) Method of forming a capacitor in a semiconductor device
JP4223248B2 (en) Dielectric film forming method for semiconductor device
JPH0786270A (en) Formation of metal oxide film
JP4812164B2 (en) Capacitor manufacturing method for semiconductor device
KR100624904B1 (en) Method of manufacturing a capacitor in a semiconductor device
KR100882090B1 (en) Method for fabricating capacitor of semiconductor device
KR100293721B1 (en) Capacitor manufacturing method having a tantalum oxide film as a dielectric film
KR20010017212A (en) Method of manufacturing a capacitor in a semiconductor device
KR100604664B1 (en) Capacitor with double dielectric and method for manufacturing the same
KR20020016313A (en) Method for manufactruing capacitor in semiconductor device
KR100671605B1 (en) Method of manufacturing a capacitor in a semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100624

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee